44#define MEMORY_ATTRIBUTE_DEFAULT (EFI_RESOURCE_ATTRIBUTE_PRESENT | \
45 EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \
46 EFI_RESOURCE_ATTRIBUTE_TESTED | \
47 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | \
48 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | \
49 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | \
50 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE )
52#define ROOT_BRIDGE_SUPPORTS_DEFAULT (EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 | \
53 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | \
54 EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 | \
55 EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO | \
56 EFI_PCI_IO_ATTRIBUTE_VGA_IO | \
57 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | \
58 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | \
59 EFI_PCI_IO_ATTRIBUTE_ISA_IO | \
60 EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO )
64INT32 mNode[0x500] = { 0 };
86 IN VOID *EfiMemoryBottom,
87 IN VOID *EfiMemoryTop,
88 IN VOID *EfiFreeMemoryBottom,
89 IN VOID *EfiFreeMemoryTop
102 DEBUG ((DEBUG_INFO,
"\n RecordMemoryNode %x , mNodeIndex :%x \n", Node, mNodeIndex));
103 mNode[mNodeIndex] = Node;
122 for (i = 0; i < mNodeIndex; i++) {
123 if (mNode[i] == Node) {
145 DEBUG ((DEBUG_INFO,
"\n CheckNodeType %a \n", NodeString));
147 return ReservedMemory;
153 return PciRootBridge;
154 }
else if (
AsciiStrCmp (NodeString,
"options") == 0) {
175 UINT32 ECCData, ECCData2;
179 CONST CHAR8 *TempStr;
183 UINT64 NumberOfBytes;
185 Attribute = MEMORY_ATTRIBUTE_DEFAULT;
187 ECCData = ECCData2 = 0;
192 Data64 = (UINT64 *)(PropertyPtr->Data);
195 }
else if (
AsciiStrCmp (TempStr,
"ecc-detection-bits") == 0) {
196 Data32 = (UINT32 *)(PropertyPtr->Data);
198 }
else if (
AsciiStrCmp (TempStr,
"ecc-correction-bits") == 0) {
199 Data32 = (UINT32 *)(PropertyPtr->Data);
204 if (ECCData == ECCData2) {
206 ECCAttribute = EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC;
207 }
else if (ECCData == 2) {
208 ECCAttribute = EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC;
212 if (ECCAttribute != 0) {
213 Attribute |= ECCAttribute;
233 CONST CHAR8 *TempStr;
237 UINT64 NumberOfBytes;
243 PlatformAcpiTable =
NULL;
247 DEBUG ((DEBUG_INFO,
"\n SubNode(%08X) %a", SubNode, NodePtr->Name));
249 ASSERT (TempLen > 0);
250 TempStr = (CHAR8 *)(PropertyPtr->Data);
252 Data64 = (UINT64 *)(PropertyPtr->Data);
255 DEBUG ((DEBUG_INFO,
"\n Property %a", TempStr));
256 DEBUG ((DEBUG_INFO,
" %016lX %016lX\n", StartAddress, NumberOfBytes));
262 DEBUG ((DEBUG_INFO,
" MemoryMappedIO"));
265 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"compatible", &TempLen);
266 TempStr = (CHAR8 *)(PropertyPtr->Data);
267 DEBUG ((DEBUG_INFO,
"compatible: %a\n", TempStr));
269 DEBUG ((DEBUG_INFO,
" boot-code\n"));
272 DEBUG ((DEBUG_INFO,
" boot-data\n"));
275 DEBUG ((DEBUG_INFO,
" runtime-code\n"));
278 DEBUG ((DEBUG_INFO,
" runtime-data\n"));
281 Attribute = MEMORY_ATTRIBUTE_DEFAULT | EFI_RESOURCE_ATTRIBUTE_SPECIAL_PURPOSE;
282 DEBUG ((DEBUG_INFO,
" special-purpose memory\n"));
285 DEBUG ((DEBUG_INFO,
"\n ********* acpi-nvs ********\n"));
288 DEBUG ((DEBUG_INFO,
" acpi, StartAddress:%x, NumberOfBytes:%x\n", StartAddress, NumberOfBytes));
291 if (PlatformAcpiTable !=
NULL) {
292 DEBUG ((DEBUG_INFO,
" build gUniversalPayloadAcpiTableGuid , NumberOfBytes:%x\n", NumberOfBytes));
294 PlatformAcpiTable->Header.Revision = UNIVERSAL_PAYLOAD_ACPI_TABLE_REVISION;
298 DEBUG ((DEBUG_INFO,
" build smbios, NumberOfBytes:%x\n", NumberOfBytes));
301 if (SmbiosTable !=
NULL) {
302 SmbiosTable->Header.Revision = UNIVERSAL_PAYLOAD_SMBIOS_TABLE_REVISION;
330 CONST CHAR8 *TempStr;
332 UINT64 FrameBufferBase;
333 UINT32 FrameBufferSize;
342 ASSERT (GraphicsInfo !=
NULL);
343 if (GraphicsInfo ==
NULL) {
353 Data32 = (UINT32 *)(PropertyPtr->Data);
356 GraphicsInfo->FrameBufferBase = FrameBufferBase;
357 GraphicsInfo->FrameBufferSize = (UINT32)FrameBufferSize;
359 Data32 = (UINT32 *)(PropertyPtr->Data);
362 Data32 = (UINT32 *)(PropertyPtr->Data);
365 TempStr = (CHAR8 *)(PropertyPtr->Data);
368 }
else if (
AsciiStrCmp (TempStr,
"a8b8g8r8") == 0) {
373 }
else if (
AsciiStrCmp (TempStr,
"display") == 0) {
374 GmaStr = (CHAR8 *)(PropertyPtr->Data);
376 DEBUG ((DEBUG_INFO,
" display (%s)", GmaStr));
395 OUT UINT8 *PciEnumDone,
403 CONST CHAR8 *TempStr;
408 UINT8 SizeOfMemorySpace;
412 DEBUG ((DEBUG_INFO,
"\n SubNode(%08X) %a", SubNode, NodePtr->Name));
415 DEBUG ((DEBUG_INFO,
" Found image@ node \n"));
420 ASSERT (PayloadBase !=
NULL);
421 if (PayloadBase ==
NULL) {
425 PayloadBase->Header.Revision = UNIVERSAL_PAYLOAD_BASE_REVISION;
430 ASSERT (TempLen > 0);
432 Data64 = (UINT64 *)(PropertyPtr->Data);
434 DEBUG ((DEBUG_INFO,
"\n Property(00000000) entry"));
435 DEBUG ((DEBUG_INFO,
" %016lX\n", StartAddress));
442 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"addr-width", &TempLen);
444 Data32 = (UINT32 *)(PropertyPtr->Data);
445 DEBUG ((DEBUG_INFO,
"\n Property(00000000) address_width"));
447 SizeOfMemorySpace = (UINT8)
Fdt32ToCpu (*Data32);
451 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"pci-enum-done", &TempLen);
454 DEBUG ((DEBUG_INFO,
" Found PciEnumDone (%08X)\n", *PciEnumDone));
457 DEBUG ((DEBUG_INFO,
" Not Found PciEnumDone \n"));
460 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"boot-mode", &TempLen);
462 TempStr = (CHAR8 *)(PropertyPtr->Data);
464 *BootMode = BOOT_WITH_FULL_CONFIGURATION;
466 *BootMode = BOOT_WITH_MINIMAL_CONFIGURATION;
468 *BootMode = BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS;
469 }
else if (
AsciiStrCmp (TempStr,
"default") == 0) {
470 *BootMode = BOOT_WITH_DEFAULT_SETTINGS;
472 *BootMode = BOOT_ON_S4_RESUME;
474 *BootMode = BOOT_ON_S3_RESUME;
499 DEBUG ((DEBUG_INFO,
" Found gma@ node \n"));
505 ASSERT (GraphicsDev !=
NULL);
506 if (GraphicsDev ==
NULL) {
511 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"vendor-id", &TempLen);
512 ASSERT (TempLen > 0);
514 Data32 = (UINT32 *)(PropertyPtr->Data);
516 DEBUG ((DEBUG_INFO,
"\n vendor-id"));
517 DEBUG ((DEBUG_INFO,
" %016lX\n", GmaID));
521 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"device-id", &TempLen);
522 ASSERT (TempLen > 0);
524 Data32 = (UINT32 *)(PropertyPtr->Data);
526 DEBUG ((DEBUG_INFO,
"\n device-id"));
527 DEBUG ((DEBUG_INFO,
" %016lX\n", GmaID));
531 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"revision-id", &TempLen);
532 ASSERT (TempLen > 0);
534 Data32 = (UINT32 *)(PropertyPtr->Data);
536 DEBUG ((DEBUG_INFO,
"\n revision-id"));
537 DEBUG ((DEBUG_INFO,
" %016lX\n", GmaID));
541 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"subsystem-vendor-id", &TempLen);
542 ASSERT (TempLen > 0);
544 Data32 = (UINT32 *)(PropertyPtr->Data);
546 DEBUG ((DEBUG_INFO,
"\n subsystem-vendor-id"));
547 DEBUG ((DEBUG_INFO,
" %016lX\n", GmaID));
551 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"subsystem-id", &TempLen);
552 ASSERT (TempLen > 0);
554 Data32 = (UINT32 *)(PropertyPtr->Data);
556 DEBUG ((DEBUG_INFO,
"\n subsystem-id"));
557 DEBUG ((DEBUG_INFO,
" %016lX\n", GmaID));
577 CONST CHAR8 *TempStr;
585 ASSERT (Serial !=
NULL);
586 if (Serial ==
NULL) {
590 Serial->Header.Revision = UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO_REVISION;
592 Serial->RegisterStride = 1;
595 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"current-speed", &TempLen);
596 ASSERT (TempLen > 0);
598 Data32 = (UINT32 *)(PropertyPtr->Data);
603 PropertyPtr =
FdtGetProperty (Fdt, SubNode,
"compatible", &TempLen);
604 TempStr = (CHAR8 *)(PropertyPtr->Data);
606 DEBUG ((DEBUG_INFO,
" find serial compatible isa \n"));
609 ASSERT (TempLen > 0);
611 Data32 = (UINT32 *)(PropertyPtr->Data);
613 Serial->RegisterBase =
Fdt32ToCpu (*(Data32 + 1));
614 Serial->UseMmio = Attribute == 1 ?
FALSE :
TRUE;
615 DEBUG ((DEBUG_INFO,
"\n in espi serial Property() %a", TempStr));
616 DEBUG ((DEBUG_INFO,
" StartAddress %016lX\n", Serial->RegisterBase));
617 DEBUG ((DEBUG_INFO,
" Attribute %016lX\n", Attribute));
620 DEBUG ((DEBUG_INFO,
" NOT serial compatible isa \n"));
622 ASSERT (TempLen > 0);
624 Data32 = (UINT32 *)(PropertyPtr->Data);
644 IN UINT8 RootBridgeCount,
657 CONST CHAR8 *TempStr;
662 if (RootBridgeCount == 0) {
671 if (mPciRootBridgeInfo ==
NULL) {
672 mPciRootBridgeInfo =
BuildGuidHob (&gUniversalPayloadPciRootBridgeInfoGuid, HobDataSize);
673 ASSERT (mPciRootBridgeInfo !=
NULL);
674 if (mPciRootBridgeInfo ==
NULL) {
678 ZeroMem (mPciRootBridgeInfo, HobDataSize);
679 mPciRootBridgeInfo->Header.Length = (UINT16)HobDataSize;
680 mPciRootBridgeInfo->Header.Revision = UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION;
681 mPciRootBridgeInfo->Count = RootBridgeCount;
682 mPciRootBridgeInfo->ResourceAssigned =
FALSE;
685 if (mUplPciSegmentInfoHob ==
NULL) {
688 if (mUplPciSegmentInfoHob !=
NULL) {
689 ZeroMem (mUplPciSegmentInfoHob, HobDataSize);
690 mUplPciSegmentInfoHob->Header.Revision = UNIVERSAL_PAYLOAD_PCI_SEGMENT_INFO_REVISION;
691 mUplPciSegmentInfoHob->Header.Length = (UINT16)HobDataSize;
692 mUplPciSegmentInfoHob->Count = RootBridgeCount;
698 DEBUG ((DEBUG_INFO,
"\n SubNode(%08X) %a", SubNode, NodePtr->Name));
701 DEBUG ((DEBUG_INFO,
" Found gma@ node \n"));
720 DEBUG ((DEBUG_INFO,
" Found ranges Property TempLen (%08X), limit %x\n", TempLen, TempLen/
sizeof (UINT32)));
723 mPciRootBridgeInfo->RootBridge[RbIndex].
Supports = ROOT_BRIDGE_SUPPORTS_DEFAULT;
724 mPciRootBridgeInfo->RootBridge[RbIndex].
PMemAbove4G.Base =
PcdGet64 (PcdPciReservedPMemAbove4GBBase);
725 mPciRootBridgeInfo->RootBridge[RbIndex].
PMemAbove4G.Limit =
PcdGet64 (PcdPciReservedPMemAbove4GBLimit);
726 mPciRootBridgeInfo->RootBridge[RbIndex].
PMem.Base =
PcdGet32 (PcdPciReservedPMemBase);
727 mPciRootBridgeInfo->RootBridge[RbIndex].
PMem.Limit =
PcdGet32 (PcdPciReservedPMemLimit);
728 mPciRootBridgeInfo->RootBridge[RbIndex].
UID = RbIndex;
729 mPciRootBridgeInfo->RootBridge[RbIndex].
HID = EISA_PNP_ID (0x0A03);
731 Data32 = (UINT32 *)(PropertyPtr->Data);
732 for (Base = 0; Base < TempLen/
sizeof (UINT32); Base = Base + DWORDS_TO_NEXT_ADDR_TYPE) {
733 DEBUG ((DEBUG_INFO,
" Base :%x \n", Base));
735 if (((MemType) & (SS_64BIT_MEMORY_SPACE)) == SS_64BIT_MEMORY_SPACE) {
738 }
else if (((MemType) & (SS_32BIT_MEMORY_SPACE)) == SS_32BIT_MEMORY_SPACE) {
739 mPciRootBridgeInfo->RootBridge[RbIndex].
Mem.Base =
Fdt32ToCpu (*(Data32 + Base + 2));
740 mPciRootBridgeInfo->RootBridge[RbIndex].
Mem.Limit = mPciRootBridgeInfo->RootBridge[RbIndex].
Mem.Base +
Fdt32ToCpu (*(Data32 + Base + 6)) -1;
741 }
else if (((MemType) & (SS_IO_SPACE)) == SS_IO_SPACE) {
742 mPciRootBridgeInfo->RootBridge[RbIndex].
Io.Base =
Fdt32ToCpu (*(Data32 + Base + 2));
743 mPciRootBridgeInfo->RootBridge[RbIndex].
Io.Limit = mPciRootBridgeInfo->RootBridge[RbIndex].
Io.Base +
Fdt32ToCpu (*(Data32 + Base + 6)) -1;
747 DEBUG ((DEBUG_INFO,
"RootBridgeCount %x, index :%x\n", RootBridgeCount, RbIndex));
749 DEBUG ((DEBUG_INFO,
"PciRootBridge->Mem.Base %x, \n", mPciRootBridgeInfo->RootBridge[RbIndex].
Mem.Base));
750 DEBUG ((DEBUG_INFO,
"PciRootBridge->Mem.limit %x, \n", mPciRootBridgeInfo->RootBridge[RbIndex].
Mem.Limit));
752 DEBUG ((DEBUG_INFO,
"PciRootBridge->MemAbove4G.Base %llx, \n", mPciRootBridgeInfo->RootBridge[RbIndex].
MemAbove4G.Base));
753 DEBUG ((DEBUG_INFO,
"PciRootBridge->MemAbove4G.limit %llx, \n", mPciRootBridgeInfo->RootBridge[RbIndex].
MemAbove4G.Limit));
755 DEBUG ((DEBUG_INFO,
"PciRootBridge->Io.Base %llx, \n", mPciRootBridgeInfo->RootBridge[RbIndex].
Io.Base));
756 DEBUG ((DEBUG_INFO,
"PciRootBridge->Io.limit %llx, \n", mPciRootBridgeInfo->RootBridge[RbIndex].
Io.Limit));
760 UINT64 *Data64 = (UINT64 *)(PropertyPtr->Data);
762 DEBUG ((DEBUG_INFO,
"PciRootBridge->Ecam.Base %llx, \n", mUplPciSegmentInfoHob->SegmentInfo[RbIndex].
BaseAddress));
766 Data32 = (UINT32 *)(PropertyPtr->Data);
767 mPciRootBridgeInfo->RootBridge[RbIndex].
Bus.Base =
Fdt32ToCpu (*Data32) & 0xFF;
768 mPciRootBridgeInfo->RootBridge[RbIndex].
Bus.Limit =
Fdt32ToCpu (*(Data32 + 1)) & 0xFF;
769 mPciRootBridgeInfo->RootBridge[RbIndex].
Bus.Translation = 0;
771 DEBUG ((DEBUG_INFO,
"PciRootBridge->Bus.Base %x, index %x\n", mPciRootBridgeInfo->RootBridge[RbIndex].
Bus.Base, RbIndex));
772 DEBUG ((DEBUG_INFO,
"PciRootBridge->Bus.limit %x, index %x\n", mPciRootBridgeInfo->RootBridge[RbIndex].
Bus.Limit, RbIndex));
802 CONST CHAR8 *TempStr;
806 UINT64 NumberOfBytes;
807 UINTN MinimalNeededSize;
812 BOOLEAN IsHobConstructed;
814 UINT8 RootBridgeCount;
823 UINT16 SegmentNumber;
824 UINT64 CurrentPciBaseAddress;
825 UINT64 NextPciBaseAddress;
826 UINT8 *RbSegNumAlreadyAssigned;
827 UINT8 NumberOfRbSegNumAlreadyAssigned;
831 MinimalNeededSize =
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize);
832 IsHobConstructed =
FALSE;
842 DEBUG ((DEBUG_INFO,
"FDT = 0x%x %x\n", Fdt,
Fdt32ToCpu (*((UINT32 *)Fdt))));
843 DEBUG ((DEBUG_INFO,
"Start parsing DTB data\n"));
844 DEBUG ((DEBUG_INFO,
"MinimalNeededSize :%x\n", MinimalNeededSize));
848 DEBUG ((DEBUG_INFO,
"\n Node(%08x) %a Depth %x", Node, NodePtr->Name, Depth));
855 Data64 = (UINT64 *)(PropertyPtr->Data);
858 DEBUG ((DEBUG_INFO,
"\n Property(%08X) %a", Property, TempStr));
859 DEBUG ((DEBUG_INFO,
" %016lX %016lX", StartAddress, NumberOfBytes));
860 if (!IsHobConstructed) {
861 if ((NumberOfBytes > MinimalNeededSize) && (StartAddress < BASE_4GB)) {
862 MemoryBottom = StartAddress + NumberOfBytes - MinimalNeededSize;
863 FreeMemoryBottom = MemoryBottom;
864 FreeMemoryTop = StartAddress + NumberOfBytes;
865 MemoryTop = FreeMemoryTop;
867 DEBUG ((DEBUG_INFO,
"MemoryBottom :0x%llx\n", MemoryBottom));
868 DEBUG ((DEBUG_INFO,
"FreeMemoryBottom :0x%llx\n", FreeMemoryBottom));
869 DEBUG ((DEBUG_INFO,
"FreeMemoryTop :0x%llx\n", FreeMemoryTop));
870 DEBUG ((DEBUG_INFO,
"MemoryTop :0x%llx\n", MemoryTop));
872 IsHobConstructed =
TRUE;
873 NewHobList = (
UINTN)mHobList;
882 if (PropertyPtr ==
NULL) {
886 TempStr = (CHAR8 *)(PropertyPtr->Data);
895 for (index = 0; index < NumRsv; index++) {
903 index = RootBridgeCount - 1;
907 DEBUG ((DEBUG_INFO,
"\n Node(%08x) %a Depth %x", Node, NodePtr->Name, Depth));
910 DEBUG ((DEBUG_INFO,
"NodeType :0x%x\n", NodeType));
913 DEBUG ((DEBUG_INFO,
"ParseReservedMemory\n"));
917 DEBUG ((DEBUG_INFO,
"ParseMemory\n"));
921 DEBUG ((DEBUG_INFO,
"Memory has initialized\n"));
926 DEBUG ((DEBUG_INFO,
"ParseFrameBuffer\n"));
930 DEBUG ((DEBUG_INFO,
"ParsePciRootBridge, index :%x \n", index));
932 DEBUG ((DEBUG_INFO,
"After ParsePciRootBridge, index :%x\n", index));
937 DEBUG ((DEBUG_INFO,
"ParseOptions\n"));
941 DEBUG ((DEBUG_INFO,
"ParseNothing\n"));
948 mPciRootBridgeInfo->ResourceAssigned = (BOOLEAN)PciEnumDone;
954 RbSegNumAlreadyAssigned =
AllocateZeroPool (
sizeof (UINT8) * RootBridgeCount);
955 NextPciBaseAddress = 0;
956 NumberOfRbSegNumAlreadyAssigned = 0;
961 CurrentPciBaseAddress = mUplPciSegmentInfoHob->SegmentInfo[0].
BaseAddress & ~0xFFFFFFF;
962 NextPciBaseAddress = CurrentPciBaseAddress;
963 mUplPciSegmentInfoHob->SegmentInfo[0].
SegmentNumber = SegmentNumber;
964 mPciRootBridgeInfo->RootBridge[0].
Segment = SegmentNumber;
965 RbSegNumAlreadyAssigned[0] = 1;
966 NumberOfRbSegNumAlreadyAssigned++;
968 while (NumberOfRbSegNumAlreadyAssigned < RootBridgeCount) {
969 for (index = 1; index < RootBridgeCount; index++) {
970 if (RbSegNumAlreadyAssigned[index] == 1) {
974 if (CurrentPciBaseAddress == (mUplPciSegmentInfoHob->SegmentInfo[index].
BaseAddress & ~0xFFFFFFF)) {
975 mUplPciSegmentInfoHob->SegmentInfo[index].
SegmentNumber = SegmentNumber;
976 mPciRootBridgeInfo->RootBridge[index].
Segment = SegmentNumber;
977 RbSegNumAlreadyAssigned[index] = 1;
978 NumberOfRbSegNumAlreadyAssigned++;
979 }
else if (CurrentPciBaseAddress == NextPciBaseAddress) {
980 NextPciBaseAddress = mUplPciSegmentInfoHob->SegmentInfo[index].
BaseAddress & ~0xFFFFFFF;
985 CurrentPciBaseAddress = NextPciBaseAddress;
989 DEBUG ((DEBUG_INFO,
"\n"));
1030 DEBUG ((DEBUG_INFO,
"%a() FDT blob\n", __func__));
1033 DEBUG ((DEBUG_INFO,
"%a() HOb list\n", __func__));
1036 return (
UINTN)(mHobList);
VOID EFIAPI BuildCpuHob(IN UINT8 SizeOfMemorySpace, IN UINT8 SizeOfIoSpace)
VOID EFIAPI BuildResourceDescriptorHob(IN EFI_RESOURCE_TYPE ResourceType, IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute, IN EFI_PHYSICAL_ADDRESS PhysicalStart, IN UINT64 NumberOfBytes)
VOID *EFIAPI BuildGuidHob(IN CONST EFI_GUID *Guid, IN UINTN DataLength)
VOID EFIAPI BuildMemoryAllocationHob(IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN EFI_MEMORY_TYPE MemoryType)
UINTN EFIAPI AsciiStrLen(IN CONST CHAR8 *String)
INTN EFIAPI AsciiStrCmp(IN CONST CHAR8 *FirstString, IN CONST CHAR8 *SecondString)
INTN EFIAPI AsciiStrnCmp(IN CONST CHAR8 *FirstString, IN CONST CHAR8 *SecondString, IN UINTN Length)
UINT64 EFIAPI LShiftU64(IN UINT64 Operand, IN UINTN Count)
VOID *EFIAPI SetMem(OUT VOID *Buffer, IN UINTN Length, IN UINT8 Value)
VOID *EFIAPI ZeroMem(OUT VOID *Buffer, IN UINTN Length)
VOID *EFIAPI AllocateZeroPool(IN UINTN AllocationSize)
INT32 EFIAPI FdtNextPropertyOffset(IN CONST VOID *Fdt, IN INT32 Offset)
INT32 EFIAPI FdtFirstSubnode(IN CONST VOID *Fdt, IN INT32 Offset)
CONST FDT_PROPERTY *EFIAPI FdtGetProperty(IN CONST VOID *Fdt, IN INT32 NodeOffset, IN CONST CHAR8 *Name, IN INT32 *Length)
UINT64 EFIAPI Fdt64ToCpu(IN UINT64 Value)
CONST CHAR8 *EFIAPI FdtGetString(IN CONST VOID *Fdt, IN INT32 StrOffset, IN INT32 *Length OPTIONAL)
INT32 EFIAPI FdtNextNode(IN CONST VOID *Fdt, IN INT32 Offset, IN INT32 *Depth)
INT32 EFIAPI FdtCheckHeader(IN CONST VOID *Fdt)
INTN EFIAPI FdtGetNumberOfReserveMapEntries(IN CONST VOID *Fdt)
UINT32 EFIAPI Fdt32ToCpu(IN UINT32 Value)
INT32 EFIAPI FdtFirstPropertyOffset(IN CONST VOID *Fdt, IN INT32 NodeOffset)
INTN EFIAPI FdtGetReserveMapEntry(IN CONST VOID *Fdt, IN INTN Index, OUT UINT64 *Addr, OUT UINT64 *Size)
INT32 EFIAPI FdtNextSubnode(IN CONST VOID *Fdt, IN INT32 Offset)
CONST FDT_PROPERTY *EFIAPI FdtGetPropertyByOffset(IN CONST VOID *Fdt, IN INT32 Offset, IN INT32 *Length)
VOID RecordMemoryNode(INT32 Node)
CHAR8 * ParseFrameBuffer(IN VOID *Fdt, IN INT32 Node)
VOID ParseMemory(IN VOID *Fdt, IN INT32 Node)
UINTN EFIAPI FdtNodeParser(IN VOID *FdtBase)
EFI_HOB_HANDOFF_INFO_TABLE *EFIAPI HobConstructor(IN VOID *EfiMemoryBottom, IN VOID *EfiMemoryTop, IN VOID *EfiFreeMemoryBottom, IN VOID *EfiFreeMemoryTop)
VOID ParsePciRootBridge(IN VOID *Fdt, IN INT32 Node, IN UINT8 RootBridgeCount, IN CHAR8 *GmaStr, IN UINT8 *index)
FDT_NODE_TYPE CheckNodeType(CHAR8 *NodeString, INT32 Depth)
BOOLEAN CheckMemoryNodeIfInit(INT32 Node)
UINTN EFIAPI UplInitHob(IN VOID *FdtBase)
VOID ParsegraphicNode(IN VOID *Fdt, IN INT32 SubNode)
VOID ParseReservedMemory(IN VOID *Fdt, IN INT32 Node)
VOID ParseOptions(IN VOID *Fdt, IN INT32 Node, OUT UINT8 *PciEnumDone, OUT EFI_BOOT_MODE *BootMode)
VOID ParseSerialPort(IN VOID *Fdt, IN INT32 SubNode)
UINTN EFIAPI ParseDtb(IN VOID *FdtBase)
#define DEBUG(Expression)
@ PixelRedGreenBlueReserved8BitPerColor
@ PixelBlueGreenRedReserved8BitPerColor
#define PcdGet64(TokenName)
#define FixedPcdGet32(TokenName)
#define PcdGet8(TokenName)
#define PcdGet32(TokenName)
#define EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE
EFI_GUID gUplPciSegmentInfoHobGuid
UINT64 EFI_PHYSICAL_ADDRESS
UINT32 VerticalResolution
EFI_GRAPHICS_PIXEL_FORMAT PixelFormat
UINT32 HorizontalResolution
UINT16 SubsystemId
Ignore if the value is 0xFFFF.
UINT16 VendorId
Ignore if the value is 0xFFFF.
UINT16 SubsystemVendorId
Ignore if the value is 0xFFFF.
UINT8 RevisionId
Ignore if the value is 0xFF.
UINT16 DeviceId
Ignore if the value is 0xFFFF.
UINT32 Segment
Segment number.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus
Bus aperture which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem
MMIO aperture below 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G
Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G
MMIO aperture above 4GB which can be used by the root bridge.
UINT64 AllocationAttributes
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem
Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io
IO aperture which can be used by the root bridge.
UINT16 SegmentNumber
Segment number.
UINT64 BaseAddress
ECAM Base address.