GoldmontMsr.h

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#ifndef __GOLDMONT_MSR_H__
#define __GOLDMONT_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x5C    \
    )                       \
   )
 
#define MSR_GOLDMONT_FEATURE_CONTROL  0x0000003A
 
typedef union {
  struct {
    UINT32    Lock                       : 1;
    UINT32    EnableVmxInsideSmx         : 1;
    UINT32    EnableVmxOutsideSmx        : 1;
    UINT32    Reserved1                  : 5;
    UINT32    SenterLocalFunctionEnables : 7;
    UINT32    SenterGlobalEnable         : 1;
    UINT32    Reserved2                  : 2;
    UINT32    SgxEnable                  : 1;
    UINT32    Reserved3                  : 13;
    UINT32    Reserved4                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;
 
#define MSR_GOLDMONT_PLATFORM_INFO  0x000000CE
 
typedef union {
  struct {
    UINT32    Reserved1              : 8;
    UINT32    MaximumNonTurboRatio   : 8;
    UINT32    Reserved2              : 12;
    UINT32    RatioLimit             : 1;
    UINT32    TDPLimit               : 1;
    UINT32    TJOFFSET               : 1;
    UINT32    Reserved3              : 1;
    UINT32    Reserved4              : 8;
    UINT32    MaximumEfficiencyRatio : 8;
    UINT32    Reserved5              : 16;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_PLATFORM_INFO_REGISTER;
 
#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL  0x000000E2
 
typedef union {
  struct {
    UINT32    Limit     : 4;
    UINT32    Reserved1 : 6;
    UINT32    IO_MWAIT  : 1;
    UINT32    Reserved2 : 4;
    UINT32    CFGLock   : 1;
    UINT32    Reserved3 : 16;
    UINT32    Reserved4 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
 
#define MSR_GOLDMONT_SMM_MCA_CAP  0x0000017D
 
typedef union {
  struct {
    UINT32    Reserved1            : 32;
    UINT32    Reserved2            : 26;
    UINT32    SMM_Code_Access_Chk  : 1;
    UINT32    Long_Flow_Indication : 1;
    UINT32    Reserved3            : 4;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;
 
#define MSR_GOLDMONT_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    FastStrings                    : 1;
    UINT32    Reserved1                      : 2;
    UINT32    AutomaticThermalControlCircuit : 1;
    UINT32    Reserved2                      : 3;
    UINT32    PerformanceMonitoring          : 1;
    UINT32    Reserved3                      : 3;
    UINT32    BTS                            : 1;
    UINT32    PEBS                           : 1;
    UINT32    Reserved4                      : 3;
    UINT32    EIST                           : 1;
    UINT32    Reserved5                      : 1;
    UINT32    MONITOR                        : 1;
    UINT32    Reserved6                      : 3;
    UINT32    LimitCpuidMaxval               : 1;
    UINT32    xTPR_Message_Disable           : 1;
    UINT32    Reserved7                      : 8;
    UINT32    Reserved8                      : 2;
    UINT32    XD                             : 1;
    UINT32    Reserved9                      : 3;
    UINT32    TurboModeDisable : 1;
    UINT32    Reserved10       : 25;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_GOLDMONT_MISC_FEATURE_CONTROL  0x000001A4
 
typedef union {
  struct {
    UINT32    L2HardwarePrefetcherDisable  : 1;
    UINT32    Reserved1                    : 1;
    UINT32    DCUHardwarePrefetcherDisable : 1;
    UINT32    Reserved2                    : 29;
    UINT32    Reserved3                    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;
 
#define MSR_GOLDMONT_MISC_PWR_MGMT  0x000001AA
 
typedef union {
  struct {
    UINT32    EISTHardwareCoordinationDisable    : 1;
    UINT32    Reserved1                          : 21;
    UINT32    ThermalInterruptCoordinationEnable : 1;
    UINT32    Reserved2                          : 9;
    UINT32    Reserved3                          : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;
 
#define MSR_GOLDMONT_TURBO_RATIO_LIMIT  0x000001AD
 
typedef union {
  struct {
    UINT32    MaxRatioLimitGroup0 : 8;
    UINT32    MaxRatioLimitGroup1 : 8;
    UINT32    MaxRatioLimitGroup2 : 8;
    UINT32    MaxRatioLimitGroup3 : 8;
    UINT32    MaxRatioLimitGroup4 : 8;
    UINT32    MaxRatioLimitGroup5 : 8;
    UINT32    MaxRatioLimitGroup6 : 8;
    UINT32    MaxRatioLimitGroup7 : 8;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;
 
#define MSR_GOLDMONT_TURBO_GROUP_CORECNT  0x000001AE
 
typedef union {
  struct {
    UINT32    CoreCountThresholdGroup0 : 8;
    UINT32    CoreCountThresholdGroup1 : 8;
    UINT32    CoreCountThresholdGroup2 : 8;
    UINT32    CoreCountThresholdGroup3 : 8;
    UINT32    CoreCountThresholdGroup4 : 8;
    UINT32    CoreCountThresholdGroup5 : 8;
    UINT32    CoreCountThresholdGroup6 : 8;
    UINT32    CoreCountThresholdGroup7 : 8;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;
 
#define MSR_GOLDMONT_LBR_SELECT  0x000001C8
 
typedef union {
  struct {
    UINT32    CPL_EQ_0      : 1;
    UINT32    CPL_NEQ_0     : 1;
    UINT32    JCC           : 1;
    UINT32    NEAR_REL_CALL : 1;
    UINT32    NEAR_IND_CALL : 1;
    UINT32    NEAR_RET      : 1;
    UINT32    NEAR_IND_JMP  : 1;
    UINT32    NEAR_REL_JMP  : 1;
    UINT32    FAR_BRANCH    : 1;
    UINT32    EN_CALL_STACK : 1;
    UINT32    Reserved1     : 22;
    UINT32    Reserved2     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_LBR_SELECT_REGISTER;
 
#define MSR_GOLDMONT_LASTBRANCH_TOS  0x000001C9
 
#define MSR_GOLDMONT_POWER_CTL  0x000001FC
 
typedef union {
  struct {
    UINT32    Reserved1 : 1;
    UINT32    C1EEnable : 1;
    UINT32    Reserved2 : 30;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_POWER_CTL_REGISTER;
 
#define MSR_GOLDMONT_SGXOWNEREPOCH0  0x00000300
 
//
// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.
//
#define MSR_GOLDMONT_SGXOWNER0  MSR_GOLDMONT_SGXOWNEREPOCH0
 
#define MSR_GOLDMONT_SGXOWNEREPOCH1  0x00000301
 
//
// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.
//
#define MSR_GOLDMONT_SGXOWNER1  MSR_GOLDMONT_SGXOWNEREPOCH1
 
#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET  0x00000390
 
typedef union {
  struct {
    UINT32    Ovf_PMC0       : 1;
    UINT32    Ovf_PMC1       : 1;
    UINT32    Ovf_PMC2       : 1;
    UINT32    Ovf_PMC3       : 1;
    UINT32    Reserved1      : 28;
    UINT32    Ovf_FixedCtr0  : 1;
    UINT32    Ovf_FixedCtr1  : 1;
    UINT32    Ovf_FixedCtr2  : 1;
    UINT32    Reserved2      : 20;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved3      : 2;
    UINT32    LBR_Frz        : 1;
    UINT32    CTR_Frz        : 1;
    UINT32    ASCI           : 1;
    UINT32    Ovf_Uncore     : 1;
    UINT32    Ovf_BufDSSAVE  : 1;
    UINT32    CondChgd       : 1;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
 
#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET  0x00000391
 
typedef union {
  struct {
    UINT32    Ovf_PMC0       : 1;
    UINT32    Ovf_PMC1       : 1;
    UINT32    Ovf_PMC2       : 1;
    UINT32    Ovf_PMC3       : 1;
    UINT32    Reserved1      : 28;
    UINT32    Ovf_FixedCtr0  : 1;
    UINT32    Ovf_FixedCtr1  : 1;
    UINT32    Ovf_FixedCtr2  : 1;
    UINT32    Reserved2      : 20;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved3      : 2;
    UINT32    LBR_Frz        : 1;
    UINT32    CTR_Frz        : 1;
    UINT32    ASCI           : 1;
    UINT32    Ovf_Uncore     : 1;
    UINT32    Ovf_BufDSSAVE  : 1;
    UINT32    Reserved4      : 1;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
 
#define MSR_GOLDMONT_PEBS_ENABLE  0x000003F1
 
typedef union {
  struct {
    UINT32    Enable    : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_PEBS_ENABLE_REGISTER;
 
#define MSR_GOLDMONT_PKG_C3_RESIDENCY  0x000003F8
 
#define MSR_GOLDMONT_PKG_C6_RESIDENCY  0x000003F9
 
#define MSR_GOLDMONT_CORE_C3_RESIDENCY  0x000003FC
 
#define MSR_GOLDMONT_SMM_FEATURE_CONTROL  0x000004E0
 
typedef union {
  struct {
    UINT32    Lock      : 1;
    UINT32    Reserved1 : 1;
    UINT32    SMM_Code_Chk_En : 1;
    UINT32    Reserved2       : 29;
    UINT32    Reserved3       : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;
 
#define MSR_GOLDMONT_SMM_DELAYED  0x000004E2
 
#define MSR_GOLDMONT_SMM_BLOCKED  0x000004E3
 
#define MSR_IA32_RTIT_CTL  0x00000570
 
typedef union {
  struct {
    UINT32    TraceEn   : 1;
    UINT32    CYCEn     : 1;
    UINT32    OS        : 1;
    UINT32    User      : 1;
    UINT32    Reserved1 : 3;
    UINT32    CR3       : 1;
    UINT32    ToPA      : 1;
    UINT32    MTCEn     : 1;
    UINT32    TSCEn     : 1;
    UINT32    DisRETC   : 1;
    UINT32    Reserved2 : 1;
    UINT32    BranchEn  : 1;
    UINT32    MTCFreq   : 4;
    UINT32    Reserved3 : 1;
    UINT32    CYCThresh : 4;
    UINT32    Reserved4 : 1;
    UINT32    PSBFreq   : 4;
    UINT32    Reserved5 : 4;
    UINT32    ADDR0_CFG : 4;
    UINT32    ADDR1_CFG : 4;
    UINT32    Reserved6 : 24;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;
 
#define MSR_GOLDMONT_RAPL_POWER_UNIT  0x00000606
 
typedef union {
  struct {
    UINT32    PowerUnits        : 4;
    UINT32    Reserved1         : 4;
    UINT32    EnergyStatusUnits : 5;
    UINT32    Reserved2         : 3;
    UINT32    TimeUnit          : 4;
    UINT32    Reserved3         : 12;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;
 
#define MSR_GOLDMONT_PKGC3_IRTL  0x0000060A
 
typedef union {
  struct {
    UINT32    InterruptResponseTimeLimit : 10;
    UINT32    TimeUnit                   : 3;
    UINT32    Reserved1                  : 2;
    UINT32    Valid                      : 1;
    UINT32    Reserved2                  : 16;
    UINT32    Reserved3                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_PKGC3_IRTL_REGISTER;
 
#define MSR_GOLDMONT_PKGC_IRTL1  0x0000060B
 
typedef union {
  struct {
    UINT32    InterruptResponseTimeLimit : 10;
    UINT32    TimeUnit                   : 3;
    UINT32    Reserved1                  : 2;
    UINT32    Valid                      : 1;
    UINT32    Reserved2                  : 16;
    UINT32    Reserved3                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_PKGC_IRTL1_REGISTER;
 
#define MSR_GOLDMONT_PKGC_IRTL2  0x0000060C
 
typedef union {
  struct {
    UINT32    InterruptResponseTimeLimit : 10;
    UINT32    TimeUnit                   : 3;
    UINT32    Reserved1                  : 2;
    UINT32    Valid                      : 1;
    UINT32    Reserved2                  : 16;
    UINT32    Reserved3                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_PKGC_IRTL2_REGISTER;
 
#define MSR_GOLDMONT_PKG_C2_RESIDENCY  0x0000060D
 
#define MSR_GOLDMONT_PKG_POWER_LIMIT  0x00000610
 
#define MSR_GOLDMONT_PKG_ENERGY_STATUS  0x00000611
 
#define MSR_GOLDMONT_PKG_PERF_STATUS  0x00000613
 
#define MSR_GOLDMONT_PKG_POWER_INFO  0x00000614
 
typedef union {
  struct {
    UINT32    ThermalSpecPower  : 15;
    UINT32    Reserved1         : 1;
    UINT32    MinimumPower      : 15;
    UINT32    Reserved2         : 1;
    UINT32    MaximumPower      : 15;
    UINT32    Reserved3         : 1;
    UINT32    MaximumTimeWindow : 7;
    UINT32    Reserved4         : 9;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;
 
#define MSR_GOLDMONT_DRAM_POWER_LIMIT  0x00000618
 
#define MSR_GOLDMONT_DRAM_ENERGY_STATUS  0x00000619
 
#define MSR_GOLDMONT_DRAM_PERF_STATUS  0x0000061B
 
#define MSR_GOLDMONT_DRAM_POWER_INFO  0x0000061C
 
#define MSR_GOLDMONT_PKG_C10_RESIDENCY  0x00000632
 
#define MSR_GOLDMONT_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_GOLDMONT_PP1_ENERGY_STATUS  0x00000641
 
#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO  0x0000064C
 
typedef union {
  struct {
    UINT32    MAX_NON_TURBO_RATIO         : 8;
    UINT32    Reserved1                   : 23;
    UINT32    TURBO_ACTIVATION_RATIO_Lock : 1;
    UINT32    Reserved2                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;
 
#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS  0x0000064F
 
typedef union {
  struct {
    UINT32    PROCHOTStatus                    : 1;
    UINT32    ThermalStatus                    : 1;
    UINT32    PL1Status                        : 1;
    UINT32    PL2Status                        : 1;
    UINT32    Reserved1                        : 5;
    UINT32    PowerLimitingStatus              : 1;
    UINT32    VRThermAlertStatus               : 1;
    UINT32    MaxTurboLimitStatus              : 1;
    UINT32    ElectricalDesignPointStatus      : 1;
    UINT32    TurboTransitionAttenuationStatus : 1;
    UINT32    MaximumEfficiencyFrequencyStatus : 1;
    UINT32    Reserved2                        : 1;
    UINT32    PROCHOT                          : 1;
    UINT32    ThermalLog                       : 1;
    UINT32    PL1Log                           : 1;
    UINT32    PL2Log                           : 1;
    UINT32    Reserved3                        : 5;
    UINT32    CorePowerLimitingLog             : 1;
    UINT32    VRThermAlertLog                  : 1;
    UINT32    MaxTurboLimitLog                 : 1;
    UINT32    ElectricalDesignPointLog         : 1;
    UINT32    TurboTransitionAttenuationLog    : 1;
    UINT32    MaximumEfficiencyFrequencyLog    : 1;
    UINT32    Reserved4                        : 1;
    UINT32    Reserved5                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP   0x00000680
#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP   0x00000681
#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP   0x00000682
#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP   0x00000683
#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP   0x00000684
#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP   0x00000685
#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP   0x00000686
#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP   0x00000687
#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP   0x00000688
#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP   0x00000689
#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP  0x0000068A
#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP  0x0000068B
#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP  0x0000068C
#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP  0x0000068D
#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP  0x0000068E
#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP  0x0000068F
#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP  0x00000690
#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP  0x00000691
#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP  0x00000692
#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP  0x00000693
#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP  0x00000694
#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP  0x00000695
#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP  0x00000696
#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP  0x00000697
#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP  0x00000698
#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP  0x00000699
#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP  0x0000069A
#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP  0x0000069B
#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP  0x0000069C
#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP  0x0000069D
#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP  0x0000069E
#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP  0x0000069F
 
typedef union {
  struct {
    UINT32    FromLinearAddress   : 32;
    UINT32    FromLinearAddressHi : 16;
    UINT32    SignedExtension     : 15;
    UINT32    Mispred             : 1;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;
 
#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP   0x000006C0
#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP   0x000006C1
#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP   0x000006C2
#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP   0x000006C3
#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP   0x000006C4
#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP   0x000006C5
#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP   0x000006C6
#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP   0x000006C7
#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP   0x000006C8
#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP   0x000006C9
#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP  0x000006CA
#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP  0x000006CB
#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP  0x000006CC
#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP  0x000006CD
#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP  0x000006CE
#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP  0x000006CF
#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP  0x000006D0
#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP  0x000006D1
#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP  0x000006D2
#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP  0x000006D3
#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP  0x000006D4
#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP  0x000006D5
#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP  0x000006D6
#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP  0x000006D7
#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP  0x000006D8
#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP  0x000006D9
#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP  0x000006DA
#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP  0x000006DB
#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP  0x000006DC
#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP  0x000006DD
#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP  0x000006DE
#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP  0x000006DF
 
typedef union {
  struct {
    UINT32    TargetLinearAddress   : 32;
    UINT32    TargetLinearAddressHi : 16;
    UINT32    ElapsedCycles         : 16;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;
 
#define MSR_GOLDMONT_IA32_PQR_ASSOC  0x00000C8F
 
typedef union {
  struct {
    UINT32    Reserved1 : 32;
    UINT32    COS       : 2;
    UINT32    Reserved2 : 30;
  } Bits;
  UINT64    Uint64;
} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;
 
#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0  0x00000D10
#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1  0x00000D11
#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2  0x00000D12
 
typedef union {
  struct {
    UINT32    CBM       : 8;
    UINT32    Reserved1 : 24;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;
 
#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3  0x00000D13
 
typedef union {
  struct {
    UINT32    CBM       : 20;
    UINT32    Reserved1 : 12;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;
 
#endif