GoldmontMsr.h File Reference

#include <Register/Intel/ArchitecturalMsr.h>

Go to the source code of this file.

Data Structures
union	MSR_GOLDMONT_FEATURE_CONTROL_REGISTER
union	MSR_GOLDMONT_PLATFORM_INFO_REGISTER
union	MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER
union	MSR_GOLDMONT_SMM_MCA_CAP_REGISTER
union	MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER
union	MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER
union	MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER
union	MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
union	MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
union	MSR_GOLDMONT_LBR_SELECT_REGISTER
union	MSR_GOLDMONT_POWER_CTL_REGISTER
union	MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
union	MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
union	MSR_GOLDMONT_PEBS_ENABLE_REGISTER
union	MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER
union	MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER
union	MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER
union	MSR_GOLDMONT_PKGC3_IRTL_REGISTER
union	MSR_GOLDMONT_PKGC_IRTL1_REGISTER
union	MSR_GOLDMONT_PKGC_IRTL2_REGISTER
union	MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
union	MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER
union	MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
union	MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
union	MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
union	MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER
union	MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER
union	MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER

Macros
#define	IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel)
#define	MSR_GOLDMONT_FEATURE_CONTROL   0x0000003A
#define	MSR_GOLDMONT_PLATFORM_INFO   0x000000CE
#define	MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL   0x000000E2
#define	MSR_GOLDMONT_SMM_MCA_CAP   0x0000017D
#define	MSR_GOLDMONT_IA32_MISC_ENABLE   0x000001A0
#define	MSR_GOLDMONT_MISC_FEATURE_CONTROL   0x000001A4
#define	MSR_GOLDMONT_MISC_PWR_MGMT   0x000001AA
#define	MSR_GOLDMONT_TURBO_RATIO_LIMIT   0x000001AD
#define	MSR_GOLDMONT_TURBO_GROUP_CORECNT   0x000001AE
#define	MSR_GOLDMONT_LBR_SELECT   0x000001C8
#define	MSR_GOLDMONT_LASTBRANCH_TOS   0x000001C9
#define	MSR_GOLDMONT_POWER_CTL   0x000001FC
#define	MSR_GOLDMONT_SGXOWNEREPOCH0   0x00000300
#define	MSR_GOLDMONT_SGXOWNER0   MSR_GOLDMONT_SGXOWNEREPOCH0
#define	MSR_GOLDMONT_SGXOWNEREPOCH1   0x00000301
#define	MSR_GOLDMONT_SGXOWNER1   MSR_GOLDMONT_SGXOWNEREPOCH1
#define	MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET   0x00000390
#define	MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET   0x00000391
#define	MSR_GOLDMONT_PEBS_ENABLE   0x000003F1
#define	MSR_GOLDMONT_PKG_C3_RESIDENCY   0x000003F8
#define	MSR_GOLDMONT_PKG_C6_RESIDENCY   0x000003F9
#define	MSR_GOLDMONT_CORE_C3_RESIDENCY   0x000003FC
#define	MSR_GOLDMONT_SMM_FEATURE_CONTROL   0x000004E0
#define	MSR_GOLDMONT_SMM_DELAYED   0x000004E2
#define	MSR_GOLDMONT_SMM_BLOCKED   0x000004E3
#define	MSR_IA32_RTIT_CTL   0x00000570
#define	MSR_GOLDMONT_RAPL_POWER_UNIT   0x00000606
#define	MSR_GOLDMONT_PKGC3_IRTL   0x0000060A
#define	MSR_GOLDMONT_PKGC_IRTL1   0x0000060B
#define	MSR_GOLDMONT_PKGC_IRTL2   0x0000060C
#define	MSR_GOLDMONT_PKG_C2_RESIDENCY   0x0000060D
#define	MSR_GOLDMONT_PKG_POWER_LIMIT   0x00000610
#define	MSR_GOLDMONT_PKG_ENERGY_STATUS   0x00000611
#define	MSR_GOLDMONT_PKG_PERF_STATUS   0x00000613
#define	MSR_GOLDMONT_PKG_POWER_INFO   0x00000614
#define	MSR_GOLDMONT_DRAM_POWER_LIMIT   0x00000618
#define	MSR_GOLDMONT_DRAM_ENERGY_STATUS   0x00000619
#define	MSR_GOLDMONT_DRAM_PERF_STATUS   0x0000061B
#define	MSR_GOLDMONT_DRAM_POWER_INFO   0x0000061C
#define	MSR_GOLDMONT_PKG_C10_RESIDENCY   0x00000632
#define	MSR_GOLDMONT_PP0_ENERGY_STATUS   0x00000639
#define	MSR_GOLDMONT_PP1_ENERGY_STATUS   0x00000641
#define	MSR_GOLDMONT_TURBO_ACTIVATION_RATIO   0x0000064C
#define	MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS   0x0000064F
#define	MSR_GOLDMONT_IA32_PQR_ASSOC   0x00000C8F
#define	MSR_GOLDMONT_IA32_L2_QOS_MASK_3   0x00000D13
#define	MSR_GOLDMONT_LASTBRANCH_0_FROM_IP   0x00000680
#define	MSR_GOLDMONT_LASTBRANCH_1_FROM_IP   0x00000681
#define	MSR_GOLDMONT_LASTBRANCH_2_FROM_IP   0x00000682
#define	MSR_GOLDMONT_LASTBRANCH_3_FROM_IP   0x00000683
#define	MSR_GOLDMONT_LASTBRANCH_4_FROM_IP   0x00000684
#define	MSR_GOLDMONT_LASTBRANCH_5_FROM_IP   0x00000685
#define	MSR_GOLDMONT_LASTBRANCH_6_FROM_IP   0x00000686
#define	MSR_GOLDMONT_LASTBRANCH_7_FROM_IP   0x00000687
#define	MSR_GOLDMONT_LASTBRANCH_8_FROM_IP   0x00000688
#define	MSR_GOLDMONT_LASTBRANCH_9_FROM_IP   0x00000689
#define	MSR_GOLDMONT_LASTBRANCH_10_FROM_IP   0x0000068A
#define	MSR_GOLDMONT_LASTBRANCH_11_FROM_IP   0x0000068B
#define	MSR_GOLDMONT_LASTBRANCH_12_FROM_IP   0x0000068C
#define	MSR_GOLDMONT_LASTBRANCH_13_FROM_IP   0x0000068D
#define	MSR_GOLDMONT_LASTBRANCH_14_FROM_IP   0x0000068E
#define	MSR_GOLDMONT_LASTBRANCH_15_FROM_IP   0x0000068F
#define	MSR_GOLDMONT_LASTBRANCH_16_FROM_IP   0x00000690
#define	MSR_GOLDMONT_LASTBRANCH_17_FROM_IP   0x00000691
#define	MSR_GOLDMONT_LASTBRANCH_18_FROM_IP   0x00000692
#define	MSR_GOLDMONT_LASTBRANCH_19_FROM_IP   0x00000693
#define	MSR_GOLDMONT_LASTBRANCH_20_FROM_IP   0x00000694
#define	MSR_GOLDMONT_LASTBRANCH_21_FROM_IP   0x00000695
#define	MSR_GOLDMONT_LASTBRANCH_22_FROM_IP   0x00000696
#define	MSR_GOLDMONT_LASTBRANCH_23_FROM_IP   0x00000697
#define	MSR_GOLDMONT_LASTBRANCH_24_FROM_IP   0x00000698
#define	MSR_GOLDMONT_LASTBRANCH_25_FROM_IP   0x00000699
#define	MSR_GOLDMONT_LASTBRANCH_26_FROM_IP   0x0000069A
#define	MSR_GOLDMONT_LASTBRANCH_27_FROM_IP   0x0000069B
#define	MSR_GOLDMONT_LASTBRANCH_28_FROM_IP   0x0000069C
#define	MSR_GOLDMONT_LASTBRANCH_29_FROM_IP   0x0000069D
#define	MSR_GOLDMONT_LASTBRANCH_30_FROM_IP   0x0000069E
#define	MSR_GOLDMONT_LASTBRANCH_31_FROM_IP   0x0000069F
#define	MSR_GOLDMONT_LASTBRANCH_0_TO_IP   0x000006C0
#define	MSR_GOLDMONT_LASTBRANCH_1_TO_IP   0x000006C1
#define	MSR_GOLDMONT_LASTBRANCH_2_TO_IP   0x000006C2
#define	MSR_GOLDMONT_LASTBRANCH_3_TO_IP   0x000006C3
#define	MSR_GOLDMONT_LASTBRANCH_4_TO_IP   0x000006C4
#define	MSR_GOLDMONT_LASTBRANCH_5_TO_IP   0x000006C5
#define	MSR_GOLDMONT_LASTBRANCH_6_TO_IP   0x000006C6
#define	MSR_GOLDMONT_LASTBRANCH_7_TO_IP   0x000006C7
#define	MSR_GOLDMONT_LASTBRANCH_8_TO_IP   0x000006C8
#define	MSR_GOLDMONT_LASTBRANCH_9_TO_IP   0x000006C9
#define	MSR_GOLDMONT_LASTBRANCH_10_TO_IP   0x000006CA
#define	MSR_GOLDMONT_LASTBRANCH_11_TO_IP   0x000006CB
#define	MSR_GOLDMONT_LASTBRANCH_12_TO_IP   0x000006CC
#define	MSR_GOLDMONT_LASTBRANCH_13_TO_IP   0x000006CD
#define	MSR_GOLDMONT_LASTBRANCH_14_TO_IP   0x000006CE
#define	MSR_GOLDMONT_LASTBRANCH_15_TO_IP   0x000006CF
#define	MSR_GOLDMONT_LASTBRANCH_16_TO_IP   0x000006D0
#define	MSR_GOLDMONT_LASTBRANCH_17_TO_IP   0x000006D1
#define	MSR_GOLDMONT_LASTBRANCH_18_TO_IP   0x000006D2
#define	MSR_GOLDMONT_LASTBRANCH_19_TO_IP   0x000006D3
#define	MSR_GOLDMONT_LASTBRANCH_20_TO_IP   0x000006D4
#define	MSR_GOLDMONT_LASTBRANCH_21_TO_IP   0x000006D5
#define	MSR_GOLDMONT_LASTBRANCH_22_TO_IP   0x000006D6
#define	MSR_GOLDMONT_LASTBRANCH_23_TO_IP   0x000006D7
#define	MSR_GOLDMONT_LASTBRANCH_24_TO_IP   0x000006D8
#define	MSR_GOLDMONT_LASTBRANCH_25_TO_IP   0x000006D9
#define	MSR_GOLDMONT_LASTBRANCH_26_TO_IP   0x000006DA
#define	MSR_GOLDMONT_LASTBRANCH_27_TO_IP   0x000006DB
#define	MSR_GOLDMONT_LASTBRANCH_28_TO_IP   0x000006DC
#define	MSR_GOLDMONT_LASTBRANCH_29_TO_IP   0x000006DD
#define	MSR_GOLDMONT_LASTBRANCH_30_TO_IP   0x000006DE
#define	MSR_GOLDMONT_LASTBRANCH_31_TO_IP   0x000006DF
#define	MSR_GOLDMONT_IA32_L2_QOS_MASK_0   0x00000D10
#define	MSR_GOLDMONT_IA32_L2_QOS_MASK_1   0x00000D11
#define	MSR_GOLDMONT_IA32_L2_QOS_MASK_2   0x00000D12

Detailed Description

MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:

Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file GoldmontMsr.h.

Macro Definition Documentation

IS_GOLDMONT_PROCESSOR

#define IS_GOLDMONT_PROCESSOR	(		DisplayFamily,
			DisplayModel
	)

Value:

  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x5C    \
    )                       \
   )

Is Intel Atom processors based on the Goldmont microarchitecture?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

Definition at line 32 of file GoldmontMsr.h.

MSR_GOLDMONT_CORE_C3_RESIDENCY

#define MSR_GOLDMONT_CORE_C3_RESIDENCY   0x000003FC

Core. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 Residency Counter. (R/O) Value since last reset that this core is in processor-specific C3 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);
AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);

Note

MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.

Definition at line 1172 of file GoldmontMsr.h.

MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS

#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS   0x0000064F

Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).

Parameters

ECX	MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);

Note

MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.

Definition at line 1959 of file GoldmontMsr.h.

MSR_GOLDMONT_DRAM_ENERGY_STATUS

#define MSR_GOLDMONT_DRAM_ENERGY_STATUS   0x00000619

Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);

Note

MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.

Definition at line 1795 of file GoldmontMsr.h.

MSR_GOLDMONT_DRAM_PERF_STATUS

#define MSR_GOLDMONT_DRAM_PERF_STATUS   0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);

Note

MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.

Definition at line 1813 of file GoldmontMsr.h.

MSR_GOLDMONT_DRAM_POWER_INFO

#define MSR_GOLDMONT_DRAM_POWER_INFO   0x0000061C

Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);
AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);

Note

MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.

Definition at line 1831 of file GoldmontMsr.h.

MSR_GOLDMONT_DRAM_POWER_LIMIT

#define MSR_GOLDMONT_DRAM_POWER_LIMIT   0x00000618

Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);
AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);

Note

MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.

Definition at line 1778 of file GoldmontMsr.h.

MSR_GOLDMONT_FEATURE_CONTROL

#define MSR_GOLDMONT_FEATURE_CONTROL   0x0000003A

Core. Control Features in Intel 64Processor (R/W).

Parameters

ECX	MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.

Example usage

MSR_GOLDMONT_FEATURE_CONTROL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);

Note

MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.

Definition at line 57 of file GoldmontMsr.h.

MSR_GOLDMONT_IA32_L2_QOS_MASK_0

#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0   0x00000D10

Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=n.

Parameters

ECX	MSR_GOLDMONT_IA32_L2_QOS_MASK_n
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.

Example usage

MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);
AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);

Note

MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM. MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM. MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.

Definition at line 2413 of file GoldmontMsr.h.

MSR_GOLDMONT_IA32_L2_QOS_MASK_1

#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1   0x00000D11

Definition at line 2414 of file GoldmontMsr.h.

MSR_GOLDMONT_IA32_L2_QOS_MASK_2

#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2   0x00000D12

Definition at line 2415 of file GoldmontMsr.h.

MSR_GOLDMONT_IA32_L2_QOS_MASK_3

#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3   0x00000D13

Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.

Parameters

ECX	MSR_GOLDMONT_IA32_L2_QOS_MASK_3
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.

Example usage

MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);
AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);

Note

MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.

Definition at line 2463 of file GoldmontMsr.h.

MSR_GOLDMONT_IA32_MISC_ENABLE

#define MSR_GOLDMONT_IA32_MISC_ENABLE   0x000001A0

Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters

ECX	MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);

Note

MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

Definition at line 315 of file GoldmontMsr.h.

MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET

#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET   0x00000390

Core. See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".

Parameters

ECX	MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.

Example usage

MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);
AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);

Note

MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.

Definition at line 894 of file GoldmontMsr.h.

MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET

#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET   0x00000391

Core. See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".

Parameters

ECX	MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.

Example usage

MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);
AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);

Note

MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.

Definition at line 990 of file GoldmontMsr.h.

MSR_GOLDMONT_IA32_PQR_ASSOC

#define MSR_GOLDMONT_IA32_PQR_ASSOC   0x00000C8F

Core. Resource Association Register (R/W).

Parameters

ECX	MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.

Example usage

MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);
AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);

Note

MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.

Definition at line 2368 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_0_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP   0x00000680

Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_GOLDMONT_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.

Example usage

MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);
AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);

Note

MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM. MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.

Definition at line 2161 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_0_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP   0x000006C0

Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.

Parameters

ECX	MSR_GOLDMONT_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.

Example usage

MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);

Note

MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM. MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.

Definition at line 2284 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_10_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP   0x0000068A

Definition at line 2171 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_10_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP   0x000006CA

Definition at line 2294 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_11_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP   0x0000068B

Definition at line 2172 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_11_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP   0x000006CB

Definition at line 2295 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_12_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP   0x0000068C

Definition at line 2173 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_12_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP   0x000006CC

Definition at line 2296 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_13_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP   0x0000068D

Definition at line 2174 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_13_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP   0x000006CD

Definition at line 2297 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_14_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP   0x0000068E

Definition at line 2175 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_14_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP   0x000006CE

Definition at line 2298 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_15_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP   0x0000068F

Definition at line 2176 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_15_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP   0x000006CF

Definition at line 2299 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_16_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP   0x00000690

Definition at line 2177 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_16_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP   0x000006D0

Definition at line 2300 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_17_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP   0x00000691

Definition at line 2178 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_17_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP   0x000006D1

Definition at line 2301 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_18_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP   0x00000692

Definition at line 2179 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_18_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP   0x000006D2

Definition at line 2302 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_19_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP   0x00000693

Definition at line 2180 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_19_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP   0x000006D3

Definition at line 2303 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_1_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP   0x00000681

Definition at line 2162 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_1_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP   0x000006C1

Definition at line 2285 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_20_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP   0x00000694

Definition at line 2181 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_20_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP   0x000006D4

Definition at line 2304 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_21_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP   0x00000695

Definition at line 2182 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_21_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP   0x000006D5

Definition at line 2305 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_22_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP   0x00000696

Definition at line 2183 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_22_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP   0x000006D6

Definition at line 2306 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_23_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP   0x00000697

Definition at line 2184 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_23_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP   0x000006D7

Definition at line 2307 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_24_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP   0x00000698

Definition at line 2185 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_24_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP   0x000006D8

Definition at line 2308 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_25_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP   0x00000699

Definition at line 2186 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_25_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP   0x000006D9

Definition at line 2309 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_26_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP   0x0000069A

Definition at line 2187 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_26_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP   0x000006DA

Definition at line 2310 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_27_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP   0x0000069B

Definition at line 2188 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_27_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP   0x000006DB

Definition at line 2311 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_28_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP   0x0000069C

Definition at line 2189 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_28_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP   0x000006DC

Definition at line 2312 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_29_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP   0x0000069D

Definition at line 2190 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_29_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP   0x000006DD

Definition at line 2313 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_2_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP   0x00000682

Definition at line 2163 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_2_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP   0x000006C2

Definition at line 2286 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_30_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP   0x0000069E

Definition at line 2191 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_30_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP   0x000006DE

Definition at line 2314 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_31_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP   0x0000069F

Definition at line 2192 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_31_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP   0x000006DF

Definition at line 2315 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_3_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP   0x00000683

Definition at line 2164 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_3_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP   0x000006C3

Definition at line 2287 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_4_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP   0x00000684

Definition at line 2165 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_4_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP   0x000006C4

Definition at line 2288 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_5_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP   0x00000685

Definition at line 2166 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_5_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP   0x000006C5

Definition at line 2289 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_6_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP   0x00000686

Definition at line 2167 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_6_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP   0x000006C6

Definition at line 2290 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_7_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP   0x00000687

Definition at line 2168 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_7_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP   0x000006C7

Definition at line 2291 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_8_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP   0x00000688

Definition at line 2169 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_8_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP   0x000006C8

Definition at line 2292 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_9_FROM_IP

#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP   0x00000689

Definition at line 2170 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_9_TO_IP

#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP   0x000006C9

Definition at line 2293 of file GoldmontMsr.h.

MSR_GOLDMONT_LASTBRANCH_TOS

#define MSR_GOLDMONT_LASTBRANCH_TOS   0x000001C9

Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP.

Parameters

ECX	MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);

Note

MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

Definition at line 777 of file GoldmontMsr.h.

MSR_GOLDMONT_LBR_SELECT

#define MSR_GOLDMONT_LBR_SELECT   0x000001C8

Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, "Filtering of Last Branch Records.".

Parameters

ECX	MSR_GOLDMONT_LBR_SELECT (0x000001C8)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.

Example usage

MSR_GOLDMONT_LBR_SELECT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);
AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);

Note

MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.

Definition at line 696 of file GoldmontMsr.h.

MSR_GOLDMONT_MISC_FEATURE_CONTROL

#define MSR_GOLDMONT_MISC_FEATURE_CONTROL   0x000001A4

Miscellaneous Feature Control (R/W).

Parameters

ECX	MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.

Example usage

MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);

Note

MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.

Definition at line 415 of file GoldmontMsr.h.

MSR_GOLDMONT_MISC_PWR_MGMT

#define MSR_GOLDMONT_MISC_PWR_MGMT   0x000001AA

Package. See http://biosbits.org.

Parameters

ECX	MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.

Example usage

MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);
AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);

Note

MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.

Definition at line 469 of file GoldmontMsr.h.

MSR_GOLDMONT_PEBS_ENABLE

#define MSR_GOLDMONT_PEBS_ENABLE   0x000003F1

Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling (PEBS).".

Parameters

ECX	MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.

Example usage

MSR_GOLDMONT_PEBS_ENABLE_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);
AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);

Note

MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.

Definition at line 1083 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_C10_RESIDENCY

#define MSR_GOLDMONT_PKG_C10_RESIDENCY   0x00000632

Package. Note: C-state values are processor specific C-state code names,. Package C10 Residency Counter. (R/O) Value since last reset that the entire SOC is in an S0i3 state. Count at the same frequency as the TSC.

Parameters

ECX	MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);
AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);

Note

MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.

Definition at line 1851 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_C2_RESIDENCY

#define MSR_GOLDMONT_PKG_C2_RESIDENCY   0x0000060D

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C2 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);
AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);

Note

MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.

Definition at line 1644 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_C3_RESIDENCY

#define MSR_GOLDMONT_PKG_C3_RESIDENCY   0x000003F8

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C3 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);
AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);

Note

MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.

Definition at line 1130 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_C6_RESIDENCY

#define MSR_GOLDMONT_PKG_C6_RESIDENCY   0x000003F9

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C6 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);

Note

MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.

Definition at line 1151 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL

#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL   0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. See http://biosbits.org.

Parameters

ECX	MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

Note

MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

Definition at line 200 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_ENERGY_STATUS

#define MSR_GOLDMONT_PKG_ENERGY_STATUS   0x00000611

Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".

Parameters

ECX	MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);

Note

MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.

Definition at line 1680 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_PERF_STATUS

#define MSR_GOLDMONT_PKG_PERF_STATUS   0x00000613

Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".

Parameters

ECX	MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);

Note

MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.

Definition at line 1697 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_POWER_INFO

#define MSR_GOLDMONT_PKG_POWER_INFO   0x00000614

Package. PKG RAPL Parameters (R/W).

Parameters

ECX	MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.

Example usage

MSR_GOLDMONT_PKG_POWER_INFO_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);
AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);

Note

MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.

Definition at line 1717 of file GoldmontMsr.h.

MSR_GOLDMONT_PKG_POWER_LIMIT

#define MSR_GOLDMONT_PKG_POWER_LIMIT   0x00000610

Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package RAPL Domain.".

Parameters

ECX	MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);
AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);

Note

MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.

Definition at line 1663 of file GoldmontMsr.h.

MSR_GOLDMONT_PKGC3_IRTL

#define MSR_GOLDMONT_PKGC3_IRTL   0x0000060A

Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates.

Parameters

ECX	MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.

Example usage

MSR_GOLDMONT_PKGC3_IRTL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);
AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);

Note

MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.

Definition at line 1459 of file GoldmontMsr.h.

MSR_GOLDMONT_PKGC_IRTL1

#define MSR_GOLDMONT_PKGC_IRTL1   0x0000060B

Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines the interrupt response time limit used by the processor to manage transition to package C6 or C7S state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates.

Parameters

ECX	MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.

Example usage

MSR_GOLDMONT_PKGC_IRTL1_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);
AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);

Note

MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.

Definition at line 1522 of file GoldmontMsr.h.

MSR_GOLDMONT_PKGC_IRTL2

#define MSR_GOLDMONT_PKGC_IRTL2   0x0000060C

Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the interrupt response time limit used by the processor to manage transition to package C7 state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates.

Parameters

ECX	MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.

Example usage

MSR_GOLDMONT_PKGC_IRTL2_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);
AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);

Note

MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.

Definition at line 1584 of file GoldmontMsr.h.

MSR_GOLDMONT_PLATFORM_INFO

#define MSR_GOLDMONT_PLATFORM_INFO   0x000000CE

Package. See http://biosbits.org.

Parameters

ECX	MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.

Example usage

MSR_GOLDMONT_PLATFORM_INFO_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);
AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);

Note

MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.

Definition at line 124 of file GoldmontMsr.h.

MSR_GOLDMONT_POWER_CTL

#define MSR_GOLDMONT_POWER_CTL   0x000001FC

Core. Power Control Register. See http://biosbits.org.

Parameters

ECX	MSR_GOLDMONT_POWER_CTL (0x000001FC)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.

Example usage

MSR_GOLDMONT_POWER_CTL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);
AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);

Note

MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.

Definition at line 797 of file GoldmontMsr.h.

MSR_GOLDMONT_PP0_ENERGY_STATUS

#define MSR_GOLDMONT_PP0_ENERGY_STATUS   0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);

Note

MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

Definition at line 1869 of file GoldmontMsr.h.

MSR_GOLDMONT_PP1_ENERGY_STATUS

#define MSR_GOLDMONT_PP1_ENERGY_STATUS   0x00000641

Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);

Note

MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.

Definition at line 1887 of file GoldmontMsr.h.

MSR_GOLDMONT_RAPL_POWER_UNIT

#define MSR_GOLDMONT_RAPL_POWER_UNIT   0x00000606

Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, "RAPL Interfaces.".

Parameters

ECX	MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.

Example usage

MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);

Note

MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.

Definition at line 1393 of file GoldmontMsr.h.

MSR_GOLDMONT_SGXOWNER0

#define MSR_GOLDMONT_SGXOWNER0   MSR_GOLDMONT_SGXOWNEREPOCH0

Definition at line 850 of file GoldmontMsr.h.

MSR_GOLDMONT_SGXOWNER1

#define MSR_GOLDMONT_SGXOWNER1   MSR_GOLDMONT_SGXOWNEREPOCH1

Definition at line 873 of file GoldmontMsr.h.

MSR_GOLDMONT_SGXOWNEREPOCH0

#define MSR_GOLDMONT_SGXOWNEREPOCH0   0x00000300

Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. Lower 64 bits of an 128-bit external entropy value for key derivation of an enclave.

Parameters

ECX	MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);

Note

MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.

Definition at line 845 of file GoldmontMsr.h.

MSR_GOLDMONT_SGXOWNEREPOCH1

#define MSR_GOLDMONT_SGXOWNEREPOCH1   0x00000301

Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of an 128-bit external entropy value for key derivation of an enclave.

Parameters

ECX	MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);

Note

MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.

Definition at line 868 of file GoldmontMsr.h.

MSR_GOLDMONT_SMM_BLOCKED

#define MSR_GOLDMONT_SMM_BLOCKED   0x000004E3

Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical processors in the package. Available only while in SMM.

Parameters

ECX	MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.

Example usage

MSR_GOLDMONT_SMM_BLOCKED_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);
AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);

Note

MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.

Definition at line 1272 of file GoldmontMsr.h.

MSR_GOLDMONT_SMM_DELAYED

#define MSR_GOLDMONT_SMM_DELAYED   0x000004E2

Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical processors in the package. Available only while in SMM and MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.

Parameters

ECX	MSR_GOLDMONT_SMM_DELAYED (0x000004E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.

Example usage

MSR_GOLDMONT_SMM_DELAYED_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);
AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);

Note

MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.

Definition at line 1251 of file GoldmontMsr.h.

MSR_GOLDMONT_SMM_FEATURE_CONTROL

#define MSR_GOLDMONT_SMM_FEATURE_CONTROL   0x000004E0

Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters

ECX	MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.

Example usage

MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);

Note

MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.

Definition at line 1193 of file GoldmontMsr.h.

MSR_GOLDMONT_SMM_MCA_CAP

#define MSR_GOLDMONT_SMM_MCA_CAP   0x0000017D

Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters

ECX	MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.

Example usage

MSR_GOLDMONT_SMM_MCA_CAP_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);
AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);

Note

MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.

Definition at line 264 of file GoldmontMsr.h.

MSR_GOLDMONT_TURBO_ACTIVATION_RATIO

#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO   0x0000064C

Package. ConfigTDP Control (R/W).

Parameters

ECX	MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.

Example usage

MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);
AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);

Note

MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.

Definition at line 1907 of file GoldmontMsr.h.

MSR_GOLDMONT_TURBO_GROUP_CORECNT

#define MSR_GOLDMONT_TURBO_GROUP_CORECNT   0x000001AE

Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of 0 threshold is ignored.

Parameters

ECX	MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.

Example usage

MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);
AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);

Note

MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.

Definition at line 612 of file GoldmontMsr.h.

MSR_GOLDMONT_TURBO_RATIO_LIMIT

#define MSR_GOLDMONT_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies Maximum Ratio Limit for each Core Group. Max ratio for groups with more cores must decrease monotonically. For groups with less than 4 cores, the max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must be 22 or less. For groups with more than 5 cores, the max ratio must be 16 or less..

Parameters

ECX	MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);

Note

MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

Definition at line 528 of file GoldmontMsr.h.

MSR_IA32_RTIT_CTL

#define MSR_IA32_RTIT_CTL   0x00000570

Core. Trace Control Register (R/W).

Parameters

ECX	MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)
EAX	Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.

Example usage

MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);
AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);

Note

MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.

Definition at line 1292 of file GoldmontMsr.h.