HaswellEMsr.h

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#ifndef __HASWELL_E_MSR_H__
#define __HASWELL_E_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x3F    \
    )                       \
   )
 
#define MSR_HASWELL_E_CORE_THREAD_COUNT  0x00000035
 
typedef union {
  struct {
    UINT32    Core_Count   : 16;
    UINT32    Thread_Count : 16;
    UINT32    Reserved     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;
 
#define MSR_HASWELL_E_THREAD_ID_INFO  0x00000053
 
typedef union {
  struct {
    UINT32    Logical_Processor_ID : 8;
    UINT32    Reserved1            : 24;
    UINT32    Reserved2            : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;
 
#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL  0x000000E2
 
typedef union {
  struct {
    UINT32    Limit            : 3;
    UINT32    Reserved1        : 7;
    UINT32    IO_MWAIT         : 1;
    UINT32    Reserved2        : 4;
    UINT32    CFGLock          : 1;
    UINT32    Reserved3        : 9;
    UINT32    C3AutoDemotion   : 1;
    UINT32    C1AutoDemotion   : 1;
    UINT32    C3Undemotion     : 1;
    UINT32    C1Undemotion     : 1;
    UINT32    CStateDemotion   : 1;
    UINT32    CStateUndemotion : 1;
    UINT32    Reserved4        : 1;
    UINT32    Reserved5        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;
 
#define MSR_HASWELL_E_IA32_MCG_CAP  0x00000179
 
typedef union {
  struct {
    UINT32    Count       : 8;
    UINT32    MCG_CTL_P   : 1;
    UINT32    MCG_EXT_P   : 1;
    UINT32    MCP_CMCI_P  : 1;
    UINT32    MCG_TES_P   : 1;
    UINT32    Reserved1   : 4;
    UINT32    MCG_EXT_CNT : 8;
    UINT32    MCG_SER_P   : 1;
    UINT32    MCG_EM_P    : 1;
    UINT32    MCG_ELOG_P  : 1;
    UINT32    Reserved2   : 5;
    UINT32    Reserved3   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;
 
#define MSR_HASWELL_E_SMM_MCA_CAP  0x0000017D
 
typedef union {
  struct {
    UINT32    Reserved1            : 32;
    UINT32    Reserved2            : 26;
    UINT32    SMM_Code_Access_Chk  : 1;
    UINT32    Long_Flow_Indication : 1;
    UINT32    Reserved3            : 4;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;
 
#define MSR_HASWELL_E_ERROR_CONTROL  0x0000017F
 
typedef union {
  struct {
    UINT32    Reserved1         : 1;
    UINT32    MemErrorLogEnable : 1;
    UINT32    Reserved2         : 30;
    UINT32    Reserved3         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;
 
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT  0x000001AD
 
typedef union {
  struct {
    UINT32    Maximum1C : 8;
    UINT32    Maximum2C : 8;
    UINT32    Maximum3C : 8;
    UINT32    Maximum4C : 8;
    UINT32    Maximum5C : 8;
    UINT32    Maximum6C : 8;
    UINT32    Maximum7C : 8;
    UINT32    Maximum8C : 8;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;
 
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1  0x000001AE
 
typedef union {
  struct {
    UINT32    Maximum9C  : 8;
    UINT32    Maximum10C : 8;
    UINT32    Maximum11C : 8;
    UINT32    Maximum12C : 8;
    UINT32    Maximum13C : 8;
    UINT32    Maximum14C : 8;
    UINT32    Maximum15C : 8;
    UINT32    Maximum16C : 8;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;
 
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2  0x000001AF
 
typedef union {
  struct {
    UINT32    Maximum17C                            : 8;
    UINT32    Maximum18C                            : 8;
    UINT32    Reserved1                             : 16;
    UINT32    Reserved2                             : 31;
    UINT32    TurboRatioLimitConfigurationSemaphore : 1;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;
 
#define MSR_HASWELL_E_RAPL_POWER_UNIT  0x00000606
 
typedef union {
  struct {
    UINT32    PowerUnits        : 4;
    UINT32    Reserved1         : 4;
    UINT32    EnergyStatusUnits : 5;
    UINT32    Reserved2         : 3;
    UINT32    TimeUnits         : 4;
    UINT32    Reserved3         : 12;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;
 
#define MSR_HASWELL_E_DRAM_POWER_LIMIT  0x00000618
 
#define MSR_HASWELL_E_DRAM_ENERGY_STATUS  0x00000619
 
typedef union {
  struct {
    UINT32    Energy   : 32;
    UINT32    Reserved : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;
 
#define MSR_HASWELL_E_DRAM_PERF_STATUS  0x0000061B
 
#define MSR_HASWELL_E_DRAM_POWER_INFO  0x0000061C
 
#define MSR_HASWELL_E_PCIE_PLL_RATIO  0x0000061E
 
typedef union {
  struct {
    UINT32    PCIERatio  : 2;
    UINT32    LPLLSelect : 1;
    UINT32    LONGRESET  : 1;
    UINT32    Reserved1  : 28;
    UINT32    Reserved2  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;
 
#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT  0x00000620
 
typedef union {
  struct {
    UINT32    MAX_RATIO : 7;
    UINT32    Reserved1 : 1;
    UINT32    MIN_RATIO : 7;
    UINT32    Reserved2 : 17;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
 
#define MSR_HASWELL_E_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS  0x00000690
 
typedef union {
  struct {
    UINT32    PROCHOT_Status                                   : 1;
    UINT32    ThermalStatus                                    : 1;
    UINT32    PowerBudgetManagementStatus                      : 1;
    UINT32    PlatformConfigurationServicesStatus              : 1;
    UINT32    Reserved1                                        : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlStatus : 1;
    UINT32    VRThermAlertStatus                               : 1;
    UINT32    Reserved2                                        : 1;
    UINT32    ElectricalDesignPointStatus                      : 1;
    UINT32    Reserved3                                        : 1;
    UINT32    MultiCoreTurboStatus                             : 1;
    UINT32    Reserved4                                        : 2;
    UINT32    FrequencyP1Status                                : 1;
    UINT32    TurboFrequencyLimitingStatus                     : 1;
    UINT32    FrequencyLimitingStatus                          : 1;
    UINT32    PROCHOT_Log                                      : 1;
    UINT32    ThermalLog                                       : 1;
    UINT32    PowerBudgetManagementLog                         : 1;
    UINT32    PlatformConfigurationServicesLog                 : 1;
    UINT32    Reserved5                                        : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlLog    : 1;
    UINT32    VRThermAlertLog                                  : 1;
    UINT32    Reserved6                                        : 1;
    UINT32    ElectricalDesignPointLog                         : 1;
    UINT32    Reserved7                                        : 1;
    UINT32    MultiCoreTurboLog                                : 1;
    UINT32    Reserved8                                        : 2;
    UINT32    CoreFrequencyP1Log                               : 1;
    UINT32    TurboFrequencyLimitingLog                        : 1;
    UINT32    CoreFrequencyLimitingLog                         : 1;
    UINT32    Reserved9                                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_HASWELL_E_IA32_QM_EVTSEL  0x00000C8D
 
typedef union {
  struct {
    UINT32    EventID   : 8;
    UINT32    Reserved1 : 24;
    UINT32    RMID      : 10;
    UINT32    Reserved2 : 22;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;
 
#define MSR_HASWELL_E_IA32_PQR_ASSOC  0x00000C8F
 
typedef union {
  struct {
    UINT32    RMID      : 10;
    UINT32    Reserved1 : 22;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;
 
#define MSR_HASWELL_E_PMON_GLOBAL_CTL  0x00000700
 
#define MSR_HASWELL_E_PMON_GLOBAL_STATUS  0x00000701
 
#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG  0x00000702
 
#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL  0x00000703
 
#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR  0x00000704
 
#define MSR_HASWELL_E_U_PMON_EVNTSEL0  0x00000705
 
#define MSR_HASWELL_E_U_PMON_EVNTSEL1  0x00000706
 
#define MSR_HASWELL_E_U_PMON_BOX_STATUS  0x00000708
 
#define MSR_HASWELL_E_U_PMON_CTR0  0x00000709
 
#define MSR_HASWELL_E_U_PMON_CTR1  0x0000070A
 
#define MSR_HASWELL_E_PCU_PMON_BOX_CTL  0x00000710
 
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0  0x00000711
 
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1  0x00000712
 
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2  0x00000713
 
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3  0x00000714
 
#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER  0x00000715
 
#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS  0x00000716
 
#define MSR_HASWELL_E_PCU_PMON_CTR0  0x00000717
 
#define MSR_HASWELL_E_PCU_PMON_CTR1  0x00000718
 
#define MSR_HASWELL_E_PCU_PMON_CTR2  0x00000719
 
#define MSR_HASWELL_E_PCU_PMON_CTR3  0x0000071A
 
#define MSR_HASWELL_E_S0_PMON_BOX_CTL  0x00000720
 
#define MSR_HASWELL_E_S0_PMON_EVNTSEL0  0x00000721
 
#define MSR_HASWELL_E_S0_PMON_EVNTSEL1  0x00000722
 
#define MSR_HASWELL_E_S0_PMON_EVNTSEL2  0x00000723
 
#define MSR_HASWELL_E_S0_PMON_EVNTSEL3  0x00000724
 
#define MSR_HASWELL_E_S0_PMON_BOX_FILTER  0x00000725
 
#define MSR_HASWELL_E_S0_PMON_CTR0  0x00000726
 
#define MSR_HASWELL_E_S0_PMON_CTR1  0x00000727
 
#define MSR_HASWELL_E_S0_PMON_CTR2  0x00000728
 
#define MSR_HASWELL_E_S0_PMON_CTR3  0x00000729
 
#define MSR_HASWELL_E_S1_PMON_BOX_CTL  0x0000072A
 
#define MSR_HASWELL_E_S1_PMON_EVNTSEL0  0x0000072B
 
#define MSR_HASWELL_E_S1_PMON_EVNTSEL1  0x0000072C
 
#define MSR_HASWELL_E_S1_PMON_EVNTSEL2  0x0000072D
 
#define MSR_HASWELL_E_S1_PMON_EVNTSEL3  0x0000072E
 
#define MSR_HASWELL_E_S1_PMON_BOX_FILTER  0x0000072F
 
#define MSR_HASWELL_E_S1_PMON_CTR0  0x00000730
 
#define MSR_HASWELL_E_S1_PMON_CTR1  0x00000731
 
#define MSR_HASWELL_E_S1_PMON_CTR2  0x00000732
 
#define MSR_HASWELL_E_S1_PMON_CTR3  0x00000733
 
#define MSR_HASWELL_E_S2_PMON_BOX_CTL  0x00000734
 
#define MSR_HASWELL_E_S2_PMON_EVNTSEL0  0x00000735
 
#define MSR_HASWELL_E_S2_PMON_EVNTSEL1  0x00000736
 
#define MSR_HASWELL_E_S2_PMON_EVNTSEL2  0x00000737
 
#define MSR_HASWELL_E_S2_PMON_EVNTSEL3  0x00000738
 
#define MSR_HASWELL_E_S2_PMON_BOX_FILTER  0x00000739
 
#define MSR_HASWELL_E_S2_PMON_CTR0  0x0000073A
 
#define MSR_HASWELL_E_S2_PMON_CTR1  0x0000073B
 
#define MSR_HASWELL_E_S2_PMON_CTR2  0x0000073C
 
#define MSR_HASWELL_E_S2_PMON_CTR3  0x0000073D
 
#define MSR_HASWELL_E_S3_PMON_BOX_CTL  0x0000073E
 
#define MSR_HASWELL_E_S3_PMON_EVNTSEL0  0x0000073F
 
#define MSR_HASWELL_E_S3_PMON_EVNTSEL1  0x00000740
 
#define MSR_HASWELL_E_S3_PMON_EVNTSEL2  0x00000741
 
#define MSR_HASWELL_E_S3_PMON_EVNTSEL3  0x00000742
 
#define MSR_HASWELL_E_S3_PMON_BOX_FILTER  0x00000743
 
#define MSR_HASWELL_E_S3_PMON_CTR0  0x00000744
 
#define MSR_HASWELL_E_S3_PMON_CTR1  0x00000745
 
#define MSR_HASWELL_E_S3_PMON_CTR2  0x00000746
 
#define MSR_HASWELL_E_S3_PMON_CTR3  0x00000747
 
#define MSR_HASWELL_E_C0_PMON_BOX_CTL  0x00000E00
 
#define MSR_HASWELL_E_C0_PMON_EVNTSEL0  0x00000E01
 
#define MSR_HASWELL_E_C0_PMON_EVNTSEL1  0x00000E02
 
#define MSR_HASWELL_E_C0_PMON_EVNTSEL2  0x00000E03
 
#define MSR_HASWELL_E_C0_PMON_EVNTSEL3  0x00000E04
 
#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0  0x00000E05
 
#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1  0x00000E06
 
#define MSR_HASWELL_E_C0_PMON_BOX_STATUS  0x00000E07
 
#define MSR_HASWELL_E_C0_PMON_CTR0  0x00000E08
 
#define MSR_HASWELL_E_C0_PMON_CTR1  0x00000E09
 
#define MSR_HASWELL_E_C0_PMON_CTR2  0x00000E0A
 
#define MSR_HASWELL_E_C0_PMON_CTR3  0x00000E0B
 
#define MSR_HASWELL_E_C1_PMON_BOX_CTL  0x00000E10
 
#define MSR_HASWELL_E_C1_PMON_EVNTSEL0  0x00000E11
 
#define MSR_HASWELL_E_C1_PMON_EVNTSEL1  0x00000E12
 
#define MSR_HASWELL_E_C1_PMON_EVNTSEL2  0x00000E13
 
#define MSR_HASWELL_E_C1_PMON_EVNTSEL3  0x00000E14
 
#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0  0x00000E15
 
#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1  0x00000E16
 
#define MSR_HASWELL_E_C1_PMON_BOX_STATUS  0x00000E17
 
#define MSR_HASWELL_E_C1_PMON_CTR0  0x00000E18
 
#define MSR_HASWELL_E_C1_PMON_CTR1  0x00000E19
 
#define MSR_HASWELL_E_C1_PMON_CTR2  0x00000E1A
 
#define MSR_HASWELL_E_C1_PMON_CTR3  0x00000E1B
 
#define MSR_HASWELL_E_C2_PMON_BOX_CTL  0x00000E20
 
#define MSR_HASWELL_E_C2_PMON_EVNTSEL0  0x00000E21
 
#define MSR_HASWELL_E_C2_PMON_EVNTSEL1  0x00000E22
 
#define MSR_HASWELL_E_C2_PMON_EVNTSEL2  0x00000E23
 
#define MSR_HASWELL_E_C2_PMON_EVNTSEL3  0x00000E24
 
#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0  0x00000E25
 
#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1  0x00000E26
 
#define MSR_HASWELL_E_C2_PMON_BOX_STATUS  0x00000E27
 
#define MSR_HASWELL_E_C2_PMON_CTR0  0x00000E28
 
#define MSR_HASWELL_E_C2_PMON_CTR1  0x00000E29
 
#define MSR_HASWELL_E_C2_PMON_CTR2  0x00000E2A
 
#define MSR_HASWELL_E_C2_PMON_CTR3  0x00000E2B
 
#define MSR_HASWELL_E_C3_PMON_BOX_CTL  0x00000E30
 
#define MSR_HASWELL_E_C3_PMON_EVNTSEL0  0x00000E31
 
#define MSR_HASWELL_E_C3_PMON_EVNTSEL1  0x00000E32
 
#define MSR_HASWELL_E_C3_PMON_EVNTSEL2  0x00000E33
 
#define MSR_HASWELL_E_C3_PMON_EVNTSEL3  0x00000E34
 
#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0  0x00000E35
 
#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1  0x00000E36
 
#define MSR_HASWELL_E_C3_PMON_BOX_STATUS  0x00000E37
 
#define MSR_HASWELL_E_C3_PMON_CTR0  0x00000E38
 
#define MSR_HASWELL_E_C3_PMON_CTR1  0x00000E39
 
#define MSR_HASWELL_E_C3_PMON_CTR2  0x00000E3A
 
#define MSR_HASWELL_E_C3_PMON_CTR3  0x00000E3B
 
#define MSR_HASWELL_E_C4_PMON_BOX_CTL  0x00000E40
 
#define MSR_HASWELL_E_C4_PMON_EVNTSEL0  0x00000E41
 
#define MSR_HASWELL_E_C4_PMON_EVNTSEL1  0x00000E42
 
#define MSR_HASWELL_E_C4_PMON_EVNTSEL2  0x00000E43
 
#define MSR_HASWELL_E_C4_PMON_EVNTSEL3  0x00000E44
 
#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0  0x00000E45
 
#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1  0x00000E46
 
#define MSR_HASWELL_E_C4_PMON_BOX_STATUS  0x00000E47
 
#define MSR_HASWELL_E_C4_PMON_CTR0  0x00000E48
 
#define MSR_HASWELL_E_C4_PMON_CTR1  0x00000E49
 
#define MSR_HASWELL_E_C4_PMON_CTR2  0x00000E4A
 
#define MSR_HASWELL_E_C4_PMON_CTR3  0x00000E4B
 
#define MSR_HASWELL_E_C5_PMON_BOX_CTL  0x00000E50
 
#define MSR_HASWELL_E_C5_PMON_EVNTSEL0  0x00000E51
 
#define MSR_HASWELL_E_C5_PMON_EVNTSEL1  0x00000E52
 
#define MSR_HASWELL_E_C5_PMON_EVNTSEL2  0x00000E53
 
#define MSR_HASWELL_E_C5_PMON_EVNTSEL3  0x00000E54
 
#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0  0x00000E55
 
#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1  0x00000E56
 
#define MSR_HASWELL_E_C5_PMON_BOX_STATUS  0x00000E57
 
#define MSR_HASWELL_E_C5_PMON_CTR0  0x00000E58
 
#define MSR_HASWELL_E_C5_PMON_CTR1  0x00000E59
 
#define MSR_HASWELL_E_C5_PMON_CTR2  0x00000E5A
 
#define MSR_HASWELL_E_C5_PMON_CTR3  0x00000E5B
 
#define MSR_HASWELL_E_C6_PMON_BOX_CTL  0x00000E60
 
#define MSR_HASWELL_E_C6_PMON_EVNTSEL0  0x00000E61
 
#define MSR_HASWELL_E_C6_PMON_EVNTSEL1  0x00000E62
 
#define MSR_HASWELL_E_C6_PMON_EVNTSEL2  0x00000E63
 
#define MSR_HASWELL_E_C6_PMON_EVNTSEL3  0x00000E64
 
#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0  0x00000E65
 
#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1  0x00000E66
 
#define MSR_HASWELL_E_C6_PMON_BOX_STATUS  0x00000E67
 
#define MSR_HASWELL_E_C6_PMON_CTR0  0x00000E68
 
#define MSR_HASWELL_E_C6_PMON_CTR1  0x00000E69
 
#define MSR_HASWELL_E_C6_PMON_CTR2  0x00000E6A
 
#define MSR_HASWELL_E_C6_PMON_CTR3  0x00000E6B
 
#define MSR_HASWELL_E_C7_PMON_BOX_CTL  0x00000E70
 
#define MSR_HASWELL_E_C7_PMON_EVNTSEL0  0x00000E71
 
#define MSR_HASWELL_E_C7_PMON_EVNTSEL1  0x00000E72
 
#define MSR_HASWELL_E_C7_PMON_EVNTSEL2  0x00000E73
 
#define MSR_HASWELL_E_C7_PMON_EVNTSEL3  0x00000E74
 
#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0  0x00000E75
 
#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1  0x00000E76
 
#define MSR_HASWELL_E_C7_PMON_BOX_STATUS  0x00000E77
 
#define MSR_HASWELL_E_C7_PMON_CTR0  0x00000E78
 
#define MSR_HASWELL_E_C7_PMON_CTR1  0x00000E79
 
#define MSR_HASWELL_E_C7_PMON_CTR2  0x00000E7A
 
#define MSR_HASWELL_E_C7_PMON_CTR3  0x00000E7B
 
#define MSR_HASWELL_E_C8_PMON_BOX_CTL  0x00000E80
 
#define MSR_HASWELL_E_C8_PMON_EVNTSEL0  0x00000E81
 
#define MSR_HASWELL_E_C8_PMON_EVNTSEL1  0x00000E82
 
#define MSR_HASWELL_E_C8_PMON_EVNTSEL2  0x00000E83
 
#define MSR_HASWELL_E_C8_PMON_EVNTSEL3  0x00000E84
 
#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0  0x00000E85
 
#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1  0x00000E86
 
#define MSR_HASWELL_E_C8_PMON_BOX_STATUS  0x00000E87
 
#define MSR_HASWELL_E_C8_PMON_CTR0  0x00000E88
 
#define MSR_HASWELL_E_C8_PMON_CTR1  0x00000E89
 
#define MSR_HASWELL_E_C8_PMON_CTR2  0x00000E8A
 
#define MSR_HASWELL_E_C8_PMON_CTR3  0x00000E8B
 
#define MSR_HASWELL_E_C9_PMON_BOX_CTL  0x00000E90
 
#define MSR_HASWELL_E_C9_PMON_EVNTSEL0  0x00000E91
 
#define MSR_HASWELL_E_C9_PMON_EVNTSEL1  0x00000E92
 
#define MSR_HASWELL_E_C9_PMON_EVNTSEL2  0x00000E93
 
#define MSR_HASWELL_E_C9_PMON_EVNTSEL3  0x00000E94
 
#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0  0x00000E95
 
#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1  0x00000E96
 
#define MSR_HASWELL_E_C9_PMON_BOX_STATUS  0x00000E97
 
#define MSR_HASWELL_E_C9_PMON_CTR0  0x00000E98
 
#define MSR_HASWELL_E_C9_PMON_CTR1  0x00000E99
 
#define MSR_HASWELL_E_C9_PMON_CTR2  0x00000E9A
 
#define MSR_HASWELL_E_C9_PMON_CTR3  0x00000E9B
 
#define MSR_HASWELL_E_C10_PMON_BOX_CTL  0x00000EA0
 
#define MSR_HASWELL_E_C10_PMON_EVNTSEL0  0x00000EA1
 
#define MSR_HASWELL_E_C10_PMON_EVNTSEL1  0x00000EA2
 
#define MSR_HASWELL_E_C10_PMON_EVNTSEL2  0x00000EA3
 
#define MSR_HASWELL_E_C10_PMON_EVNTSEL3  0x00000EA4
 
#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0  0x00000EA5
 
#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1  0x00000EA6
 
#define MSR_HASWELL_E_C10_PMON_BOX_STATUS  0x00000EA7
 
#define MSR_HASWELL_E_C10_PMON_CTR0  0x00000EA8
 
#define MSR_HASWELL_E_C10_PMON_CTR1  0x00000EA9
 
#define MSR_HASWELL_E_C10_PMON_CTR2  0x00000EAA
 
#define MSR_HASWELL_E_C10_PMON_CTR3  0x00000EAB
 
#define MSR_HASWELL_E_C11_PMON_BOX_CTL  0x00000EB0
 
#define MSR_HASWELL_E_C11_PMON_EVNTSEL0  0x00000EB1
 
#define MSR_HASWELL_E_C11_PMON_EVNTSEL1  0x00000EB2
 
#define MSR_HASWELL_E_C11_PMON_EVNTSEL2  0x00000EB3
 
#define MSR_HASWELL_E_C11_PMON_EVNTSEL3  0x00000EB4
 
#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0  0x00000EB5
 
#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1  0x00000EB6
 
#define MSR_HASWELL_E_C11_PMON_BOX_STATUS  0x00000EB7
 
#define MSR_HASWELL_E_C11_PMON_CTR0  0x00000EB8
 
#define MSR_HASWELL_E_C11_PMON_CTR1  0x00000EB9
 
#define MSR_HASWELL_E_C11_PMON_CTR2  0x00000EBA
 
#define MSR_HASWELL_E_C11_PMON_CTR3  0x00000EBB
 
#define MSR_HASWELL_E_C12_PMON_BOX_CTL  0x00000EC0
 
#define MSR_HASWELL_E_C12_PMON_EVNTSEL0  0x00000EC1
 
#define MSR_HASWELL_E_C12_PMON_EVNTSEL1  0x00000EC2
 
#define MSR_HASWELL_E_C12_PMON_EVNTSEL2  0x00000EC3
 
#define MSR_HASWELL_E_C12_PMON_EVNTSEL3  0x00000EC4
 
#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0  0x00000EC5
 
#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1  0x00000EC6
 
#define MSR_HASWELL_E_C12_PMON_BOX_STATUS  0x00000EC7
 
#define MSR_HASWELL_E_C12_PMON_CTR0  0x00000EC8
 
#define MSR_HASWELL_E_C12_PMON_CTR1  0x00000EC9
 
#define MSR_HASWELL_E_C12_PMON_CTR2  0x00000ECA
 
#define MSR_HASWELL_E_C12_PMON_CTR3  0x00000ECB
 
#define MSR_HASWELL_E_C13_PMON_BOX_CTL  0x00000ED0
 
#define MSR_HASWELL_E_C13_PMON_EVNTSEL0  0x00000ED1
 
#define MSR_HASWELL_E_C13_PMON_EVNTSEL1  0x00000ED2
 
#define MSR_HASWELL_E_C13_PMON_EVNTSEL2  0x00000ED3
 
#define MSR_HASWELL_E_C13_PMON_EVNTSEL3  0x00000ED4
 
#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0  0x00000ED5
 
#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1  0x00000ED6
 
#define MSR_HASWELL_E_C13_PMON_BOX_STATUS  0x00000ED7
 
#define MSR_HASWELL_E_C13_PMON_CTR0  0x00000ED8
 
#define MSR_HASWELL_E_C13_PMON_CTR1  0x00000ED9
 
#define MSR_HASWELL_E_C13_PMON_CTR2  0x00000EDA
 
#define MSR_HASWELL_E_C13_PMON_CTR3  0x00000EDB
 
#define MSR_HASWELL_E_C14_PMON_BOX_CTL  0x00000EE0
 
#define MSR_HASWELL_E_C14_PMON_EVNTSEL0  0x00000EE1
 
#define MSR_HASWELL_E_C14_PMON_EVNTSEL1  0x00000EE2
 
#define MSR_HASWELL_E_C14_PMON_EVNTSEL2  0x00000EE3
 
#define MSR_HASWELL_E_C14_PMON_EVNTSEL3  0x00000EE4
 
#define MSR_HASWELL_E_C14_PMON_BOX_FILTER  0x00000EE5
 
#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1  0x00000EE6
 
#define MSR_HASWELL_E_C14_PMON_BOX_STATUS  0x00000EE7
 
#define MSR_HASWELL_E_C14_PMON_CTR0  0x00000EE8
 
#define MSR_HASWELL_E_C14_PMON_CTR1  0x00000EE9
 
#define MSR_HASWELL_E_C14_PMON_CTR2  0x00000EEA
 
#define MSR_HASWELL_E_C14_PMON_CTR3  0x00000EEB
 
#define MSR_HASWELL_E_C15_PMON_BOX_CTL  0x00000EF0
 
#define MSR_HASWELL_E_C15_PMON_EVNTSEL0  0x00000EF1
 
#define MSR_HASWELL_E_C15_PMON_EVNTSEL1  0x00000EF2
 
#define MSR_HASWELL_E_C15_PMON_EVNTSEL2  0x00000EF3
 
#define MSR_HASWELL_E_C15_PMON_EVNTSEL3  0x00000EF4
 
#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0  0x00000EF5
 
#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1  0x00000EF6
 
#define MSR_HASWELL_E_C15_PMON_BOX_STATUS  0x00000EF7
 
#define MSR_HASWELL_E_C15_PMON_CTR0  0x00000EF8
 
#define MSR_HASWELL_E_C15_PMON_CTR1  0x00000EF9
 
#define MSR_HASWELL_E_C15_PMON_CTR2  0x00000EFA
 
#define MSR_HASWELL_E_C15_PMON_CTR3  0x00000EFB
 
#define MSR_HASWELL_E_C16_PMON_BOX_CTL  0x00000F00
 
#define MSR_HASWELL_E_C16_PMON_EVNTSEL0  0x00000F01
 
#define MSR_HASWELL_E_C16_PMON_EVNTSEL1  0x00000F02
 
#define MSR_HASWELL_E_C16_PMON_EVNTSEL2  0x00000F03
 
#define MSR_HASWELL_E_C16_PMON_EVNTSEL3  0x00000F04
 
#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0  0x00000F05
 
#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1  0x00000F06
 
#define MSR_HASWELL_E_C16_PMON_BOX_STATUS  0x00000F07
 
#define MSR_HASWELL_E_C16_PMON_CTR0  0x00000F08
 
#define MSR_HASWELL_E_C16_PMON_CTR1  0x00000F09
 
#define MSR_HASWELL_E_C16_PMON_CTR2  0x00000F0A
 
#define MSR_HASWELL_E_C16_PMON_CTR3  0x00000E0B
 
#define MSR_HASWELL_E_C17_PMON_BOX_CTL  0x00000F10
 
#define MSR_HASWELL_E_C17_PMON_EVNTSEL0  0x00000F11
 
#define MSR_HASWELL_E_C17_PMON_EVNTSEL1  0x00000F12
 
#define MSR_HASWELL_E_C17_PMON_EVNTSEL2  0x00000F13
 
#define MSR_HASWELL_E_C17_PMON_EVNTSEL3  0x00000F14
 
#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0  0x00000F15
 
#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1  0x00000F16
 
#define MSR_HASWELL_E_C17_PMON_BOX_STATUS  0x00000F17
 
#define MSR_HASWELL_E_C17_PMON_CTR0  0x00000F18
#define MSR_HASWELL_E_C17_PMON_CTR1  0x00000F19
#define MSR_HASWELL_E_C17_PMON_CTR2  0x00000F1A
#define MSR_HASWELL_E_C17_PMON_CTR3  0x00000F1B
 
#endif