TianoCore EDK2 master
HaswellEMsr.h File Reference

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Data Structures

union  MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
 
union  MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
 
union  MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
 
union  MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
 
union  MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
 
union  MSR_HASWELL_E_ERROR_CONTROL_REGISTER
 
union  MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
 
union  MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
 
union  MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
 
union  MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
 
union  MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER
 
union  MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
 
union  MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER
 
union  MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
 
union  MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
 
union  MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER
 

Macros

#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_HASWELL_E_CORE_THREAD_COUNT   0x00000035
 
#define MSR_HASWELL_E_THREAD_ID_INFO   0x00000053
 
#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL   0x000000E2
 
#define MSR_HASWELL_E_IA32_MCG_CAP   0x00000179
 
#define MSR_HASWELL_E_SMM_MCA_CAP   0x0000017D
 
#define MSR_HASWELL_E_ERROR_CONTROL   0x0000017F
 
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT   0x000001AD
 
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1   0x000001AE
 
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2   0x000001AF
 
#define MSR_HASWELL_E_RAPL_POWER_UNIT   0x00000606
 
#define MSR_HASWELL_E_DRAM_POWER_LIMIT   0x00000618
 
#define MSR_HASWELL_E_DRAM_ENERGY_STATUS   0x00000619
 
#define MSR_HASWELL_E_DRAM_PERF_STATUS   0x0000061B
 
#define MSR_HASWELL_E_DRAM_POWER_INFO   0x0000061C
 
#define MSR_HASWELL_E_PCIE_PLL_RATIO   0x0000061E
 
#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT   0x00000620
 
#define MSR_HASWELL_E_PP0_ENERGY_STATUS   0x00000639
 
#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS   0x00000690
 
#define MSR_HASWELL_E_IA32_QM_EVTSEL   0x00000C8D
 
#define MSR_HASWELL_E_IA32_PQR_ASSOC   0x00000C8F
 
#define MSR_HASWELL_E_PMON_GLOBAL_CTL   0x00000700
 
#define MSR_HASWELL_E_PMON_GLOBAL_STATUS   0x00000701
 
#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG   0x00000702
 
#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL   0x00000703
 
#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR   0x00000704
 
#define MSR_HASWELL_E_U_PMON_EVNTSEL0   0x00000705
 
#define MSR_HASWELL_E_U_PMON_EVNTSEL1   0x00000706
 
#define MSR_HASWELL_E_U_PMON_BOX_STATUS   0x00000708
 
#define MSR_HASWELL_E_U_PMON_CTR0   0x00000709
 
#define MSR_HASWELL_E_U_PMON_CTR1   0x0000070A
 
#define MSR_HASWELL_E_PCU_PMON_BOX_CTL   0x00000710
 
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0   0x00000711
 
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1   0x00000712
 
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2   0x00000713
 
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3   0x00000714
 
#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER   0x00000715
 
#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS   0x00000716
 
#define MSR_HASWELL_E_PCU_PMON_CTR0   0x00000717
 
#define MSR_HASWELL_E_PCU_PMON_CTR1   0x00000718
 
#define MSR_HASWELL_E_PCU_PMON_CTR2   0x00000719
 
#define MSR_HASWELL_E_PCU_PMON_CTR3   0x0000071A
 
#define MSR_HASWELL_E_S0_PMON_BOX_CTL   0x00000720
 
#define MSR_HASWELL_E_S0_PMON_EVNTSEL0   0x00000721
 
#define MSR_HASWELL_E_S0_PMON_EVNTSEL1   0x00000722
 
#define MSR_HASWELL_E_S0_PMON_EVNTSEL2   0x00000723
 
#define MSR_HASWELL_E_S0_PMON_EVNTSEL3   0x00000724
 
#define MSR_HASWELL_E_S0_PMON_BOX_FILTER   0x00000725
 
#define MSR_HASWELL_E_S0_PMON_CTR0   0x00000726
 
#define MSR_HASWELL_E_S0_PMON_CTR1   0x00000727
 
#define MSR_HASWELL_E_S0_PMON_CTR2   0x00000728
 
#define MSR_HASWELL_E_S0_PMON_CTR3   0x00000729
 
#define MSR_HASWELL_E_S1_PMON_BOX_CTL   0x0000072A
 
#define MSR_HASWELL_E_S1_PMON_EVNTSEL0   0x0000072B
 
#define MSR_HASWELL_E_S1_PMON_EVNTSEL1   0x0000072C
 
#define MSR_HASWELL_E_S1_PMON_EVNTSEL2   0x0000072D
 
#define MSR_HASWELL_E_S1_PMON_EVNTSEL3   0x0000072E
 
#define MSR_HASWELL_E_S1_PMON_BOX_FILTER   0x0000072F
 
#define MSR_HASWELL_E_S1_PMON_CTR0   0x00000730
 
#define MSR_HASWELL_E_S1_PMON_CTR1   0x00000731
 
#define MSR_HASWELL_E_S1_PMON_CTR2   0x00000732
 
#define MSR_HASWELL_E_S1_PMON_CTR3   0x00000733
 
#define MSR_HASWELL_E_S2_PMON_BOX_CTL   0x00000734
 
#define MSR_HASWELL_E_S2_PMON_EVNTSEL0   0x00000735
 
#define MSR_HASWELL_E_S2_PMON_EVNTSEL1   0x00000736
 
#define MSR_HASWELL_E_S2_PMON_EVNTSEL2   0x00000737
 
#define MSR_HASWELL_E_S2_PMON_EVNTSEL3   0x00000738
 
#define MSR_HASWELL_E_S2_PMON_BOX_FILTER   0x00000739
 
#define MSR_HASWELL_E_S2_PMON_CTR0   0x0000073A
 
#define MSR_HASWELL_E_S2_PMON_CTR1   0x0000073B
 
#define MSR_HASWELL_E_S2_PMON_CTR2   0x0000073C
 
#define MSR_HASWELL_E_S2_PMON_CTR3   0x0000073D
 
#define MSR_HASWELL_E_S3_PMON_BOX_CTL   0x0000073E
 
#define MSR_HASWELL_E_S3_PMON_EVNTSEL0   0x0000073F
 
#define MSR_HASWELL_E_S3_PMON_EVNTSEL1   0x00000740
 
#define MSR_HASWELL_E_S3_PMON_EVNTSEL2   0x00000741
 
#define MSR_HASWELL_E_S3_PMON_EVNTSEL3   0x00000742
 
#define MSR_HASWELL_E_S3_PMON_BOX_FILTER   0x00000743
 
#define MSR_HASWELL_E_S3_PMON_CTR0   0x00000744
 
#define MSR_HASWELL_E_S3_PMON_CTR1   0x00000745
 
#define MSR_HASWELL_E_S3_PMON_CTR2   0x00000746
 
#define MSR_HASWELL_E_S3_PMON_CTR3   0x00000747
 
#define MSR_HASWELL_E_C0_PMON_BOX_CTL   0x00000E00
 
#define MSR_HASWELL_E_C0_PMON_EVNTSEL0   0x00000E01
 
#define MSR_HASWELL_E_C0_PMON_EVNTSEL1   0x00000E02
 
#define MSR_HASWELL_E_C0_PMON_EVNTSEL2   0x00000E03
 
#define MSR_HASWELL_E_C0_PMON_EVNTSEL3   0x00000E04
 
#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0   0x00000E05
 
#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1   0x00000E06
 
#define MSR_HASWELL_E_C0_PMON_BOX_STATUS   0x00000E07
 
#define MSR_HASWELL_E_C0_PMON_CTR0   0x00000E08
 
#define MSR_HASWELL_E_C0_PMON_CTR1   0x00000E09
 
#define MSR_HASWELL_E_C0_PMON_CTR2   0x00000E0A
 
#define MSR_HASWELL_E_C0_PMON_CTR3   0x00000E0B
 
#define MSR_HASWELL_E_C1_PMON_BOX_CTL   0x00000E10
 
#define MSR_HASWELL_E_C1_PMON_EVNTSEL0   0x00000E11
 
#define MSR_HASWELL_E_C1_PMON_EVNTSEL1   0x00000E12
 
#define MSR_HASWELL_E_C1_PMON_EVNTSEL2   0x00000E13
 
#define MSR_HASWELL_E_C1_PMON_EVNTSEL3   0x00000E14
 
#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0   0x00000E15
 
#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1   0x00000E16
 
#define MSR_HASWELL_E_C1_PMON_BOX_STATUS   0x00000E17
 
#define MSR_HASWELL_E_C1_PMON_CTR0   0x00000E18
 
#define MSR_HASWELL_E_C1_PMON_CTR1   0x00000E19
 
#define MSR_HASWELL_E_C1_PMON_CTR2   0x00000E1A
 
#define MSR_HASWELL_E_C1_PMON_CTR3   0x00000E1B
 
#define MSR_HASWELL_E_C2_PMON_BOX_CTL   0x00000E20
 
#define MSR_HASWELL_E_C2_PMON_EVNTSEL0   0x00000E21
 
#define MSR_HASWELL_E_C2_PMON_EVNTSEL1   0x00000E22
 
#define MSR_HASWELL_E_C2_PMON_EVNTSEL2   0x00000E23
 
#define MSR_HASWELL_E_C2_PMON_EVNTSEL3   0x00000E24
 
#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0   0x00000E25
 
#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1   0x00000E26
 
#define MSR_HASWELL_E_C2_PMON_BOX_STATUS   0x00000E27
 
#define MSR_HASWELL_E_C2_PMON_CTR0   0x00000E28
 
#define MSR_HASWELL_E_C2_PMON_CTR1   0x00000E29
 
#define MSR_HASWELL_E_C2_PMON_CTR2   0x00000E2A
 
#define MSR_HASWELL_E_C2_PMON_CTR3   0x00000E2B
 
#define MSR_HASWELL_E_C3_PMON_BOX_CTL   0x00000E30
 
#define MSR_HASWELL_E_C3_PMON_EVNTSEL0   0x00000E31
 
#define MSR_HASWELL_E_C3_PMON_EVNTSEL1   0x00000E32
 
#define MSR_HASWELL_E_C3_PMON_EVNTSEL2   0x00000E33
 
#define MSR_HASWELL_E_C3_PMON_EVNTSEL3   0x00000E34
 
#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0   0x00000E35
 
#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1   0x00000E36
 
#define MSR_HASWELL_E_C3_PMON_BOX_STATUS   0x00000E37
 
#define MSR_HASWELL_E_C3_PMON_CTR0   0x00000E38
 
#define MSR_HASWELL_E_C3_PMON_CTR1   0x00000E39
 
#define MSR_HASWELL_E_C3_PMON_CTR2   0x00000E3A
 
#define MSR_HASWELL_E_C3_PMON_CTR3   0x00000E3B
 
#define MSR_HASWELL_E_C4_PMON_BOX_CTL   0x00000E40
 
#define MSR_HASWELL_E_C4_PMON_EVNTSEL0   0x00000E41
 
#define MSR_HASWELL_E_C4_PMON_EVNTSEL1   0x00000E42
 
#define MSR_HASWELL_E_C4_PMON_EVNTSEL2   0x00000E43
 
#define MSR_HASWELL_E_C4_PMON_EVNTSEL3   0x00000E44
 
#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0   0x00000E45
 
#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1   0x00000E46
 
#define MSR_HASWELL_E_C4_PMON_BOX_STATUS   0x00000E47
 
#define MSR_HASWELL_E_C4_PMON_CTR0   0x00000E48
 
#define MSR_HASWELL_E_C4_PMON_CTR1   0x00000E49
 
#define MSR_HASWELL_E_C4_PMON_CTR2   0x00000E4A
 
#define MSR_HASWELL_E_C4_PMON_CTR3   0x00000E4B
 
#define MSR_HASWELL_E_C5_PMON_BOX_CTL   0x00000E50
 
#define MSR_HASWELL_E_C5_PMON_EVNTSEL0   0x00000E51
 
#define MSR_HASWELL_E_C5_PMON_EVNTSEL1   0x00000E52
 
#define MSR_HASWELL_E_C5_PMON_EVNTSEL2   0x00000E53
 
#define MSR_HASWELL_E_C5_PMON_EVNTSEL3   0x00000E54
 
#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0   0x00000E55
 
#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1   0x00000E56
 
#define MSR_HASWELL_E_C5_PMON_BOX_STATUS   0x00000E57
 
#define MSR_HASWELL_E_C5_PMON_CTR0   0x00000E58
 
#define MSR_HASWELL_E_C5_PMON_CTR1   0x00000E59
 
#define MSR_HASWELL_E_C5_PMON_CTR2   0x00000E5A
 
#define MSR_HASWELL_E_C5_PMON_CTR3   0x00000E5B
 
#define MSR_HASWELL_E_C6_PMON_BOX_CTL   0x00000E60
 
#define MSR_HASWELL_E_C6_PMON_EVNTSEL0   0x00000E61
 
#define MSR_HASWELL_E_C6_PMON_EVNTSEL1   0x00000E62
 
#define MSR_HASWELL_E_C6_PMON_EVNTSEL2   0x00000E63
 
#define MSR_HASWELL_E_C6_PMON_EVNTSEL3   0x00000E64
 
#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0   0x00000E65
 
#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1   0x00000E66
 
#define MSR_HASWELL_E_C6_PMON_BOX_STATUS   0x00000E67
 
#define MSR_HASWELL_E_C6_PMON_CTR0   0x00000E68
 
#define MSR_HASWELL_E_C6_PMON_CTR1   0x00000E69
 
#define MSR_HASWELL_E_C6_PMON_CTR2   0x00000E6A
 
#define MSR_HASWELL_E_C6_PMON_CTR3   0x00000E6B
 
#define MSR_HASWELL_E_C7_PMON_BOX_CTL   0x00000E70
 
#define MSR_HASWELL_E_C7_PMON_EVNTSEL0   0x00000E71
 
#define MSR_HASWELL_E_C7_PMON_EVNTSEL1   0x00000E72
 
#define MSR_HASWELL_E_C7_PMON_EVNTSEL2   0x00000E73
 
#define MSR_HASWELL_E_C7_PMON_EVNTSEL3   0x00000E74
 
#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0   0x00000E75
 
#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1   0x00000E76
 
#define MSR_HASWELL_E_C7_PMON_BOX_STATUS   0x00000E77
 
#define MSR_HASWELL_E_C7_PMON_CTR0   0x00000E78
 
#define MSR_HASWELL_E_C7_PMON_CTR1   0x00000E79
 
#define MSR_HASWELL_E_C7_PMON_CTR2   0x00000E7A
 
#define MSR_HASWELL_E_C7_PMON_CTR3   0x00000E7B
 
#define MSR_HASWELL_E_C8_PMON_BOX_CTL   0x00000E80
 
#define MSR_HASWELL_E_C8_PMON_EVNTSEL0   0x00000E81
 
#define MSR_HASWELL_E_C8_PMON_EVNTSEL1   0x00000E82
 
#define MSR_HASWELL_E_C8_PMON_EVNTSEL2   0x00000E83
 
#define MSR_HASWELL_E_C8_PMON_EVNTSEL3   0x00000E84
 
#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0   0x00000E85
 
#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1   0x00000E86
 
#define MSR_HASWELL_E_C8_PMON_BOX_STATUS   0x00000E87
 
#define MSR_HASWELL_E_C8_PMON_CTR0   0x00000E88
 
#define MSR_HASWELL_E_C8_PMON_CTR1   0x00000E89
 
#define MSR_HASWELL_E_C8_PMON_CTR2   0x00000E8A
 
#define MSR_HASWELL_E_C8_PMON_CTR3   0x00000E8B
 
#define MSR_HASWELL_E_C9_PMON_BOX_CTL   0x00000E90
 
#define MSR_HASWELL_E_C9_PMON_EVNTSEL0   0x00000E91
 
#define MSR_HASWELL_E_C9_PMON_EVNTSEL1   0x00000E92
 
#define MSR_HASWELL_E_C9_PMON_EVNTSEL2   0x00000E93
 
#define MSR_HASWELL_E_C9_PMON_EVNTSEL3   0x00000E94
 
#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0   0x00000E95
 
#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1   0x00000E96
 
#define MSR_HASWELL_E_C9_PMON_BOX_STATUS   0x00000E97
 
#define MSR_HASWELL_E_C9_PMON_CTR0   0x00000E98
 
#define MSR_HASWELL_E_C9_PMON_CTR1   0x00000E99
 
#define MSR_HASWELL_E_C9_PMON_CTR2   0x00000E9A
 
#define MSR_HASWELL_E_C9_PMON_CTR3   0x00000E9B
 
#define MSR_HASWELL_E_C10_PMON_BOX_CTL   0x00000EA0
 
#define MSR_HASWELL_E_C10_PMON_EVNTSEL0   0x00000EA1
 
#define MSR_HASWELL_E_C10_PMON_EVNTSEL1   0x00000EA2
 
#define MSR_HASWELL_E_C10_PMON_EVNTSEL2   0x00000EA3
 
#define MSR_HASWELL_E_C10_PMON_EVNTSEL3   0x00000EA4
 
#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0   0x00000EA5
 
#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1   0x00000EA6
 
#define MSR_HASWELL_E_C10_PMON_BOX_STATUS   0x00000EA7
 
#define MSR_HASWELL_E_C10_PMON_CTR0   0x00000EA8
 
#define MSR_HASWELL_E_C10_PMON_CTR1   0x00000EA9
 
#define MSR_HASWELL_E_C10_PMON_CTR2   0x00000EAA
 
#define MSR_HASWELL_E_C10_PMON_CTR3   0x00000EAB
 
#define MSR_HASWELL_E_C11_PMON_BOX_CTL   0x00000EB0
 
#define MSR_HASWELL_E_C11_PMON_EVNTSEL0   0x00000EB1
 
#define MSR_HASWELL_E_C11_PMON_EVNTSEL1   0x00000EB2
 
#define MSR_HASWELL_E_C11_PMON_EVNTSEL2   0x00000EB3
 
#define MSR_HASWELL_E_C11_PMON_EVNTSEL3   0x00000EB4
 
#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0   0x00000EB5
 
#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1   0x00000EB6
 
#define MSR_HASWELL_E_C11_PMON_BOX_STATUS   0x00000EB7
 
#define MSR_HASWELL_E_C11_PMON_CTR0   0x00000EB8
 
#define MSR_HASWELL_E_C11_PMON_CTR1   0x00000EB9
 
#define MSR_HASWELL_E_C11_PMON_CTR2   0x00000EBA
 
#define MSR_HASWELL_E_C11_PMON_CTR3   0x00000EBB
 
#define MSR_HASWELL_E_C12_PMON_BOX_CTL   0x00000EC0
 
#define MSR_HASWELL_E_C12_PMON_EVNTSEL0   0x00000EC1
 
#define MSR_HASWELL_E_C12_PMON_EVNTSEL1   0x00000EC2
 
#define MSR_HASWELL_E_C12_PMON_EVNTSEL2   0x00000EC3
 
#define MSR_HASWELL_E_C12_PMON_EVNTSEL3   0x00000EC4
 
#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0   0x00000EC5
 
#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1   0x00000EC6
 
#define MSR_HASWELL_E_C12_PMON_BOX_STATUS   0x00000EC7
 
#define MSR_HASWELL_E_C12_PMON_CTR0   0x00000EC8
 
#define MSR_HASWELL_E_C12_PMON_CTR1   0x00000EC9
 
#define MSR_HASWELL_E_C12_PMON_CTR2   0x00000ECA
 
#define MSR_HASWELL_E_C12_PMON_CTR3   0x00000ECB
 
#define MSR_HASWELL_E_C13_PMON_BOX_CTL   0x00000ED0
 
#define MSR_HASWELL_E_C13_PMON_EVNTSEL0   0x00000ED1
 
#define MSR_HASWELL_E_C13_PMON_EVNTSEL1   0x00000ED2
 
#define MSR_HASWELL_E_C13_PMON_EVNTSEL2   0x00000ED3
 
#define MSR_HASWELL_E_C13_PMON_EVNTSEL3   0x00000ED4
 
#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0   0x00000ED5
 
#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1   0x00000ED6
 
#define MSR_HASWELL_E_C13_PMON_BOX_STATUS   0x00000ED7
 
#define MSR_HASWELL_E_C13_PMON_CTR0   0x00000ED8
 
#define MSR_HASWELL_E_C13_PMON_CTR1   0x00000ED9
 
#define MSR_HASWELL_E_C13_PMON_CTR2   0x00000EDA
 
#define MSR_HASWELL_E_C13_PMON_CTR3   0x00000EDB
 
#define MSR_HASWELL_E_C14_PMON_BOX_CTL   0x00000EE0
 
#define MSR_HASWELL_E_C14_PMON_EVNTSEL0   0x00000EE1
 
#define MSR_HASWELL_E_C14_PMON_EVNTSEL1   0x00000EE2
 
#define MSR_HASWELL_E_C14_PMON_EVNTSEL2   0x00000EE3
 
#define MSR_HASWELL_E_C14_PMON_EVNTSEL3   0x00000EE4
 
#define MSR_HASWELL_E_C14_PMON_BOX_FILTER   0x00000EE5
 
#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1   0x00000EE6
 
#define MSR_HASWELL_E_C14_PMON_BOX_STATUS   0x00000EE7
 
#define MSR_HASWELL_E_C14_PMON_CTR0   0x00000EE8
 
#define MSR_HASWELL_E_C14_PMON_CTR1   0x00000EE9
 
#define MSR_HASWELL_E_C14_PMON_CTR2   0x00000EEA
 
#define MSR_HASWELL_E_C14_PMON_CTR3   0x00000EEB
 
#define MSR_HASWELL_E_C15_PMON_BOX_CTL   0x00000EF0
 
#define MSR_HASWELL_E_C15_PMON_EVNTSEL0   0x00000EF1
 
#define MSR_HASWELL_E_C15_PMON_EVNTSEL1   0x00000EF2
 
#define MSR_HASWELL_E_C15_PMON_EVNTSEL2   0x00000EF3
 
#define MSR_HASWELL_E_C15_PMON_EVNTSEL3   0x00000EF4
 
#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0   0x00000EF5
 
#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1   0x00000EF6
 
#define MSR_HASWELL_E_C15_PMON_BOX_STATUS   0x00000EF7
 
#define MSR_HASWELL_E_C15_PMON_CTR0   0x00000EF8
 
#define MSR_HASWELL_E_C15_PMON_CTR1   0x00000EF9
 
#define MSR_HASWELL_E_C15_PMON_CTR2   0x00000EFA
 
#define MSR_HASWELL_E_C15_PMON_CTR3   0x00000EFB
 
#define MSR_HASWELL_E_C16_PMON_BOX_CTL   0x00000F00
 
#define MSR_HASWELL_E_C16_PMON_EVNTSEL0   0x00000F01
 
#define MSR_HASWELL_E_C16_PMON_EVNTSEL1   0x00000F02
 
#define MSR_HASWELL_E_C16_PMON_EVNTSEL2   0x00000F03
 
#define MSR_HASWELL_E_C16_PMON_EVNTSEL3   0x00000F04
 
#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0   0x00000F05
 
#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1   0x00000F06
 
#define MSR_HASWELL_E_C16_PMON_BOX_STATUS   0x00000F07
 
#define MSR_HASWELL_E_C16_PMON_CTR0   0x00000F08
 
#define MSR_HASWELL_E_C16_PMON_CTR1   0x00000F09
 
#define MSR_HASWELL_E_C16_PMON_CTR2   0x00000F0A
 
#define MSR_HASWELL_E_C16_PMON_CTR3   0x00000E0B
 
#define MSR_HASWELL_E_C17_PMON_BOX_CTL   0x00000F10
 
#define MSR_HASWELL_E_C17_PMON_EVNTSEL0   0x00000F11
 
#define MSR_HASWELL_E_C17_PMON_EVNTSEL1   0x00000F12
 
#define MSR_HASWELL_E_C17_PMON_EVNTSEL2   0x00000F13
 
#define MSR_HASWELL_E_C17_PMON_EVNTSEL3   0x00000F14
 
#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0   0x00000F15
 
#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1   0x00000F16
 
#define MSR_HASWELL_E_C17_PMON_BOX_STATUS   0x00000F17
 
#define MSR_HASWELL_E_C17_PMON_CTR0   0x00000F18
 
#define MSR_HASWELL_E_C17_PMON_CTR1   0x00000F19
 
#define MSR_HASWELL_E_C17_PMON_CTR2   0x00000F1A
 
#define MSR_HASWELL_E_C17_PMON_CTR3   0x00000F1B
 

Detailed Description

MSR Definitions for Intel processors based on the Haswell-E microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file HaswellEMsr.h.

Macro Definition Documentation

◆ IS_HASWELL_E_PROCESSOR

#define IS_HASWELL_E_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3F \
) \
)

Is Intel processors based on the Haswell-E microarchitecture?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.

Definition at line 32 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_BOX_CTL

#define MSR_HASWELL_E_C0_PMON_BOX_CTL   0x00000E00

Package. Uncore C-box 0 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_HASWELL_E_C0_PMON_BOX_CTL
Definition: HaswellEMsr.h:2283
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
Note
MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.

Definition at line 2283 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0   0x00000E05

Package. Uncore C-box 0 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.

Definition at line 2373 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1   0x00000E06

Package. Uncore C-box 0 perfmon box wide filter 1.

Parameters
ECXMSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.

Definition at line 2391 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_BOX_STATUS

#define MSR_HASWELL_E_C0_PMON_BOX_STATUS   0x00000E07

Package. Uncore C-box 0 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.

Definition at line 2409 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_CTR0

#define MSR_HASWELL_E_C0_PMON_CTR0   0x00000E08

Package. Uncore C-box 0 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.

Definition at line 2427 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_CTR1

#define MSR_HASWELL_E_C0_PMON_CTR1   0x00000E09

Package. Uncore C-box 0 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.

Definition at line 2445 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_CTR2

#define MSR_HASWELL_E_C0_PMON_CTR2   0x00000E0A

Package. Uncore C-box 0 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.

Definition at line 2463 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_CTR3

#define MSR_HASWELL_E_C0_PMON_CTR3   0x00000E0B

Package. Uncore C-box 0 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.

Definition at line 2481 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_EVNTSEL0

#define MSR_HASWELL_E_C0_PMON_EVNTSEL0   0x00000E01

Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.

Parameters
ECXMSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.

Definition at line 2301 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_EVNTSEL1

#define MSR_HASWELL_E_C0_PMON_EVNTSEL1   0x00000E02

Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.

Parameters
ECXMSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.

Definition at line 2319 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_EVNTSEL2

#define MSR_HASWELL_E_C0_PMON_EVNTSEL2   0x00000E03

Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.

Parameters
ECXMSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.

Definition at line 2337 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C0_PMON_EVNTSEL3

#define MSR_HASWELL_E_C0_PMON_EVNTSEL3   0x00000E04

Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.

Parameters
ECXMSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.

Definition at line 2355 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_BOX_CTL

#define MSR_HASWELL_E_C10_PMON_BOX_CTL   0x00000EA0

Package. Uncore C-box 10 perfmon local box wide control.

Parameters
ECXMSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.

Definition at line 4443 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0   0x00000EA5

Package. Uncore C-box 10 perfmon box wide filter0.

Parameters
ECXMSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.

Definition at line 4533 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1   0x00000EA6

Package. Uncore C-box 10 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.

Definition at line 4551 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_BOX_STATUS

#define MSR_HASWELL_E_C10_PMON_BOX_STATUS   0x00000EA7

Package. Uncore C-box 10 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.

Definition at line 4569 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_CTR0

#define MSR_HASWELL_E_C10_PMON_CTR0   0x00000EA8

Package. Uncore C-box 10 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.

Definition at line 4587 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_CTR1

#define MSR_HASWELL_E_C10_PMON_CTR1   0x00000EA9

Package. Uncore C-box 10 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.

Definition at line 4605 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_CTR2

#define MSR_HASWELL_E_C10_PMON_CTR2   0x00000EAA

Package. Uncore C-box 10 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.

Definition at line 4623 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_CTR3

#define MSR_HASWELL_E_C10_PMON_CTR3   0x00000EAB

Package. Uncore C-box 10 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.

Definition at line 4641 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_EVNTSEL0

#define MSR_HASWELL_E_C10_PMON_EVNTSEL0   0x00000EA1

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.

Parameters
ECXMSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.

Definition at line 4461 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_EVNTSEL1

#define MSR_HASWELL_E_C10_PMON_EVNTSEL1   0x00000EA2

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.

Parameters
ECXMSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.

Definition at line 4479 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_EVNTSEL2

#define MSR_HASWELL_E_C10_PMON_EVNTSEL2   0x00000EA3

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.

Parameters
ECXMSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.

Definition at line 4497 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C10_PMON_EVNTSEL3

#define MSR_HASWELL_E_C10_PMON_EVNTSEL3   0x00000EA4

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.

Parameters
ECXMSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.

Definition at line 4515 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_BOX_CTL

#define MSR_HASWELL_E_C11_PMON_BOX_CTL   0x00000EB0

Package. Uncore C-box 11 perfmon local box wide control.

Parameters
ECXMSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.

Definition at line 4659 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0   0x00000EB5

Package. Uncore C-box 11 perfmon box wide filter0.

Parameters
ECXMSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.

Definition at line 4749 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1   0x00000EB6

Package. Uncore C-box 11 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.

Definition at line 4767 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_BOX_STATUS

#define MSR_HASWELL_E_C11_PMON_BOX_STATUS   0x00000EB7

Package. Uncore C-box 11 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.

Definition at line 4785 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_CTR0

#define MSR_HASWELL_E_C11_PMON_CTR0   0x00000EB8

Package. Uncore C-box 11 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.

Definition at line 4803 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_CTR1

#define MSR_HASWELL_E_C11_PMON_CTR1   0x00000EB9

Package. Uncore C-box 11 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.

Definition at line 4821 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_CTR2

#define MSR_HASWELL_E_C11_PMON_CTR2   0x00000EBA

Package. Uncore C-box 11 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.

Definition at line 4839 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_CTR3

#define MSR_HASWELL_E_C11_PMON_CTR3   0x00000EBB

Package. Uncore C-box 11 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.

Definition at line 4857 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_EVNTSEL0

#define MSR_HASWELL_E_C11_PMON_EVNTSEL0   0x00000EB1

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.

Parameters
ECXMSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.

Definition at line 4677 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_EVNTSEL1

#define MSR_HASWELL_E_C11_PMON_EVNTSEL1   0x00000EB2

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.

Parameters
ECXMSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.

Definition at line 4695 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_EVNTSEL2

#define MSR_HASWELL_E_C11_PMON_EVNTSEL2   0x00000EB3

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.

Parameters
ECXMSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.

Definition at line 4713 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C11_PMON_EVNTSEL3

#define MSR_HASWELL_E_C11_PMON_EVNTSEL3   0x00000EB4

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.

Parameters
ECXMSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.

Definition at line 4731 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_BOX_CTL

#define MSR_HASWELL_E_C12_PMON_BOX_CTL   0x00000EC0

Package. Uncore C-box 12 perfmon local box wide control.

Parameters
ECXMSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.

Definition at line 4875 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0   0x00000EC5

Package. Uncore C-box 12 perfmon box wide filter0.

Parameters
ECXMSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.

Definition at line 4965 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1   0x00000EC6

Package. Uncore C-box 12 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.

Definition at line 4983 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_BOX_STATUS

#define MSR_HASWELL_E_C12_PMON_BOX_STATUS   0x00000EC7

Package. Uncore C-box 12 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.

Definition at line 5001 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_CTR0

#define MSR_HASWELL_E_C12_PMON_CTR0   0x00000EC8

Package. Uncore C-box 12 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.

Definition at line 5019 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_CTR1

#define MSR_HASWELL_E_C12_PMON_CTR1   0x00000EC9

Package. Uncore C-box 12 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.

Definition at line 5037 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_CTR2

#define MSR_HASWELL_E_C12_PMON_CTR2   0x00000ECA

Package. Uncore C-box 12 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.

Definition at line 5055 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_CTR3

#define MSR_HASWELL_E_C12_PMON_CTR3   0x00000ECB

Package. Uncore C-box 12 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.

Definition at line 5073 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_EVNTSEL0

#define MSR_HASWELL_E_C12_PMON_EVNTSEL0   0x00000EC1

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.

Parameters
ECXMSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.

Definition at line 4893 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_EVNTSEL1

#define MSR_HASWELL_E_C12_PMON_EVNTSEL1   0x00000EC2

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.

Parameters
ECXMSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.

Definition at line 4911 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_EVNTSEL2

#define MSR_HASWELL_E_C12_PMON_EVNTSEL2   0x00000EC3

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.

Parameters
ECXMSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.

Definition at line 4929 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C12_PMON_EVNTSEL3

#define MSR_HASWELL_E_C12_PMON_EVNTSEL3   0x00000EC4

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.

Parameters
ECXMSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.

Definition at line 4947 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_BOX_CTL

#define MSR_HASWELL_E_C13_PMON_BOX_CTL   0x00000ED0

Package. Uncore C-box 13 perfmon local box wide control.

Parameters
ECXMSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.

Definition at line 5091 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0   0x00000ED5

Package. Uncore C-box 13 perfmon box wide filter0.

Parameters
ECXMSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.

Definition at line 5181 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1   0x00000ED6

Package. Uncore C-box 13 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.

Definition at line 5199 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_BOX_STATUS

#define MSR_HASWELL_E_C13_PMON_BOX_STATUS   0x00000ED7

Package. Uncore C-box 13 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.

Definition at line 5217 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_CTR0

#define MSR_HASWELL_E_C13_PMON_CTR0   0x00000ED8

Package. Uncore C-box 13 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.

Definition at line 5235 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_CTR1

#define MSR_HASWELL_E_C13_PMON_CTR1   0x00000ED9

Package. Uncore C-box 13 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.

Definition at line 5253 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_CTR2

#define MSR_HASWELL_E_C13_PMON_CTR2   0x00000EDA

Package. Uncore C-box 13 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.

Definition at line 5271 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_CTR3

#define MSR_HASWELL_E_C13_PMON_CTR3   0x00000EDB

Package. Uncore C-box 13 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.

Definition at line 5289 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_EVNTSEL0

#define MSR_HASWELL_E_C13_PMON_EVNTSEL0   0x00000ED1

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.

Parameters
ECXMSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.

Definition at line 5109 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_EVNTSEL1

#define MSR_HASWELL_E_C13_PMON_EVNTSEL1   0x00000ED2

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.

Parameters
ECXMSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.

Definition at line 5127 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_EVNTSEL2

#define MSR_HASWELL_E_C13_PMON_EVNTSEL2   0x00000ED3

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.

Parameters
ECXMSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.

Definition at line 5145 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C13_PMON_EVNTSEL3

#define MSR_HASWELL_E_C13_PMON_EVNTSEL3   0x00000ED4

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.

Parameters
ECXMSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.

Definition at line 5163 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_BOX_CTL

#define MSR_HASWELL_E_C14_PMON_BOX_CTL   0x00000EE0

Package. Uncore C-box 14 perfmon local box wide control.

Parameters
ECXMSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.

Definition at line 5307 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_BOX_FILTER

#define MSR_HASWELL_E_C14_PMON_BOX_FILTER   0x00000EE5

Package. Uncore C-box 14 perfmon box wide filter0.

Parameters
ECXMSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.

Definition at line 5397 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1   0x00000EE6

Package. Uncore C-box 14 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.

Definition at line 5415 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_BOX_STATUS

#define MSR_HASWELL_E_C14_PMON_BOX_STATUS   0x00000EE7

Package. Uncore C-box 14 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.

Definition at line 5433 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_CTR0

#define MSR_HASWELL_E_C14_PMON_CTR0   0x00000EE8

Package. Uncore C-box 14 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.

Definition at line 5451 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_CTR1

#define MSR_HASWELL_E_C14_PMON_CTR1   0x00000EE9

Package. Uncore C-box 14 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.

Definition at line 5469 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_CTR2

#define MSR_HASWELL_E_C14_PMON_CTR2   0x00000EEA

Package. Uncore C-box 14 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.

Definition at line 5487 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_CTR3

#define MSR_HASWELL_E_C14_PMON_CTR3   0x00000EEB

Package. Uncore C-box 14 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.

Definition at line 5505 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_EVNTSEL0

#define MSR_HASWELL_E_C14_PMON_EVNTSEL0   0x00000EE1

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.

Parameters
ECXMSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.

Definition at line 5325 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_EVNTSEL1

#define MSR_HASWELL_E_C14_PMON_EVNTSEL1   0x00000EE2

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.

Parameters
ECXMSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.

Definition at line 5343 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_EVNTSEL2

#define MSR_HASWELL_E_C14_PMON_EVNTSEL2   0x00000EE3

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.

Parameters
ECXMSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.

Definition at line 5361 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C14_PMON_EVNTSEL3

#define MSR_HASWELL_E_C14_PMON_EVNTSEL3   0x00000EE4

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.

Parameters
ECXMSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.

Definition at line 5379 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_BOX_CTL

#define MSR_HASWELL_E_C15_PMON_BOX_CTL   0x00000EF0

Package. Uncore C-box 15 perfmon local box wide control.

Parameters
ECXMSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.

Definition at line 5523 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0   0x00000EF5

Package. Uncore C-box 15 perfmon box wide filter0.

Parameters
ECXMSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.

Definition at line 5613 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1   0x00000EF6

Package. Uncore C-box 15 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.

Definition at line 5631 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_BOX_STATUS

#define MSR_HASWELL_E_C15_PMON_BOX_STATUS   0x00000EF7

Package. Uncore C-box 15 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.

Definition at line 5649 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_CTR0

#define MSR_HASWELL_E_C15_PMON_CTR0   0x00000EF8

Package. Uncore C-box 15 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.

Definition at line 5667 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_CTR1

#define MSR_HASWELL_E_C15_PMON_CTR1   0x00000EF9

Package. Uncore C-box 15 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.

Definition at line 5685 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_CTR2

#define MSR_HASWELL_E_C15_PMON_CTR2   0x00000EFA

Package. Uncore C-box 15 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.

Definition at line 5703 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_CTR3

#define MSR_HASWELL_E_C15_PMON_CTR3   0x00000EFB

Package. Uncore C-box 15 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.

Definition at line 5721 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_EVNTSEL0

#define MSR_HASWELL_E_C15_PMON_EVNTSEL0   0x00000EF1

Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.

Parameters
ECXMSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.

Definition at line 5541 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_EVNTSEL1

#define MSR_HASWELL_E_C15_PMON_EVNTSEL1   0x00000EF2

Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.

Parameters
ECXMSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.

Definition at line 5559 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_EVNTSEL2

#define MSR_HASWELL_E_C15_PMON_EVNTSEL2   0x00000EF3

Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.

Parameters
ECXMSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.

Definition at line 5577 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C15_PMON_EVNTSEL3

#define MSR_HASWELL_E_C15_PMON_EVNTSEL3   0x00000EF4

Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.

Parameters
ECXMSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.

Definition at line 5595 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_BOX_CTL

#define MSR_HASWELL_E_C16_PMON_BOX_CTL   0x00000F00

Package. Uncore C-box 16 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.

Definition at line 5739 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0   0x00000F05

Package. Uncore C-box 16 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.

Definition at line 5829 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1   0x00000F06

Package. Uncore C-box 16 perfmon box wide filter 1.

Parameters
ECXMSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.

Definition at line 5847 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_BOX_STATUS

#define MSR_HASWELL_E_C16_PMON_BOX_STATUS   0x00000F07

Package. Uncore C-box 16 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.

Definition at line 5865 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_CTR0

#define MSR_HASWELL_E_C16_PMON_CTR0   0x00000F08

Package. Uncore C-box 16 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.

Definition at line 5883 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_CTR1

#define MSR_HASWELL_E_C16_PMON_CTR1   0x00000F09

Package. Uncore C-box 16 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.

Definition at line 5901 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_CTR2

#define MSR_HASWELL_E_C16_PMON_CTR2   0x00000F0A

Package. Uncore C-box 16 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.

Definition at line 5919 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_CTR3

#define MSR_HASWELL_E_C16_PMON_CTR3   0x00000E0B

Package. Uncore C-box 16 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.

Definition at line 5937 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_EVNTSEL0

#define MSR_HASWELL_E_C16_PMON_EVNTSEL0   0x00000F01

Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.

Parameters
ECXMSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.

Definition at line 5757 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_EVNTSEL1

#define MSR_HASWELL_E_C16_PMON_EVNTSEL1   0x00000F02

Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.

Parameters
ECXMSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.

Definition at line 5775 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_EVNTSEL2

#define MSR_HASWELL_E_C16_PMON_EVNTSEL2   0x00000F03

Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.

Parameters
ECXMSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.

Definition at line 5793 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C16_PMON_EVNTSEL3

#define MSR_HASWELL_E_C16_PMON_EVNTSEL3   0x00000F04

Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.

Parameters
ECXMSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.

Definition at line 5811 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_BOX_CTL

#define MSR_HASWELL_E_C17_PMON_BOX_CTL   0x00000F10

Package. Uncore C-box 17 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.

Definition at line 5955 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0   0x00000F15

Package. Uncore C-box 17 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.

Definition at line 6045 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1   0x00000F16

Package. Uncore C-box 17 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.

Definition at line 6063 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_BOX_STATUS

#define MSR_HASWELL_E_C17_PMON_BOX_STATUS   0x00000F17

Package. Uncore C-box 17 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.

Definition at line 6081 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_CTR0

#define MSR_HASWELL_E_C17_PMON_CTR0   0x00000F18

Package. Uncore C-box 17 perfmon counter n.

Parameters
ECXMSR_HASWELL_E_C17_PMON_CTRn
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM. MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM. MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM. MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.

Definition at line 6103 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_CTR1

#define MSR_HASWELL_E_C17_PMON_CTR1   0x00000F19

Definition at line 6104 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_CTR2

#define MSR_HASWELL_E_C17_PMON_CTR2   0x00000F1A

Definition at line 6105 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_CTR3

#define MSR_HASWELL_E_C17_PMON_CTR3   0x00000F1B

Definition at line 6106 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_EVNTSEL0

#define MSR_HASWELL_E_C17_PMON_EVNTSEL0   0x00000F11

Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.

Parameters
ECXMSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.

Definition at line 5973 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_EVNTSEL1

#define MSR_HASWELL_E_C17_PMON_EVNTSEL1   0x00000F12

Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.

Parameters
ECXMSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.

Definition at line 5991 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_EVNTSEL2

#define MSR_HASWELL_E_C17_PMON_EVNTSEL2   0x00000F13

Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.

Parameters
ECXMSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.

Definition at line 6009 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C17_PMON_EVNTSEL3

#define MSR_HASWELL_E_C17_PMON_EVNTSEL3   0x00000F14

Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.

Parameters
ECXMSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.

Definition at line 6027 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_BOX_CTL

#define MSR_HASWELL_E_C1_PMON_BOX_CTL   0x00000E10

Package. Uncore C-box 1 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.

Definition at line 2499 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0   0x00000E15

Package. Uncore C-box 1 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.

Definition at line 2589 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1   0x00000E16

Package. Uncore C-box 1 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.

Definition at line 2607 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_BOX_STATUS

#define MSR_HASWELL_E_C1_PMON_BOX_STATUS   0x00000E17

Package. Uncore C-box 1 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.

Definition at line 2625 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_CTR0

#define MSR_HASWELL_E_C1_PMON_CTR0   0x00000E18

Package. Uncore C-box 1 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.

Definition at line 2643 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_CTR1

#define MSR_HASWELL_E_C1_PMON_CTR1   0x00000E19

Package. Uncore C-box 1 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.

Definition at line 2661 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_CTR2

#define MSR_HASWELL_E_C1_PMON_CTR2   0x00000E1A

Package. Uncore C-box 1 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.

Definition at line 2679 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_CTR3

#define MSR_HASWELL_E_C1_PMON_CTR3   0x00000E1B

Package. Uncore C-box 1 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.

Definition at line 2697 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_EVNTSEL0

#define MSR_HASWELL_E_C1_PMON_EVNTSEL0   0x00000E11

Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.

Parameters
ECXMSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.

Definition at line 2517 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_EVNTSEL1

#define MSR_HASWELL_E_C1_PMON_EVNTSEL1   0x00000E12

Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.

Parameters
ECXMSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.

Definition at line 2535 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_EVNTSEL2

#define MSR_HASWELL_E_C1_PMON_EVNTSEL2   0x00000E13

Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.

Parameters
ECXMSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.

Definition at line 2553 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C1_PMON_EVNTSEL3

#define MSR_HASWELL_E_C1_PMON_EVNTSEL3   0x00000E14

Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.

Parameters
ECXMSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.

Definition at line 2571 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_BOX_CTL

#define MSR_HASWELL_E_C2_PMON_BOX_CTL   0x00000E20

Package. Uncore C-box 2 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.

Definition at line 2715 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0   0x00000E25

Package. Uncore C-box 2 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.

Definition at line 2805 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1   0x00000E26

Package. Uncore C-box 2 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.

Definition at line 2823 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_BOX_STATUS

#define MSR_HASWELL_E_C2_PMON_BOX_STATUS   0x00000E27

Package. Uncore C-box 2 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.

Definition at line 2841 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_CTR0

#define MSR_HASWELL_E_C2_PMON_CTR0   0x00000E28

Package. Uncore C-box 2 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.

Definition at line 2859 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_CTR1

#define MSR_HASWELL_E_C2_PMON_CTR1   0x00000E29

Package. Uncore C-box 2 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.

Definition at line 2877 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_CTR2

#define MSR_HASWELL_E_C2_PMON_CTR2   0x00000E2A

Package. Uncore C-box 2 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.

Definition at line 2895 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_CTR3

#define MSR_HASWELL_E_C2_PMON_CTR3   0x00000E2B

Package. Uncore C-box 2 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.

Definition at line 2913 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_EVNTSEL0

#define MSR_HASWELL_E_C2_PMON_EVNTSEL0   0x00000E21

Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.

Parameters
ECXMSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.

Definition at line 2733 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_EVNTSEL1

#define MSR_HASWELL_E_C2_PMON_EVNTSEL1   0x00000E22

Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.

Parameters
ECXMSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.

Definition at line 2751 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_EVNTSEL2

#define MSR_HASWELL_E_C2_PMON_EVNTSEL2   0x00000E23

Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.

Parameters
ECXMSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.

Definition at line 2769 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C2_PMON_EVNTSEL3

#define MSR_HASWELL_E_C2_PMON_EVNTSEL3   0x00000E24

Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.

Parameters
ECXMSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.

Definition at line 2787 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_BOX_CTL

#define MSR_HASWELL_E_C3_PMON_BOX_CTL   0x00000E30

Package. Uncore C-box 3 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.

Definition at line 2931 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0   0x00000E35

Package. Uncore C-box 3 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.

Definition at line 3021 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1   0x00000E36

Package. Uncore C-box 3 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.

Definition at line 3039 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_BOX_STATUS

#define MSR_HASWELL_E_C3_PMON_BOX_STATUS   0x00000E37

Package. Uncore C-box 3 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.

Definition at line 3057 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_CTR0

#define MSR_HASWELL_E_C3_PMON_CTR0   0x00000E38

Package. Uncore C-box 3 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.

Definition at line 3075 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_CTR1

#define MSR_HASWELL_E_C3_PMON_CTR1   0x00000E39

Package. Uncore C-box 3 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.

Definition at line 3093 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_CTR2

#define MSR_HASWELL_E_C3_PMON_CTR2   0x00000E3A

Package. Uncore C-box 3 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.

Definition at line 3111 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_CTR3

#define MSR_HASWELL_E_C3_PMON_CTR3   0x00000E3B

Package. Uncore C-box 3 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.

Definition at line 3129 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_EVNTSEL0

#define MSR_HASWELL_E_C3_PMON_EVNTSEL0   0x00000E31

Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.

Parameters
ECXMSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.

Definition at line 2949 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_EVNTSEL1

#define MSR_HASWELL_E_C3_PMON_EVNTSEL1   0x00000E32

Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.

Parameters
ECXMSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.

Definition at line 2967 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_EVNTSEL2

#define MSR_HASWELL_E_C3_PMON_EVNTSEL2   0x00000E33

Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.

Parameters
ECXMSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.

Definition at line 2985 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C3_PMON_EVNTSEL3

#define MSR_HASWELL_E_C3_PMON_EVNTSEL3   0x00000E34

Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.

Parameters
ECXMSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.

Definition at line 3003 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_BOX_CTL

#define MSR_HASWELL_E_C4_PMON_BOX_CTL   0x00000E40

Package. Uncore C-box 4 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.

Definition at line 3147 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0   0x00000E45

Package. Uncore C-box 4 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.

Definition at line 3237 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1   0x00000E46

Package. Uncore C-box 4 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.

Definition at line 3255 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_BOX_STATUS

#define MSR_HASWELL_E_C4_PMON_BOX_STATUS   0x00000E47

Package. Uncore C-box 4 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.

Definition at line 3273 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_CTR0

#define MSR_HASWELL_E_C4_PMON_CTR0   0x00000E48

Package. Uncore C-box 4 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.

Definition at line 3291 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_CTR1

#define MSR_HASWELL_E_C4_PMON_CTR1   0x00000E49

Package. Uncore C-box 4 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.

Definition at line 3309 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_CTR2

#define MSR_HASWELL_E_C4_PMON_CTR2   0x00000E4A

Package. Uncore C-box 4 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.

Definition at line 3327 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_CTR3

#define MSR_HASWELL_E_C4_PMON_CTR3   0x00000E4B

Package. Uncore C-box 4 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.

Definition at line 3345 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_EVNTSEL0

#define MSR_HASWELL_E_C4_PMON_EVNTSEL0   0x00000E41

Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.

Parameters
ECXMSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.

Definition at line 3165 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_EVNTSEL1

#define MSR_HASWELL_E_C4_PMON_EVNTSEL1   0x00000E42

Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.

Parameters
ECXMSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.

Definition at line 3183 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_EVNTSEL2

#define MSR_HASWELL_E_C4_PMON_EVNTSEL2   0x00000E43

Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.

Parameters
ECXMSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.

Definition at line 3201 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C4_PMON_EVNTSEL3

#define MSR_HASWELL_E_C4_PMON_EVNTSEL3   0x00000E44

Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.

Parameters
ECXMSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.

Definition at line 3219 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_BOX_CTL

#define MSR_HASWELL_E_C5_PMON_BOX_CTL   0x00000E50

Package. Uncore C-box 5 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.

Definition at line 3363 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0   0x00000E55

Package. Uncore C-box 5 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.

Definition at line 3453 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1   0x00000E56

Package. Uncore C-box 5 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.

Definition at line 3471 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_BOX_STATUS

#define MSR_HASWELL_E_C5_PMON_BOX_STATUS   0x00000E57

Package. Uncore C-box 5 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.

Definition at line 3489 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_CTR0

#define MSR_HASWELL_E_C5_PMON_CTR0   0x00000E58

Package. Uncore C-box 5 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.

Definition at line 3507 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_CTR1

#define MSR_HASWELL_E_C5_PMON_CTR1   0x00000E59

Package. Uncore C-box 5 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.

Definition at line 3525 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_CTR2

#define MSR_HASWELL_E_C5_PMON_CTR2   0x00000E5A

Package. Uncore C-box 5 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.

Definition at line 3543 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_CTR3

#define MSR_HASWELL_E_C5_PMON_CTR3   0x00000E5B

Package. Uncore C-box 5 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.

Definition at line 3561 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_EVNTSEL0

#define MSR_HASWELL_E_C5_PMON_EVNTSEL0   0x00000E51

Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.

Parameters
ECXMSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.

Definition at line 3381 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_EVNTSEL1

#define MSR_HASWELL_E_C5_PMON_EVNTSEL1   0x00000E52

Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.

Parameters
ECXMSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.

Definition at line 3399 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_EVNTSEL2

#define MSR_HASWELL_E_C5_PMON_EVNTSEL2   0x00000E53

Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.

Parameters
ECXMSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.

Definition at line 3417 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C5_PMON_EVNTSEL3

#define MSR_HASWELL_E_C5_PMON_EVNTSEL3   0x00000E54

Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.

Parameters
ECXMSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.

Definition at line 3435 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_BOX_CTL

#define MSR_HASWELL_E_C6_PMON_BOX_CTL   0x00000E60

Package. Uncore C-box 6 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.

Definition at line 3579 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0   0x00000E65

Package. Uncore C-box 6 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.

Definition at line 3669 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1   0x00000E66

Package. Uncore C-box 6 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.

Definition at line 3687 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_BOX_STATUS

#define MSR_HASWELL_E_C6_PMON_BOX_STATUS   0x00000E67

Package. Uncore C-box 6 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.

Definition at line 3705 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_CTR0

#define MSR_HASWELL_E_C6_PMON_CTR0   0x00000E68

Package. Uncore C-box 6 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.

Definition at line 3723 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_CTR1

#define MSR_HASWELL_E_C6_PMON_CTR1   0x00000E69

Package. Uncore C-box 6 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.

Definition at line 3741 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_CTR2

#define MSR_HASWELL_E_C6_PMON_CTR2   0x00000E6A

Package. Uncore C-box 6 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.

Definition at line 3759 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_CTR3

#define MSR_HASWELL_E_C6_PMON_CTR3   0x00000E6B

Package. Uncore C-box 6 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.

Definition at line 3777 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_EVNTSEL0

#define MSR_HASWELL_E_C6_PMON_EVNTSEL0   0x00000E61

Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.

Parameters
ECXMSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.

Definition at line 3597 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_EVNTSEL1

#define MSR_HASWELL_E_C6_PMON_EVNTSEL1   0x00000E62

Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.

Parameters
ECXMSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.

Definition at line 3615 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_EVNTSEL2

#define MSR_HASWELL_E_C6_PMON_EVNTSEL2   0x00000E63

Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.

Parameters
ECXMSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.

Definition at line 3633 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C6_PMON_EVNTSEL3

#define MSR_HASWELL_E_C6_PMON_EVNTSEL3   0x00000E64

Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.

Parameters
ECXMSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.

Definition at line 3651 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_BOX_CTL

#define MSR_HASWELL_E_C7_PMON_BOX_CTL   0x00000E70

Package. Uncore C-box 7 perfmon for box-wide control.

Parameters
ECXMSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.

Definition at line 3795 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0   0x00000E75

Package. Uncore C-box 7 perfmon box wide filter 0.

Parameters
ECXMSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.

Definition at line 3885 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1   0x00000E76

Package. Uncore C-box 7 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.

Definition at line 3903 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_BOX_STATUS

#define MSR_HASWELL_E_C7_PMON_BOX_STATUS   0x00000E77

Package. Uncore C-box 7 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.

Definition at line 3921 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_CTR0

#define MSR_HASWELL_E_C7_PMON_CTR0   0x00000E78

Package. Uncore C-box 7 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.

Definition at line 3939 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_CTR1

#define MSR_HASWELL_E_C7_PMON_CTR1   0x00000E79

Package. Uncore C-box 7 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.

Definition at line 3957 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_CTR2

#define MSR_HASWELL_E_C7_PMON_CTR2   0x00000E7A

Package. Uncore C-box 7 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.

Definition at line 3975 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_CTR3

#define MSR_HASWELL_E_C7_PMON_CTR3   0x00000E7B

Package. Uncore C-box 7 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.

Definition at line 3993 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_EVNTSEL0

#define MSR_HASWELL_E_C7_PMON_EVNTSEL0   0x00000E71

Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.

Parameters
ECXMSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.

Definition at line 3813 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_EVNTSEL1

#define MSR_HASWELL_E_C7_PMON_EVNTSEL1   0x00000E72

Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.

Parameters
ECXMSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.

Definition at line 3831 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_EVNTSEL2

#define MSR_HASWELL_E_C7_PMON_EVNTSEL2   0x00000E73

Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.

Parameters
ECXMSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.

Definition at line 3849 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C7_PMON_EVNTSEL3

#define MSR_HASWELL_E_C7_PMON_EVNTSEL3   0x00000E74

Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.

Parameters
ECXMSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.

Definition at line 3867 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_BOX_CTL

#define MSR_HASWELL_E_C8_PMON_BOX_CTL   0x00000E80

Package. Uncore C-box 8 perfmon local box wide control.

Parameters
ECXMSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.

Definition at line 4011 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0   0x00000E85

Package. Uncore C-box 8 perfmon box wide filter0.

Parameters
ECXMSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.

Definition at line 4101 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1   0x00000E86

Package. Uncore C-box 8 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.

Definition at line 4119 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_BOX_STATUS

#define MSR_HASWELL_E_C8_PMON_BOX_STATUS   0x00000E87

Package. Uncore C-box 8 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.

Definition at line 4137 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_CTR0

#define MSR_HASWELL_E_C8_PMON_CTR0   0x00000E88

Package. Uncore C-box 8 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.

Definition at line 4155 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_CTR1

#define MSR_HASWELL_E_C8_PMON_CTR1   0x00000E89

Package. Uncore C-box 8 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.

Definition at line 4173 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_CTR2

#define MSR_HASWELL_E_C8_PMON_CTR2   0x00000E8A

Package. Uncore C-box 8 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.

Definition at line 4191 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_CTR3

#define MSR_HASWELL_E_C8_PMON_CTR3   0x00000E8B

Package. Uncore C-box 8 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.

Definition at line 4209 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_EVNTSEL0

#define MSR_HASWELL_E_C8_PMON_EVNTSEL0   0x00000E81

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.

Parameters
ECXMSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.

Definition at line 4029 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_EVNTSEL1

#define MSR_HASWELL_E_C8_PMON_EVNTSEL1   0x00000E82

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.

Parameters
ECXMSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.

Definition at line 4047 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_EVNTSEL2

#define MSR_HASWELL_E_C8_PMON_EVNTSEL2   0x00000E83

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.

Parameters
ECXMSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.

Definition at line 4065 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C8_PMON_EVNTSEL3

#define MSR_HASWELL_E_C8_PMON_EVNTSEL3   0x00000E84

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.

Parameters
ECXMSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.

Definition at line 4083 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_BOX_CTL

#define MSR_HASWELL_E_C9_PMON_BOX_CTL   0x00000E90

Package. Uncore C-box 9 perfmon local box wide control.

Parameters
ECXMSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.

Definition at line 4227 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_BOX_FILTER0

#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0   0x00000E95

Package. Uncore C-box 9 perfmon box wide filter0.

Parameters
ECXMSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.

Definition at line 4317 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_BOX_FILTER1

#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1   0x00000E96

Package. Uncore C-box 9 perfmon box wide filter1.

Parameters
ECXMSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.

Definition at line 4335 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_BOX_STATUS

#define MSR_HASWELL_E_C9_PMON_BOX_STATUS   0x00000E97

Package. Uncore C-box 9 perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.

Definition at line 4353 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_CTR0

#define MSR_HASWELL_E_C9_PMON_CTR0   0x00000E98

Package. Uncore C-box 9 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.

Definition at line 4371 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_CTR1

#define MSR_HASWELL_E_C9_PMON_CTR1   0x00000E99

Package. Uncore C-box 9 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.

Definition at line 4389 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_CTR2

#define MSR_HASWELL_E_C9_PMON_CTR2   0x00000E9A

Package. Uncore C-box 9 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.

Definition at line 4407 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_CTR3

#define MSR_HASWELL_E_C9_PMON_CTR3   0x00000E9B

Package. Uncore C-box 9 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.

Definition at line 4425 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_EVNTSEL0

#define MSR_HASWELL_E_C9_PMON_EVNTSEL0   0x00000E91

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.

Parameters
ECXMSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.

Definition at line 4245 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_EVNTSEL1

#define MSR_HASWELL_E_C9_PMON_EVNTSEL1   0x00000E92

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.

Parameters
ECXMSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.

Definition at line 4263 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_EVNTSEL2

#define MSR_HASWELL_E_C9_PMON_EVNTSEL2   0x00000E93

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.

Parameters
ECXMSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.

Definition at line 4281 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_C9_PMON_EVNTSEL3

#define MSR_HASWELL_E_C9_PMON_EVNTSEL3   0x00000E94

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.

Parameters
ECXMSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.

Definition at line 4299 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS

#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS   0x00000690

Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).

Parameters
ECXMSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.

Example usage

Note
MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.

Definition at line 917 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_CORE_THREAD_COUNT

#define MSR_HASWELL_E_CORE_THREAD_COUNT   0x00000035

Package. Configured State of Enabled Processor Core Count and Logical Processor Count (RO) - After a Power-On RESET, enumerates factory configuration of the number of processor cores and logical processors in the physical package. - Following the sequence of (i) BIOS modified a Configuration Mask which selects a subset of processor cores to be active post RESET and (ii) a RESET event after the modification, enumerates the current configuration of enabled processor core count and logical processor count in the physical package.

Parameters
ECXMSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.

Example usage

Note
MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.

Definition at line 63 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_DRAM_ENERGY_STATUS

#define MSR_HASWELL_E_DRAM_ENERGY_STATUS   0x00000619

Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.

Parameters
ECXMSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.

Example usage

Note
MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.

Definition at line 706 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_DRAM_PERF_STATUS

#define MSR_HASWELL_E_DRAM_PERF_STATUS   0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_HASWELL_E_DRAM_PERF_STATUS
Definition: HaswellEMsr.h:749
Note
MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.

Definition at line 749 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_DRAM_POWER_INFO

#define MSR_HASWELL_E_DRAM_POWER_INFO   0x0000061C

Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.

Definition at line 767 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_DRAM_POWER_LIMIT

#define MSR_HASWELL_E_DRAM_POWER_LIMIT   0x00000618

Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.

Definition at line 687 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_ERROR_CONTROL

#define MSR_HASWELL_E_ERROR_CONTROL   0x0000017F

Package. MC Bank Error Configuration (R/W).

Parameters
ECXMSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.

Example usage

Note
MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.

Definition at line 378 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_IA32_MCG_CAP

#define MSR_HASWELL_E_IA32_MCG_CAP   0x00000179

Thread. Global Machine Check Capability (R/O).

Parameters
ECXMSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.

Example usage

Note
MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.

Definition at line 249 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_IA32_PQR_ASSOC

#define MSR_HASWELL_E_IA32_PQR_ASSOC   0x00000C8F

THREAD. Resource Association Register (R/W)..

Parameters
ECXMSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.

Example usage

Note
MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.

Definition at line 1142 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_IA32_QM_EVTSEL

#define MSR_HASWELL_E_IA32_QM_EVTSEL   0x00000C8D

THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.

Parameters
ECXMSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.

Example usage

Note
MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.

Definition at line 1096 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT

#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT   0x00000620

Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.

Parameters
ECXMSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.

Example usage

Definition at line 847 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCIE_PLL_RATIO

#define MSR_HASWELL_E_PCIE_PLL_RATIO   0x0000061E

Package. Configuration of PCIE PLL Relative to BCLK(R/W).

Parameters
ECXMSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.

Example usage

Note
MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.

Definition at line 787 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_BOX_CTL

#define MSR_HASWELL_E_PCU_PMON_BOX_CTL   0x00000710

Package. Uncore PCU perfmon for PCU-box-wide control.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.

Definition at line 1365 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_BOX_FILTER

#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER   0x00000715

Package. Uncore PCU perfmon box-wide filter.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.

Definition at line 1455 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_BOX_STATUS

#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS   0x00000716

Package. Uncore PCU perfmon box wide status.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.

Definition at line 1473 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_CTR0

#define MSR_HASWELL_E_PCU_PMON_CTR0   0x00000717

Package. Uncore PCU perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.

Definition at line 1491 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_CTR1

#define MSR_HASWELL_E_PCU_PMON_CTR1   0x00000718

Package. Uncore PCU perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.

Definition at line 1509 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_CTR2

#define MSR_HASWELL_E_PCU_PMON_CTR2   0x00000719

Package. Uncore PCU perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.

Definition at line 1527 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_CTR3

#define MSR_HASWELL_E_PCU_PMON_CTR3   0x0000071A

Package. Uncore PCU perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.

Definition at line 1545 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_EVNTSEL0

#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0   0x00000711

Package. Uncore PCU perfmon event select for PCU counter 0.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.

Definition at line 1383 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_EVNTSEL1

#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1   0x00000712

Package. Uncore PCU perfmon event select for PCU counter 1.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.

Definition at line 1401 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_EVNTSEL2

#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2   0x00000713

Package. Uncore PCU perfmon event select for PCU counter 2.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.

Definition at line 1419 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PCU_PMON_EVNTSEL3

#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3   0x00000714

Package. Uncore PCU perfmon event select for PCU counter 3.

Parameters
ECXMSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.

Definition at line 1437 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL

#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL   0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. <http://biosbits.org>__.

Parameters
ECXMSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

Note
MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

Definition at line 164 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PMON_GLOBAL_CONFIG

#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG   0x00000702

Package. Uncore perfmon per-socket global configuration.

Parameters
ECXMSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.

Definition at line 1221 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PMON_GLOBAL_CTL

#define MSR_HASWELL_E_PMON_GLOBAL_CTL   0x00000700

Package. Uncore perfmon per-socket global control.

Parameters
ECXMSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.

Definition at line 1185 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PMON_GLOBAL_STATUS

#define MSR_HASWELL_E_PMON_GLOBAL_STATUS   0x00000701

Package. Uncore perfmon per-socket global status.

Parameters
ECXMSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.

Definition at line 1203 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_PP0_ENERGY_STATUS

#define MSR_HASWELL_E_PP0_ENERGY_STATUS   0x00000639

Package. Reserved (R/O) Reads return 0.

Parameters
ECXMSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_HASWELL_E_PP0_ENERGY_STATUS
Definition: HaswellEMsr.h:896
Note
MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

Definition at line 896 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_RAPL_POWER_UNIT

#define MSR_HASWELL_E_RAPL_POWER_UNIT   0x00000606

Package. Unit Multipliers used in RAPL Interfaces (R/O).

Parameters
ECXMSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.

Example usage

Note
MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.

Definition at line 629 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_BOX_CTL

#define MSR_HASWELL_E_S0_PMON_BOX_CTL   0x00000720

Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.

Parameters
ECXMSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.

Definition at line 1563 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_BOX_FILTER

#define MSR_HASWELL_E_S0_PMON_BOX_FILTER   0x00000725

Package. Uncore SBo 0 perfmon box-wide filter.

Parameters
ECXMSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.

Definition at line 1653 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_CTR0

#define MSR_HASWELL_E_S0_PMON_CTR0   0x00000726

Package. Uncore SBo 0 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.

Definition at line 1671 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_CTR1

#define MSR_HASWELL_E_S0_PMON_CTR1   0x00000727

Package. Uncore SBo 0 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.

Definition at line 1689 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_CTR2

#define MSR_HASWELL_E_S0_PMON_CTR2   0x00000728

Package. Uncore SBo 0 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.

Definition at line 1707 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_CTR3

#define MSR_HASWELL_E_S0_PMON_CTR3   0x00000729

Package. Uncore SBo 0 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.

Definition at line 1725 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_EVNTSEL0

#define MSR_HASWELL_E_S0_PMON_EVNTSEL0   0x00000721

Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.

Parameters
ECXMSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.

Definition at line 1581 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_EVNTSEL1

#define MSR_HASWELL_E_S0_PMON_EVNTSEL1   0x00000722

Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.

Parameters
ECXMSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.

Definition at line 1599 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_EVNTSEL2

#define MSR_HASWELL_E_S0_PMON_EVNTSEL2   0x00000723

Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.

Parameters
ECXMSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.

Definition at line 1617 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S0_PMON_EVNTSEL3

#define MSR_HASWELL_E_S0_PMON_EVNTSEL3   0x00000724

Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.

Parameters
ECXMSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.

Definition at line 1635 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_BOX_CTL

#define MSR_HASWELL_E_S1_PMON_BOX_CTL   0x0000072A

Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.

Parameters
ECXMSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.

Definition at line 1743 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_BOX_FILTER

#define MSR_HASWELL_E_S1_PMON_BOX_FILTER   0x0000072F

Package. Uncore SBo 1 perfmon box-wide filter.

Parameters
ECXMSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.

Definition at line 1833 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_CTR0

#define MSR_HASWELL_E_S1_PMON_CTR0   0x00000730

Package. Uncore SBo 1 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.

Definition at line 1851 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_CTR1

#define MSR_HASWELL_E_S1_PMON_CTR1   0x00000731

Package. Uncore SBo 1 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.

Definition at line 1869 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_CTR2

#define MSR_HASWELL_E_S1_PMON_CTR2   0x00000732

Package. Uncore SBo 1 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.

Definition at line 1887 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_CTR3

#define MSR_HASWELL_E_S1_PMON_CTR3   0x00000733

Package. Uncore SBo 1 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.

Definition at line 1905 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_EVNTSEL0

#define MSR_HASWELL_E_S1_PMON_EVNTSEL0   0x0000072B

Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.

Parameters
ECXMSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.

Definition at line 1761 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_EVNTSEL1

#define MSR_HASWELL_E_S1_PMON_EVNTSEL1   0x0000072C

Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.

Parameters
ECXMSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.

Definition at line 1779 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_EVNTSEL2

#define MSR_HASWELL_E_S1_PMON_EVNTSEL2   0x0000072D

Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.

Parameters
ECXMSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.

Definition at line 1797 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S1_PMON_EVNTSEL3

#define MSR_HASWELL_E_S1_PMON_EVNTSEL3   0x0000072E

Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.

Parameters
ECXMSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.

Definition at line 1815 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_BOX_CTL

#define MSR_HASWELL_E_S2_PMON_BOX_CTL   0x00000734

Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.

Parameters
ECXMSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.

Definition at line 1923 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_BOX_FILTER

#define MSR_HASWELL_E_S2_PMON_BOX_FILTER   0x00000739

Package. Uncore SBo 2 perfmon box-wide filter.

Parameters
ECXMSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.

Definition at line 2013 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_CTR0

#define MSR_HASWELL_E_S2_PMON_CTR0   0x0000073A

Package. Uncore SBo 2 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.

Definition at line 2031 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_CTR1

#define MSR_HASWELL_E_S2_PMON_CTR1   0x0000073B

Package. Uncore SBo 2 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.

Definition at line 2049 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_CTR2

#define MSR_HASWELL_E_S2_PMON_CTR2   0x0000073C

Package. Uncore SBo 2 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.

Definition at line 2067 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_CTR3

#define MSR_HASWELL_E_S2_PMON_CTR3   0x0000073D

Package. Uncore SBo 2 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.

Definition at line 2085 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_EVNTSEL0

#define MSR_HASWELL_E_S2_PMON_EVNTSEL0   0x00000735

Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.

Parameters
ECXMSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.

Definition at line 1941 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_EVNTSEL1

#define MSR_HASWELL_E_S2_PMON_EVNTSEL1   0x00000736

Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.

Parameters
ECXMSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.

Definition at line 1959 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_EVNTSEL2

#define MSR_HASWELL_E_S2_PMON_EVNTSEL2   0x00000737

Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.

Parameters
ECXMSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.

Definition at line 1977 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S2_PMON_EVNTSEL3

#define MSR_HASWELL_E_S2_PMON_EVNTSEL3   0x00000738

Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.

Parameters
ECXMSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.

Definition at line 1995 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_BOX_CTL

#define MSR_HASWELL_E_S3_PMON_BOX_CTL   0x0000073E

Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.

Parameters
ECXMSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.

Definition at line 2103 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_BOX_FILTER

#define MSR_HASWELL_E_S3_PMON_BOX_FILTER   0x00000743

Package. Uncore SBo 3 perfmon box-wide filter.

Parameters
ECXMSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.

Definition at line 2193 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_CTR0

#define MSR_HASWELL_E_S3_PMON_CTR0   0x00000744

Package. Uncore SBo 3 perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.

Definition at line 2211 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_CTR1

#define MSR_HASWELL_E_S3_PMON_CTR1   0x00000745

Package. Uncore SBo 3 perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.

Definition at line 2229 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_CTR2

#define MSR_HASWELL_E_S3_PMON_CTR2   0x00000746

Package. Uncore SBo 3 perfmon counter 2.

Parameters
ECXMSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.

Definition at line 2247 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_CTR3

#define MSR_HASWELL_E_S3_PMON_CTR3   0x00000747

Package. Uncore SBo 3 perfmon counter 3.

Parameters
ECXMSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.

Definition at line 2265 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_EVNTSEL0

#define MSR_HASWELL_E_S3_PMON_EVNTSEL0   0x0000073F

Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.

Parameters
ECXMSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.

Definition at line 2121 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_EVNTSEL1

#define MSR_HASWELL_E_S3_PMON_EVNTSEL1   0x00000740

Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.

Parameters
ECXMSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.

Definition at line 2139 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_EVNTSEL2

#define MSR_HASWELL_E_S3_PMON_EVNTSEL2   0x00000741

Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.

Parameters
ECXMSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.

Definition at line 2157 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_S3_PMON_EVNTSEL3

#define MSR_HASWELL_E_S3_PMON_EVNTSEL3   0x00000742

Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.

Parameters
ECXMSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.

Definition at line 2175 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_SMM_MCA_CAP

#define MSR_HASWELL_E_SMM_MCA_CAP   0x0000017D

THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters
ECXMSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.

Example usage

Note
MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.

Definition at line 328 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_THREAD_ID_INFO

#define MSR_HASWELL_E_THREAD_ID_INFO   0x00000053

Thread. A Hardware Assigned ID for the Logical Processor (RO).

Parameters
ECXMSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.

Example usage

Note
MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.

Definition at line 114 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_TURBO_RATIO_LIMIT

#define MSR_HASWELL_E_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters
ECXMSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.

Example usage

Note
MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

Definition at line 425 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_TURBO_RATIO_LIMIT1

#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1   0x000001AE

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters
ECXMSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.

Example usage

Note
MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.

Definition at line 500 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_TURBO_RATIO_LIMIT2

#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2   0x000001AF

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters
ECXMSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
EAXLower 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.

Example usage

Note
MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.

Definition at line 575 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_U_PMON_BOX_STATUS

#define MSR_HASWELL_E_U_PMON_BOX_STATUS   0x00000708

Package. Uncore U-box perfmon U-box wide status.

Parameters
ECXMSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.

Definition at line 1311 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_U_PMON_CTR0

#define MSR_HASWELL_E_U_PMON_CTR0   0x00000709

Package. Uncore U-box perfmon counter 0.

Parameters
ECXMSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_HASWELL_E_U_PMON_CTR0
Definition: HaswellEMsr.h:1329
Note
MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.

Definition at line 1329 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_U_PMON_CTR1

#define MSR_HASWELL_E_U_PMON_CTR1   0x0000070A

Package. Uncore U-box perfmon counter 1.

Parameters
ECXMSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_HASWELL_E_U_PMON_CTR1
Definition: HaswellEMsr.h:1347
Note
MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.

Definition at line 1347 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_U_PMON_EVNTSEL0

#define MSR_HASWELL_E_U_PMON_EVNTSEL0   0x00000705

Package. Uncore U-box perfmon event select for U-box counter 0.

Parameters
ECXMSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.

Definition at line 1275 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_U_PMON_EVNTSEL1

#define MSR_HASWELL_E_U_PMON_EVNTSEL1   0x00000706

Package. Uncore U-box perfmon event select for U-box counter 1.

Parameters
ECXMSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.

Definition at line 1293 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL

#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL   0x00000703

Package. Uncore U-box UCLK fixed counter control.

Parameters
ECXMSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.

Definition at line 1239 of file HaswellEMsr.h.

◆ MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR

#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR   0x00000704

Package. Uncore U-box UCLK fixed counter.

Parameters
ECXMSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.

Definition at line 1257 of file HaswellEMsr.h.