TianoCore EDK2 master
GccInlinePriv.c
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1
11#include "BaseLibInternals.h"
13
20VOID
21EFIAPI
23 VOID
24 )
25{
26 __asm__ __volatile__ ("sti"::: "memory");
27}
28
35VOID
36EFIAPI
38 VOID
39 )
40{
41 __asm__ __volatile__ ("cli"::: "memory");
42}
43
58UINT64
59EFIAPI
61 IN UINT32 Index
62 )
63{
64 UINT64 Data;
65 BOOLEAN Flag;
66
67 Flag = FilterBeforeMsrRead (Index, &Data);
68 if (Flag) {
69 __asm__ __volatile__ (
70 "rdmsr"
71 : "=A" (Data) // %0
72 : "c" (Index) // %1
73 );
74 }
75
76 FilterAfterMsrRead (Index, &Data);
77
78 return Data;
79}
80
98UINT64
99EFIAPI
101 IN UINT32 Index,
102 IN UINT64 Value
103 )
104{
105 BOOLEAN Flag;
106
107 Flag = FilterBeforeMsrWrite (Index, &Value);
108 if (Flag) {
109 __asm__ __volatile__ (
110 "wrmsr"
111 :
112 : "c" (Index),
113 "A" (Value)
114 );
115 }
116
117 FilterAfterMsrWrite (Index, &Value);
118
119 return Value;
120}
121
132UINTN
133EFIAPI
135 VOID
136 )
137{
138 UINTN Data;
139
140 __asm__ __volatile__ (
141 "movl %%cr0,%0"
142 : "=a" (Data)
143 );
144
145 return Data;
146}
147
158UINTN
159EFIAPI
161 VOID
162 )
163{
164 UINTN Data;
165
166 __asm__ __volatile__ (
167 "movl %%cr2, %0"
168 : "=r" (Data)
169 );
170
171 return Data;
172}
173
184UINTN
185EFIAPI
187 VOID
188 )
189{
190 UINTN Data;
191
192 __asm__ __volatile__ (
193 "movl %%cr3, %0"
194 : "=r" (Data)
195 );
196
197 return Data;
198}
199
210UINTN
211EFIAPI
213 VOID
214 )
215{
216 UINTN Data;
217
218 __asm__ __volatile__ (
219 "movl %%cr4, %0"
220 : "=a" (Data)
221 );
222
223 return Data;
224}
225
237UINTN
238EFIAPI
240 UINTN Cr0
241 )
242{
243 __asm__ __volatile__ (
244 "movl %0, %%cr0"
245 :
246 : "r" (Cr0)
247 );
248 return Cr0;
249}
250
262UINTN
263EFIAPI
265 UINTN Cr2
266 )
267{
268 __asm__ __volatile__ (
269 "movl %0, %%cr2"
270 :
271 : "r" (Cr2)
272 );
273 return Cr2;
274}
275
287UINTN
288EFIAPI
290 UINTN Cr3
291 )
292{
293 __asm__ __volatile__ (
294 "movl %0, %%cr3"
295 :
296 : "r" (Cr3)
297 );
298 return Cr3;
299}
300
312UINTN
313EFIAPI
315 UINTN Cr4
316 )
317{
318 __asm__ __volatile__ (
319 "movl %0, %%cr4"
320 :
321 : "r" (Cr4)
322 );
323 return Cr4;
324}
325
336UINTN
337EFIAPI
339 VOID
340 )
341{
342 UINTN Data;
343
344 __asm__ __volatile__ (
345 "movl %%dr0, %0"
346 : "=r" (Data)
347 );
348
349 return Data;
350}
351
362UINTN
363EFIAPI
365 VOID
366 )
367{
368 UINTN Data;
369
370 __asm__ __volatile__ (
371 "movl %%dr1, %0"
372 : "=r" (Data)
373 );
374
375 return Data;
376}
377
388UINTN
389EFIAPI
391 VOID
392 )
393{
394 UINTN Data;
395
396 __asm__ __volatile__ (
397 "movl %%dr2, %0"
398 : "=r" (Data)
399 );
400
401 return Data;
402}
403
414UINTN
415EFIAPI
417 VOID
418 )
419{
420 UINTN Data;
421
422 __asm__ __volatile__ (
423 "movl %%dr3, %0"
424 : "=r" (Data)
425 );
426
427 return Data;
428}
429
440UINTN
441EFIAPI
443 VOID
444 )
445{
446 UINTN Data;
447
448 __asm__ __volatile__ (
449 "movl %%dr4, %0"
450 : "=r" (Data)
451 );
452
453 return Data;
454}
455
466UINTN
467EFIAPI
469 VOID
470 )
471{
472 UINTN Data;
473
474 __asm__ __volatile__ (
475 "movl %%dr5, %0"
476 : "=r" (Data)
477 );
478
479 return Data;
480}
481
492UINTN
493EFIAPI
495 VOID
496 )
497{
498 UINTN Data;
499
500 __asm__ __volatile__ (
501 "movl %%dr6, %0"
502 : "=r" (Data)
503 );
504
505 return Data;
506}
507
518UINTN
519EFIAPI
521 VOID
522 )
523{
524 UINTN Data;
525
526 __asm__ __volatile__ (
527 "movl %%dr7, %0"
528 : "=r" (Data)
529 );
530
531 return Data;
532}
533
545UINTN
546EFIAPI
548 UINTN Dr0
549 )
550{
551 __asm__ __volatile__ (
552 "movl %0, %%dr0"
553 :
554 : "r" (Dr0)
555 );
556 return Dr0;
557}
558
570UINTN
571EFIAPI
573 UINTN Dr1
574 )
575{
576 __asm__ __volatile__ (
577 "movl %0, %%dr1"
578 :
579 : "r" (Dr1)
580 );
581 return Dr1;
582}
583
595UINTN
596EFIAPI
598 UINTN Dr2
599 )
600{
601 __asm__ __volatile__ (
602 "movl %0, %%dr2"
603 :
604 : "r" (Dr2)
605 );
606 return Dr2;
607}
608
620UINTN
621EFIAPI
623 UINTN Dr3
624 )
625{
626 __asm__ __volatile__ (
627 "movl %0, %%dr3"
628 :
629 : "r" (Dr3)
630 );
631 return Dr3;
632}
633
645UINTN
646EFIAPI
648 UINTN Dr4
649 )
650{
651 __asm__ __volatile__ (
652 "movl %0, %%dr4"
653 :
654 : "r" (Dr4)
655 );
656 return Dr4;
657}
658
670UINTN
671EFIAPI
673 UINTN Dr5
674 )
675{
676 __asm__ __volatile__ (
677 "movl %0, %%dr5"
678 :
679 : "r" (Dr5)
680 );
681 return Dr5;
682}
683
695UINTN
696EFIAPI
698 UINTN Dr6
699 )
700{
701 __asm__ __volatile__ (
702 "movl %0, %%dr6"
703 :
704 : "r" (Dr6)
705 );
706 return Dr6;
707}
708
720UINTN
721EFIAPI
723 UINTN Dr7
724 )
725{
726 __asm__ __volatile__ (
727 "movl %0, %%dr7"
728 :
729 : "r" (Dr7)
730 );
731 return Dr7;
732}
733
743UINT16
744EFIAPI
746 VOID
747 )
748{
749 UINT16 Data;
750
751 __asm__ __volatile__ (
752 "mov %%cs, %0"
753 :"=a" (Data)
754 );
755
756 return Data;
757}
758
768UINT16
769EFIAPI
771 VOID
772 )
773{
774 UINT16 Data;
775
776 __asm__ __volatile__ (
777 "mov %%ds, %0"
778 :"=a" (Data)
779 );
780
781 return Data;
782}
783
793UINT16
794EFIAPI
796 VOID
797 )
798{
799 UINT16 Data;
800
801 __asm__ __volatile__ (
802 "mov %%es, %0"
803 :"=a" (Data)
804 );
805
806 return Data;
807}
808
818UINT16
819EFIAPI
821 VOID
822 )
823{
824 UINT16 Data;
825
826 __asm__ __volatile__ (
827 "mov %%fs, %0"
828 :"=a" (Data)
829 );
830
831 return Data;
832}
833
843UINT16
844EFIAPI
846 VOID
847 )
848{
849 UINT16 Data;
850
851 __asm__ __volatile__ (
852 "mov %%gs, %0"
853 :"=a" (Data)
854 );
855
856 return Data;
857}
858
868UINT16
869EFIAPI
871 VOID
872 )
873{
874 UINT16 Data;
875
876 __asm__ __volatile__ (
877 "mov %%ss, %0"
878 :"=a" (Data)
879 );
880
881 return Data;
882}
883
893UINT16
894EFIAPI
896 VOID
897 )
898{
899 UINT16 Data;
900
901 __asm__ __volatile__ (
902 "str %0"
903 : "=a" (Data)
904 );
905
906 return Data;
907}
908
918VOID
919EFIAPI
921 OUT IA32_DESCRIPTOR *Gdtr
922 )
923{
924 __asm__ __volatile__ (
925 "sgdt %0"
926 : "=m" (*Gdtr)
927 );
928}
929
939VOID
940EFIAPI
942 IN CONST IA32_DESCRIPTOR *Gdtr
943 )
944{
945 __asm__ __volatile__ (
946 "lgdt %0"
947 :
948 : "m" (*Gdtr)
949 );
950}
951
961VOID
962EFIAPI
964 OUT IA32_DESCRIPTOR *Idtr
965 )
966{
967 __asm__ __volatile__ (
968 "sidt %0"
969 : "=m" (*Idtr)
970 );
971}
972
982VOID
983EFIAPI
985 IN CONST IA32_DESCRIPTOR *Idtr
986 )
987{
988 __asm__ __volatile__ (
989 "lidt %0"
990 :
991 : "m" (*Idtr)
992 );
993}
994
1004UINT16
1005EFIAPI
1007 VOID
1008 )
1009{
1010 UINT16 Data;
1011
1012 __asm__ __volatile__ (
1013 "sldt %0"
1014 : "=g" (Data) // %0
1015 );
1016
1017 return Data;
1018}
1019
1029VOID
1030EFIAPI
1032 IN UINT16 Ldtr
1033 )
1034{
1035 __asm__ __volatile__ (
1036 "lldtw %0"
1037 :
1038 : "g" (Ldtr) // %0
1039 );
1040}
1041
1053UINT64
1054EFIAPI
1056 IN UINT32 Index
1057 )
1058{
1059 UINT64 Data;
1060
1061 __asm__ __volatile__ (
1062 "rdpmc"
1063 : "=A" (Data)
1064 : "c" (Index)
1065 );
1066
1067 return Data;
1068}
1069
1077VOID
1078EFIAPI
1080 VOID
1081 )
1082{
1083 __asm__ __volatile__ ("wbinvd":::"memory");
1084}
1085
1093VOID
1094EFIAPI
1096 VOID
1097 )
1098{
1099 __asm__ __volatile__ ("invd":::"memory");
1100}
1101
1117VOID *
1118EFIAPI
1120 IN VOID *LinearAddress
1121 )
1122{
1123 UINT32 RegEdx;
1124
1125 //
1126 // If the CPU does not support CLFLUSH instruction,
1127 // then promote flush range to flush entire cache.
1128 //
1129 AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);
1130 if ((RegEdx & BIT19) == 0) {
1131 __asm__ __volatile__ ("wbinvd":::"memory");
1132 return LinearAddress;
1133 }
1134
1135 __asm__ __volatile__ (
1136 "clflush (%0)"
1137 : "+a" (LinearAddress)
1138 :
1139 : "memory"
1140 );
1141
1142 return LinearAddress;
1143}
UINT64 UINTN
#define NULL
Definition: Base.h:312
#define CONST
Definition: Base.h:259
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
UINTN EFIAPI AsmWriteDr1(UINTN Dr1)
UINT16 EFIAPI AsmReadTr(VOID)
UINT16 EFIAPI AsmReadLdtr(VOID)
UINTN EFIAPI AsmWriteDr4(UINTN Dr4)
UINTN EFIAPI AsmReadDr1(VOID)
VOID EFIAPI AsmInvd(VOID)
UINTN EFIAPI AsmReadDr0(VOID)
UINT16 EFIAPI AsmReadFs(VOID)
UINTN EFIAPI AsmWriteDr7(UINTN Dr7)
VOID EFIAPI InternalX86ReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI AsmWriteDr3(UINTN Dr3)
UINT16 EFIAPI AsmReadEs(VOID)
UINTN EFIAPI AsmReadCr3(VOID)
VOID EFIAPI InternalX86ReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
UINTN EFIAPI AsmReadDr2(VOID)
UINTN EFIAPI AsmWriteCr2(UINTN Cr2)
VOID EFIAPI EnableInterrupts(VOID)
Definition: GccInlinePriv.c:22
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
VOID EFIAPI DisableInterrupts(VOID)
Definition: GccInlinePriv.c:37
UINTN EFIAPI AsmWriteCr3(UINTN Cr3)
VOID EFIAPI InternalX86WriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
UINTN EFIAPI AsmWriteCr4(UINTN Cr4)
VOID EFIAPI AsmWbinvd(VOID)
UINTN EFIAPI AsmReadCr0(VOID)
UINTN EFIAPI AsmWriteDr2(UINTN Dr2)
UINTN EFIAPI AsmWriteDr0(UINTN Dr0)
UINT16 EFIAPI AsmReadGs(VOID)
UINTN EFIAPI AsmWriteCr0(UINTN Cr0)
VOID *EFIAPI AsmFlushCacheLine(IN VOID *LinearAddress)
UINTN EFIAPI AsmWriteDr5(UINTN Dr5)
UINTN EFIAPI AsmReadCr2(VOID)
UINT16 EFIAPI AsmReadSs(VOID)
UINT16 EFIAPI AsmReadCs(VOID)
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINTN EFIAPI AsmReadDr3(VOID)
VOID EFIAPI AsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmReadCr4(VOID)
VOID EFIAPI InternalX86WriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI AsmReadDr6(VOID)
UINTN EFIAPI AsmWriteDr6(UINTN Dr6)
UINT64 EFIAPI AsmReadPmc(IN UINT32 Index)
UINT16 EFIAPI AsmReadDs(VOID)
UINTN EFIAPI AsmReadDr4(VOID)
UINTN EFIAPI AsmReadDr7(VOID)
UINTN EFIAPI AsmReadDr5(VOID)
UINT32 EFIAPI AsmCpuid(IN UINT32 Index, OUT UINT32 *RegisterEax OPTIONAL, OUT UINT32 *RegisterEbx OPTIONAL, OUT UINT32 *RegisterEcx OPTIONAL, OUT UINT32 *RegisterEdx OPTIONAL)
Definition: CpuId.c:36
VOID EFIAPI FilterAfterMsrWrite(IN UINT32 Index, IN UINT64 *Value)
BOOLEAN EFIAPI FilterBeforeMsrRead(IN UINT32 Index, IN OUT UINT64 *Value)
VOID EFIAPI FilterAfterMsrRead(IN UINT32 Index, IN UINT64 *Value)
BOOLEAN EFIAPI FilterBeforeMsrWrite(IN UINT32 Index, IN UINT64 *Value)