NvmExpressPei.h

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#ifndef _NVM_EXPRESS_PEI_H_
#define _NVM_EXPRESS_PEI_H_
 
#include <PiPei.h>
 
#include <IndustryStandard/Nvme.h>
#include <IndustryStandard/Pci.h>
 
#include <Ppi/NvmExpressHostController.h>
#include <Ppi/BlockIo.h>
#include <Ppi/BlockIo2.h>
#include <Ppi/StorageSecurityCommand.h>
#include <Ppi/NvmExpressPassThru.h>
#include <Ppi/IoMmu.h>
#include <Ppi/EndOfPeiPhase.h>
#include <Ppi/PciDevice.h>
 
#include <Library/DebugLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/IoLib.h>
#include <Library/TimerLib.h>
#include <Library/DevicePathLib.h>
 
//
// Structure forward declarations
//
typedef struct _PEI_NVME_NAMESPACE_INFO           PEI_NVME_NAMESPACE_INFO;
typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA  PEI_NVME_CONTROLLER_PRIVATE_DATA;
 
#define IS_PCI_NVMHCI(_p)  IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SOLID_STATE, PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI)
 
#include "NvmExpressPeiHci.h"
#include "NvmExpressPeiPassThru.h"
#include "NvmExpressPeiBlockIo.h"
#include "NvmExpressPeiStorageSecurity.h"
 
//
// NVME PEI driver implementation related definitions
//
#define NVME_MAX_QUEUES  2                                  // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
#define NVME_ASQ_SIZE    1                                  // Number of admin submission queue entries, which is 0-based
#define NVME_ACQ_SIZE    1                                  // Number of admin completion queue entries, which is 0-based
#define NVME_CSQ_SIZE    63                                 // Number of I/O submission queue entries, which is 0-based
#define NVME_CCQ_SIZE    63                                 // Number of I/O completion queue entries, which is 0-based
#define NVME_PRP_SIZE    (8)                                // Pages of PRP list
 
#define NVME_MEM_MAX_PAGES                                           \
  (                                                                  \
  1 /* ASQ */ +                                                      \
  1 /* ACQ */ +                                                      \
  1 /* SQs */ +                                                      \
  1 /* CQs */ +                                                      \
  NVME_PRP_SIZE)                            /* PRPs */
 
#define NVME_ADMIN_QUEUE      0x00
#define NVME_IO_QUEUE         0x01
#define NVME_GENERIC_TIMEOUT  5000000                           // Generic PassThru command timeout value, in us unit
#define NVME_POLL_INTERVAL    100                               // Poll interval for PassThru command, in us unit
 
//
// Nvme namespace data structure.
//
struct _PEI_NVME_NAMESPACE_INFO {
  UINT32                              NamespaceId;
  UINT64                              NamespaceUuid;
  EFI_PEI_BLOCK_IO2_MEDIA             Media;
 
  PEI_NVME_CONTROLLER_PRIVATE_DATA    *Controller;
};
 
#define NVME_CONTROLLER_NSID  0
 
//
// Unique signature for private data structure.
//
#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('N','V','P','C')
 
//
// Nvme controller private data structure.
//
struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
  UINT32                                 Signature;
  UINTN                                  MmioBase;
  EFI_NVM_EXPRESS_PASS_THRU_MODE         PassThruMode;
  UINTN                                  DevicePathLength;
  EFI_DEVICE_PATH_PROTOCOL               *DevicePath;
 
  EFI_PEI_RECOVERY_BLOCK_IO_PPI          BlkIoPpi;
  EFI_PEI_RECOVERY_BLOCK_IO2_PPI         BlkIo2Ppi;
  EDKII_PEI_STORAGE_SECURITY_CMD_PPI     StorageSecurityPpi;
  EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI    NvmePassThruPpi;
  EFI_PEI_PPI_DESCRIPTOR                 BlkIoPpiList;
  EFI_PEI_PPI_DESCRIPTOR                 BlkIo2PpiList;
  EFI_PEI_PPI_DESCRIPTOR                 StorageSecurityPpiList;
  EFI_PEI_PPI_DESCRIPTOR                 NvmePassThruPpiList;
  EFI_PEI_NOTIFY_DESCRIPTOR              EndOfPeiNotifyList;
 
  //
  // Pointer to identify controller data
  //
  NVME_ADMIN_CONTROLLER_DATA             *ControllerData;
 
  //
  // (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer
  // 1st 4kB boundary is the start of the admin submission queue
  // 2nd 4kB boundary is the start of the admin completion queue
  // 3rd 4kB boundary is the start of I/O submission queue
  // 4th 4kB boundary is the start of I/O completion queue
  // 5th 4kB boundary is the start of PRP list buffers
  //
  VOID                       *Buffer;
  VOID                       *BufferMapping;
 
  //
  // Pointers to 4kB aligned submission & completion queues
  //
  NVME_SQ                    *SqBuffer[NVME_MAX_QUEUES];
  NVME_CQ                    *CqBuffer[NVME_MAX_QUEUES];
 
  //
  // Submission and completion queue indices
  //
  NVME_SQTDBL                SqTdbl[NVME_MAX_QUEUES];
  NVME_CQHDBL                CqHdbl[NVME_MAX_QUEUES];
 
  UINT8                      Pt[NVME_MAX_QUEUES];
  UINT16                     Cid[NVME_MAX_QUEUES];
 
  //
  // Nvme controller capabilities
  //
  NVME_CAP                   Cap;
 
  //
  // Namespaces information on the controller
  //
  UINT32                     ActiveNamespaceNum;
  PEI_NVME_NAMESPACE_INFO    *NamespaceInfo;
};
 
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a)               \
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a)              \
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY(a)    \
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, StorageSecurityPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NVME_PASSTHRU(a)       \
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, NvmePassThruPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a)              \
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 
//
// Internal functions
//
 
EFI_STATUS
IoMmuAllocateBuffer (
  IN UINTN                  Pages,
  OUT VOID                  **HostAddress,
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
  OUT VOID                  **Mapping
  );
 
EFI_STATUS
IoMmuFreeBuffer (
  IN UINTN  Pages,
  IN VOID   *HostAddress,
  IN VOID   *Mapping
  );
 
EFI_STATUS
IoMmuMap (
  IN  EDKII_IOMMU_OPERATION  Operation,
  IN VOID                    *HostAddress,
  IN  OUT UINTN              *NumberOfBytes,
  OUT EFI_PHYSICAL_ADDRESS   *DeviceAddress,
  OUT VOID                   **Mapping
  );
 
EFI_STATUS
IoMmuUnmap (
  IN VOID  *Mapping
  );
 
EFI_STATUS
EFIAPI
NvmePeimEndOfPei (
  IN EFI_PEI_SERVICES           **PeiServices,
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
  IN VOID                       *Ppi
  );
 
EFI_STATUS
GetDevicePathInstanceSize (
  IN  EFI_DEVICE_PATH_PROTOCOL  *DevicePath,
  OUT UINTN                     *InstanceSize,
  OUT BOOLEAN                   *EntireDevicePathEnd
  );
 
EFI_STATUS
NvmeIsHcDevicePathValid (
  IN EFI_DEVICE_PATH_PROTOCOL  *DevicePath,
  IN UINTN                     DevicePathLength
  );
 
EFI_STATUS
NvmeBuildDevicePath (
  IN  PEI_NVME_CONTROLLER_PRIVATE_DATA  *Private,
  IN  UINT32                            NamespaceId,
  IN  UINT64                            NamespaceUuid,
  OUT UINTN                             *DevicePathLength,
  OUT EFI_DEVICE_PATH_PROTOCOL          **DevicePath
  );
 
BOOLEAN
NvmeS3SkipThisController (
  IN  EFI_DEVICE_PATH_PROTOCOL  *HcDevicePath,
  IN  UINTN                     HcDevicePathLength
  );
 
EFI_STATUS
EFIAPI
NvmePciDevicePpiInstallationCallback (
  IN EFI_PEI_SERVICES           **PeiServices,
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
  IN VOID                       *Ppi
  );
 
EFI_STATUS
EFIAPI
NvmeHostControllerPpiInstallationCallback (
  IN EFI_PEI_SERVICES           **PeiServices,
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
  IN VOID                       *Ppi
  );
 
#endif