PL011UartLib.c

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#include <Uefi.h>
 
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
 
#include <Protocol/SerialIo.h>
 
#include "PL011Uart.h"
 
#define FRACTION_PART_SIZE_IN_BITS  6
#define FRACTION_PART_MASK          ((1 << FRACTION_PART_SIZE_IN_BITS) - 1)
 
//
// Per UEFI spec, only these control bits are allowed to be set.
//
STATIC CONST UINT32  mAllowedControlBits =
  EFI_SERIAL_REQUEST_TO_SEND |
  EFI_SERIAL_DATA_TERMINAL_READY |
  EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE |
  EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE |
  EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
 
//
// platform-specific bits that are not supported by this device.
//
STATIC CONST UINT32  mPlatformInvalidControlBits =
  EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
 
RETURN_STATUS
EFIAPI
PL011UartInitializePort (
  IN     UINTN               UartBase,
  IN     UINT32              UartClkInHz,
  IN OUT UINT64              *BaudRate,
  IN OUT UINT32              *ReceiveFifoDepth,
  IN OUT EFI_PARITY_TYPE     *Parity,
  IN OUT UINT8               *DataBits,
  IN OUT EFI_STOP_BITS_TYPE  *StopBits
  )
{
  UINT32  LineControl;
  UINT32  Divisor;
  UINT32  Integer;
  UINT32  Fractional;
  UINT32  HardwareFifoDepth;
  UINT32  UartPid2;
 
  HardwareFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
  if (HardwareFifoDepth == 0) {
    UartPid2          = MmioRead32 (UartBase + UARTPID2);
    HardwareFifoDepth = (PL011_UARTPID2_VER (UartPid2) > PL011_VER_R1P4) ? 32 : 16;
  }
 
  // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept
  // 1 char buffer as the minimum FIFO size. Because everything can be rounded
  // down, there is no maximum FIFO size.
  if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {
    // Enable FIFO
    LineControl       = PL011_UARTLCR_H_FEN;
    *ReceiveFifoDepth = HardwareFifoDepth;
  } else {
    // Disable FIFO
    LineControl = 0;
    // Nothing else to do. 1 byte FIFO is default.
    *ReceiveFifoDepth = 1;
  }
 
  //
  // Parity
  //
  switch (*Parity) {
    case DefaultParity:
      *Parity = NoParity;
    case NoParity:
      // Nothing to do. Parity is disabled by default.
      break;
    case EvenParity:
      LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
      break;
    case OddParity:
      LineControl |= PL011_UARTLCR_H_PEN;
      break;
    case MarkParity:
      LineControl |= (PL011_UARTLCR_H_PEN \
                      | PL011_UARTLCR_H_SPS \
                      | PL011_UARTLCR_H_EPS);
      break;
    case SpaceParity:
      LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
      break;
    default:
      return RETURN_INVALID_PARAMETER;
  }
 
  //
  // Data Bits
  //
  switch (*DataBits) {
    case 0:
      *DataBits = 8;
    case 8:
      LineControl |= PL011_UARTLCR_H_WLEN_8;
      break;
    case 7:
      LineControl |= PL011_UARTLCR_H_WLEN_7;
      break;
    case 6:
      LineControl |= PL011_UARTLCR_H_WLEN_6;
      break;
    case 5:
      LineControl |= PL011_UARTLCR_H_WLEN_5;
      break;
    default:
      return RETURN_INVALID_PARAMETER;
  }
 
  //
  // Stop Bits
  //
  switch (*StopBits) {
    case DefaultStopBits:
      *StopBits = OneStopBit;
    case OneStopBit:
      // Nothing to do. One stop bit is enabled by default.
      break;
    case TwoStopBits:
      LineControl |= PL011_UARTLCR_H_STP2;
      break;
    case OneFiveStopBits:
    // Only 1 or 2 stop bits are supported
    default:
      return RETURN_INVALID_PARAMETER;
  }
 
  // Don't send the LineControl value to the PL011 yet,
  // wait until after the Baud Rate setting.
  // This ensures we do not mess up the UART settings halfway through
  // in the rare case when there is an error with the Baud Rate.
 
  //
  // Baud Rate
  //
 
  // If PL011 Integer value has been defined then always ignore the BAUD rate
  if (FixedPcdGet32 (PL011UartInteger) != 0) {
    Integer    = FixedPcdGet32 (PL011UartInteger);
    Fractional = FixedPcdGet32 (PL011UartFractional);
  } else {
    // If BAUD rate is zero then replace it with the system default value
    if (*BaudRate == 0) {
      *BaudRate = FixedPcdGet32 (PcdSerialBaudRate);
      if (*BaudRate == 0) {
        return RETURN_INVALID_PARAMETER;
      }
    }
 
    if (0 == UartClkInHz) {
      return RETURN_INVALID_PARAMETER;
    }
 
    Divisor    = (UINT32)((UartClkInHz * 4) / *BaudRate);
    Integer    = Divisor >> FRACTION_PART_SIZE_IN_BITS;
    Fractional = Divisor & FRACTION_PART_MASK;
  }
 
  //
  // If PL011 is already initialized, check the current settings
  // and re-initialize only if the settings are different.
  //
  if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&
      (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
      (MmioRead32 (UartBase + UARTIBRD) == Integer) &&
      (MmioRead32 (UartBase + UARTFBRD) == Fractional))
  {
    // Nothing to do - already initialized with correct attributes
    return RETURN_SUCCESS;
  }
 
  // Wait for the end of transmission
  while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0) {
  }
 
  // Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed
  // when the UART is enabled"
  MmioWrite32 (UartBase + UARTCR, 0);
 
  // Set Baud Rate Registers
  MmioWrite32 (UartBase + UARTIBRD, Integer);
  MmioWrite32 (UartBase + UARTFBRD, Fractional);
 
  // No parity, 1 stop, no fifo, 8 data bits
  MmioWrite32 (UartBase + UARTLCR_H, LineControl);
 
  // Clear any pending errors
  MmioWrite32 (UartBase + UARTECR, 0);
 
  // Enable Tx, Rx, and UART overall
  MmioWrite32 (
    UartBase + UARTCR,
    PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN
    );
 
  return RETURN_SUCCESS;
}
 
RETURN_STATUS
EFIAPI
PL011UartSetControl (
  IN UINTN   UartBase,
  IN UINT32  Control
  )
{
  UINT32  Bits;
 
  if ((Control & ~mAllowedControlBits) != 0) {
    return RETURN_UNSUPPORTED;
  }
 
  if ((Control & mPlatformInvalidControlBits) != 0) {
    return RETURN_UNSUPPORTED;
  }
 
  Bits = MmioRead32 (UartBase + UARTCR);
 
  if ((Control & EFI_SERIAL_REQUEST_TO_SEND) != 0) {
    Bits |= PL011_UARTCR_RTS;
  } else {
    Bits &= ~PL011_UARTCR_RTS;
  }
 
  if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) != 0) {
    Bits |= PL011_UARTCR_DTR;
  } else {
    Bits &= ~PL011_UARTCR_DTR;
  }
 
  if ((Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) != 0) {
    Bits |= PL011_UARTCR_LBE;
  } else {
    Bits &= ~PL011_UARTCR_LBE;
  }
 
  if ((Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) != 0) {
    Bits |= (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);
  } else {
    Bits &= ~(PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);
  }
 
  MmioWrite32 (UartBase + UARTCR, Bits);
 
  return RETURN_SUCCESS;
}
 
RETURN_STATUS
EFIAPI
PL011UartGetControl (
  IN UINTN    UartBase,
  OUT UINT32  *Control
  )
{
  UINT32  FlagRegister;
  UINT32  ControlRegister;
 
  FlagRegister    = MmioRead32 (UartBase + UARTFR);
  ControlRegister = MmioRead32 (UartBase + UARTCR);
 
  *Control = 0;
 
  if ((FlagRegister & PL011_UARTFR_CTS) == PL011_UARTFR_CTS) {
    *Control |= EFI_SERIAL_CLEAR_TO_SEND;
  }
 
  if ((FlagRegister & PL011_UARTFR_DSR) == PL011_UARTFR_DSR) {
    *Control |= EFI_SERIAL_DATA_SET_READY;
  }
 
  if ((FlagRegister & PL011_UARTFR_RI) == PL011_UARTFR_RI) {
    *Control |= EFI_SERIAL_RING_INDICATE;
  }
 
  if ((FlagRegister & PL011_UARTFR_DCD) == PL011_UARTFR_DCD) {
    *Control |= EFI_SERIAL_CARRIER_DETECT;
  }
 
  if ((ControlRegister & PL011_UARTCR_RTS) == PL011_UARTCR_RTS) {
    *Control |= EFI_SERIAL_REQUEST_TO_SEND;
  }
 
  if ((ControlRegister & PL011_UARTCR_DTR) == PL011_UARTCR_DTR) {
    *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
  }
 
  if ((FlagRegister & PL011_UARTFR_RXFE) == PL011_UARTFR_RXFE) {
    *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
  }
 
  if ((FlagRegister & PL011_UARTFR_TXFE) == PL011_UARTFR_TXFE) {
    *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
  }
 
  if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
      == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
  {
    *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
  }
 
  if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {
    *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
  }
 
  return RETURN_SUCCESS;
}
 
UINTN
EFIAPI
PL011UartWrite (
  IN  UINTN  UartBase,
  IN UINT8   *Buffer,
  IN UINTN   NumberOfBytes
  )
{
  UINT8 *CONST  Final = &Buffer[NumberOfBytes];
 
  while (Buffer < Final) {
    // Wait until UART able to accept another char
    while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK)) {
    }
 
    MmioWrite8 (UartBase + UARTDR, *Buffer++);
  }
 
  return NumberOfBytes;
}
 
UINTN
EFIAPI
PL011UartRead (
  IN  UINTN  UartBase,
  OUT UINT8  *Buffer,
  IN  UINTN  NumberOfBytes
  )
{
  UINTN  Count;
 
  for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
    while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0) {
    }
 
    *Buffer = MmioRead8 (UartBase + UARTDR);
  }
 
  return NumberOfBytes;
}
 
BOOLEAN
EFIAPI
PL011UartPoll (
  IN  UINTN  UartBase
  )
{
  return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
}