9#ifndef __PL011_UART_LIB_H__
10#define __PL011_UART_LIB_H__
52 IN UINT32 UartClkInHz,
53 IN OUT UINT64 *BaudRate,
54 IN OUT UINT32 *ReceiveFifoDepth,
56 IN OUT UINT8 *DataBits,
RETURN_STATUS EFIAPI PL011UartInitializePort(IN UINTN UartBase, IN UINT32 UartClkInHz, IN OUT UINT64 *BaudRate, IN OUT UINT32 *ReceiveFifoDepth, IN OUT EFI_PARITY_TYPE *Parity, IN OUT UINT8 *DataBits, IN OUT EFI_STOP_BITS_TYPE *StopBits)
RETURN_STATUS EFIAPI PL011UartSetControl(IN UINTN UartBase, IN UINT32 Control)
UINTN EFIAPI PL011UartWrite(IN UINTN UartBase, IN UINT8 *Buffer, IN UINTN NumberOfBytes)
UINTN EFIAPI PL011UartRead(IN UINTN UartBase, OUT UINT8 *Buffer, IN UINTN NumberOfBytes)
BOOLEAN EFIAPI PL011UartPoll(IN UINTN UartBase)
RETURN_STATUS EFIAPI PL011UartGetControl(IN UINTN UartBase, OUT UINT32 *Control)