TianoCore EDK2 master
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PrintHob.c
Go to the documentation of this file.
1
6#include "UefiPayloadEntry.h"
13#include <Library/HobPrintLib.h>
14
15typedef
17(*GUID_HOB_PRINT) (
18 IN UINT8 *HobRaw,
19 IN UINT16 HobLength
20 );
21
22typedef struct {
23 EFI_GUID *Guid;
24 GUID_HOB_PRINT PrintHandler;
25 CHAR8 *GuidName;
27
38 IN UINT8 *HobRaw,
39 IN UINT16 HobLength
40 )
41{
42 UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob;
43
44 AcpiTableHob = (UNIVERSAL_PAYLOAD_ACPI_TABLE *)GET_GUID_HOB_DATA (HobRaw);
45 ASSERT (HobLength >= AcpiTableHob->Header.Length);
46 DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", AcpiTableHob->Header.Revision));
47 DEBUG ((DEBUG_INFO, " Length = 0x%x\n", AcpiTableHob->Header.Length));
48 DEBUG ((DEBUG_INFO, " Rsdp = 0x%p\n", (UINT64)AcpiTableHob->Rsdp));
49 return EFI_SUCCESS;
50}
51
61 IN UINT8 *HobRaw,
62 IN UINT16 HobLength
63 )
64{
66
67 SerialPortInfo = (UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO *)GET_GUID_HOB_DATA (HobRaw);
68 ASSERT (HobLength >= SerialPortInfo->Header.Length);
69 DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", SerialPortInfo->Header.Revision));
70 DEBUG ((DEBUG_INFO, " Length = 0x%x\n", SerialPortInfo->Header.Length));
71 DEBUG ((DEBUG_INFO, " UseMmio = 0x%x\n", SerialPortInfo->UseMmio));
72 DEBUG ((DEBUG_INFO, " RegisterStride = 0x%x\n", SerialPortInfo->RegisterStride));
73 DEBUG ((DEBUG_INFO, " BaudRate = %d\n", SerialPortInfo->BaudRate));
74 DEBUG ((DEBUG_INFO, " RegisterBase = 0x%lx\n", SerialPortInfo->RegisterBase));
75 return EFI_SUCCESS;
76}
77
86 IN UINT8 *HobRaw,
87 IN UINT16 HobLength
88 )
89{
91
92 SmBiosTable = (UNIVERSAL_PAYLOAD_SMBIOS_TABLE *)GET_GUID_HOB_DATA (HobRaw);
93 ASSERT (HobLength >= SmBiosTable->Header.Length);
94 DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", SmBiosTable->Header.Revision));
95 DEBUG ((DEBUG_INFO, " Length = 0x%x\n", SmBiosTable->Header.Length));
96 DEBUG ((DEBUG_INFO, " SmBiosEntryPoint = 0x%lx\n", (UINT64)SmBiosTable->SmBiosEntryPoint));
97 return EFI_SUCCESS;
98}
99
109 IN UINT8 *HobRaw,
110 IN UINT16 HobLength
111 )
112{
114
115 SmBiosTable = (UNIVERSAL_PAYLOAD_SMBIOS_TABLE *)GET_GUID_HOB_DATA (HobRaw);
116 ASSERT (HobLength >= SmBiosTable->Header.Length);
117 DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", SmBiosTable->Header.Revision));
118 DEBUG ((DEBUG_INFO, " Length = 0x%x\n", SmBiosTable->Header.Length));
119 DEBUG ((DEBUG_INFO, " SmBiosEntryPoint = 0x%lx\n", (UINT64)SmBiosTable->SmBiosEntryPoint));
120 return EFI_SUCCESS;
121}
122
132 IN UINT8 *HobRaw,
133 IN UINT16 HobLength
134 )
135{
136 ACPI_BOARD_INFO *AcpBoardInfo;
137
138 AcpBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (HobRaw);
139 ASSERT (HobLength >= sizeof (*AcpBoardInfo));
140 DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", AcpBoardInfo->Revision));
141 DEBUG ((DEBUG_INFO, " Reserved0 = 0x%x\n", AcpBoardInfo->Reserved0));
142 DEBUG ((DEBUG_INFO, " ResetValue = 0x%x\n", AcpBoardInfo->ResetValue));
143 DEBUG ((DEBUG_INFO, " PmEvtBase = 0x%lx\n", AcpBoardInfo->PmEvtBase));
144 DEBUG ((DEBUG_INFO, " PmGpeEnBase = 0x%lx\n", AcpBoardInfo->PmGpeEnBase));
145 DEBUG ((DEBUG_INFO, " PmCtrlRegBase = 0x%lx\n", AcpBoardInfo->PmCtrlRegBase));
146 DEBUG ((DEBUG_INFO, " PmTimerRegBase = 0x%lx\n", AcpBoardInfo->PmTimerRegBase));
147 DEBUG ((DEBUG_INFO, " ResetRegAddress = 0x%lx\n", AcpBoardInfo->ResetRegAddress));
148 DEBUG ((DEBUG_INFO, " PcieBaseAddress = 0x%lx\n", AcpBoardInfo->PcieBaseAddress));
149 DEBUG ((DEBUG_INFO, " PcieBaseSize = 0x%lx\n", AcpBoardInfo->PcieBaseSize));
150 return EFI_SUCCESS;
151}
152
162 IN UINT8 *HobRaw,
163 IN UINT16 HobLength
164 )
165{
167 UINTN Index;
168 UINTN Length;
169
170 Index = 0;
171 PciRootBridges = (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *)GET_GUID_HOB_DATA (HobRaw);
172 Length = sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES) + (PciRootBridges->Count * sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE));
173 ASSERT (HobLength >= Length);
174 DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", PciRootBridges->Header.Revision));
175 DEBUG ((DEBUG_INFO, " Length = 0x%x\n", PciRootBridges->Header.Length));
176 DEBUG ((DEBUG_INFO, " Count = 0x%x\n", PciRootBridges->Count));
177 DEBUG ((DEBUG_INFO, " ResourceAssigned = %a\n", (PciRootBridges->ResourceAssigned ? "True" : "False")));
178
179 while (Index < PciRootBridges->Count) {
180 DEBUG ((DEBUG_INFO, " Root Bridge Index[%d]:\n", Index));
181 DEBUG ((DEBUG_INFO, " Segment = 0x%x\n", PciRootBridges->RootBridge[Index].Segment));
182 DEBUG ((DEBUG_INFO, " Supports = 0x%lx\n", PciRootBridges->RootBridge[Index].Supports));
183 DEBUG ((DEBUG_INFO, " Attributes = 0x%lx\n", PciRootBridges->RootBridge[Index].Attributes));
184 DEBUG ((DEBUG_INFO, " DmaAbove4G = 0x%x\n", PciRootBridges->RootBridge[Index].DmaAbove4G));
185 DEBUG ((DEBUG_INFO, " NoExtendedConfigSpace = 0x%x\n", PciRootBridges->RootBridge[Index].NoExtendedConfigSpace));
186 DEBUG ((DEBUG_INFO, " AllocationAttributes = 0x%lx\n", PciRootBridges->RootBridge[Index].AllocationAttributes));
187 DEBUG ((DEBUG_INFO, " Bus.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].Bus.Base));
188 DEBUG ((DEBUG_INFO, " Bus.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].Bus.Limit));
189 DEBUG ((DEBUG_INFO, " Bus.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].Bus.Translation));
190 DEBUG ((DEBUG_INFO, " Io.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].Io.Base));
191 DEBUG ((DEBUG_INFO, " Io.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].Io.Limit));
192 DEBUG ((DEBUG_INFO, " Io.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].Io.Translation));
193 DEBUG ((DEBUG_INFO, " Mem.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].Mem.Base));
194 DEBUG ((DEBUG_INFO, " Mem.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].Mem.Limit));
195 DEBUG ((DEBUG_INFO, " Mem.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].Mem.Translation));
196 DEBUG ((DEBUG_INFO, " MemAbove4G.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].MemAbove4G.Base));
197 DEBUG ((DEBUG_INFO, " MemAbove4G.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].MemAbove4G.Limit));
198 DEBUG ((DEBUG_INFO, " MemAbove4G.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].MemAbove4G.Translation));
199 DEBUG ((DEBUG_INFO, " PMem.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].PMem.Base));
200 DEBUG ((DEBUG_INFO, " PMem.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].PMem.Limit));
201 DEBUG ((DEBUG_INFO, " PMem.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].PMem.Translation));
202 DEBUG ((DEBUG_INFO, " PMemAbove4G.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].PMemAbove4G.Base));
203 DEBUG ((DEBUG_INFO, " PMemAbove4G.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].PMemAbove4G.Limit));
204 DEBUG ((DEBUG_INFO, " PMemAbove4G.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].PMemAbove4G.Translation));
205 Index += 1;
206 }
207
208 return EFI_SUCCESS;
209}
210
220 IN UINT8 *HobRaw,
221 IN UINT16 HobLength
222 )
223{
225 UINTN Index;
226 UINTN Length;
227
228 Index = 0;
229 ExtraData = (UNIVERSAL_PAYLOAD_EXTRA_DATA *)GET_GUID_HOB_DATA (HobRaw);
230 Length = sizeof (UNIVERSAL_PAYLOAD_EXTRA_DATA) + ExtraData->Count * sizeof (UNIVERSAL_PAYLOAD_EXTRA_DATA_ENTRY);
231 ASSERT (HobLength >= Length);
232 DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", ExtraData->Header.Revision));
233 DEBUG ((DEBUG_INFO, " Length = 0x%x\n", ExtraData->Header.Length));
234 DEBUG ((DEBUG_INFO, " Count = 0x%x\n", ExtraData->Count));
235
236 while (Index < ExtraData->Count) {
237 DEBUG ((DEBUG_INFO, " Id[%d] = %a\n", Index, ExtraData->Entry[Index].Identifier));
238 DEBUG ((DEBUG_INFO, " Base[%d] = 0x%lx\n", Index, ExtraData->Entry[Index].Base));
239 DEBUG ((DEBUG_INFO, " Size[%d] = 0x%lx\n", Index, ExtraData->Entry[Index].Size));
240 Index += 1;
241 }
242
243 return EFI_SUCCESS;
244}
245
255 IN UINT8 *HobRaw,
256 IN UINT16 HobLength
257 )
258{
259 EFI_MEMORY_TYPE_INFORMATION *MemoryTypeInfo;
260
261 MemoryTypeInfo = (EFI_MEMORY_TYPE_INFORMATION *)GET_GUID_HOB_DATA (HobRaw);
262 ASSERT (HobLength >= sizeof (*MemoryTypeInfo));
263 DEBUG ((DEBUG_INFO, " Type = 0x%x\n", MemoryTypeInfo->Type));
264 DEBUG ((DEBUG_INFO, " NumberOfPages = 0x%x\n", MemoryTypeInfo->NumberOfPages));
265 return EFI_SUCCESS;
266}
267
268//
269// Mappint table for dump Guid Hob information.
270// This table can be easily extented.
271//
272GUID_HOB_PRINT_HANDLE GuidHobPrintHandleTable[] = {
273 { &gUniversalPayloadAcpiTableGuid, PrintAcpiGuidHob, "gUniversalPayloadAcpiTableGuid(ACPI table Guid)" },
274 { &gUniversalPayloadSerialPortInfoGuid, PrintSerialGuidHob, "gUniversalPayloadSerialPortInfoGuid(Serial Port Info)" },
275 { &gUniversalPayloadSmbios3TableGuid, PrintSmbios3GuidHob, "gUniversalPayloadSmbios3TableGuid(SmBios Guid)" },
276 { &gUniversalPayloadSmbiosTableGuid, PrintSmbiosTablGuidHob, "gUniversalPayloadSmbiosTableGuid(SmBios Guid)" },
277 { &gUefiAcpiBoardInfoGuid, PrintAcpiBoardInfoGuidHob, "gUefiAcpiBoardInfoGuid(Acpi Guid)" },
278 { &gUniversalPayloadPciRootBridgeInfoGuid, PrintPciRootBridgeInfoGuidHob, "gUniversalPayloadPciRootBridgeInfoGuid(Pci Guid)" },
279 { &gEfiMemoryTypeInformationGuid, PrintMemoryTypeInfoGuidHob, "gEfiMemoryTypeInformationGuid(Memory Type Information Guid)" },
280 { &gUniversalPayloadExtraDataGuid, PrintExtraDataGuidHob, "gUniversalPayloadExtraDataGuid(PayLoad Extra Data Guid)" }
281};
282
292 IN VOID *HobStart,
293 IN UINT16 HobLength
294 )
295{
297 UINTN Index;
298 EFI_STATUS Status;
299
300 Hob.Raw = (UINT8 *)HobStart;
301 ASSERT (HobLength >= sizeof (Hob.Guid));
302
303 for (Index = 0; Index < ARRAY_SIZE (GuidHobPrintHandleTable); Index++) {
304 if (CompareGuid (&Hob.Guid->Name, GuidHobPrintHandleTable[Index].Guid)) {
305 DEBUG ((DEBUG_INFO, " Guid = %a\n", GuidHobPrintHandleTable[Index].GuidName));
306 Status = GuidHobPrintHandleTable[Index].PrintHandler (Hob.Raw, GET_GUID_HOB_DATA_SIZE (Hob.Raw));
307 return Status;
308 }
309 }
310
311 return EFI_UNSUPPORTED;
312}
313
322 IN VOID *HobStart,
323 IN UINT16 HobLength
324 )
325{
326 return EFI_SUCCESS;
327}
328
340 IN VOID *HobStart,
341 IN UINT16 HobLength
342 )
343{
345
346 Hob.Raw = (UINT8 *)HobStart;
347
348 if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
349 return InternalPrintGuidHob (Hob.Raw, HobLength);
350 } else if (Hob.Header->HobType == EFI_HOB_TYPE_MEMORY_POOL) {
351 return InternalPrintMemoryPoolHob (Hob.Raw, HobLength);
352 }
353
354 return EFI_UNSUPPORTED;
355}
356
361VOID
363 IN CONST VOID *HobStart
364 )
365{
367}
UINT64 UINTN
EFI_GUID gUefiAcpiBoardInfoGuid
BOOLEAN EFIAPI CompareGuid(IN CONST GUID *Guid1, IN CONST GUID *Guid2)
Definition: MemLibGuid.c:73
VOID EFIAPI PrintHobList(IN CONST VOID *HobStart, IN HOB_PRINT_HANDLER PrintHandler OPTIONAL)
Definition: HobPrintLib.c:410
#define CONST
Definition: Base.h:259
#define ARRAY_SIZE(Array)
Definition: Base.h:1393
#define IN
Definition: Base.h:279
#define DEBUG(Expression)
Definition: DebugLib.h:434
VOID PrintHob(IN CONST VOID *HobStart)
Definition: PrintHob.c:362
EFI_STATUS PrintExtraDataGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
Definition: PrintHob.c:219
EFI_STATUS PrintAcpiBoardInfoGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
Definition: PrintHob.c:131
EFI_STATUS PrintSerialGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
Definition: PrintHob.c:60
EFI_STATUS PrintSmbios3GuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
Definition: PrintHob.c:85
EFI_STATUS InternalPrintMemoryPoolHob(IN VOID *HobStart, IN UINT16 HobLength)
Definition: PrintHob.c:321
EFI_STATUS PrintSmbiosTablGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
Definition: PrintHob.c:108
EFI_STATUS PrintMemoryTypeInfoGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
Definition: PrintHob.c:254
EFI_STATUS PrintPciRootBridgeInfoGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
Definition: PrintHob.c:161
EFI_STATUS InternalPrintGuidHob(IN VOID *HobStart, IN UINT16 HobLength)
Definition: PrintHob.c:291
EFI_STATUS PrintAcpiGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
Definition: PrintHob.c:37
EFI_STATUS InternalPrintHobs(IN VOID *HobStart, IN UINT16 HobLength)
Definition: PrintHob.c:339
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
#define EFI_SUCCESS
Definition: UefiBaseType.h:112
EFI_GUID Name
Definition: PiHob.h:347
UINT32 NumberOfPages
The pages of this type memory.
UINT32 Type
EFI memory type defined in UEFI specification.
Definition: Base.h:213
UINT32 Segment
Segment number.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus
Bus aperture which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem
MMIO aperture below 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G
Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G
MMIO aperture above 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem
Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io
IO aperture which can be used by the root bridge.