24 GUID_HOB_PRINT PrintHandler;
45 ASSERT (HobLength >= AcpiTableHob->Header.Length);
46 DEBUG ((DEBUG_INFO,
" Revision = 0x%x\n", AcpiTableHob->Header.Revision));
47 DEBUG ((DEBUG_INFO,
" Length = 0x%x\n", AcpiTableHob->Header.Length));
48 DEBUG ((DEBUG_INFO,
" Rsdp = 0x%p\n", (UINT64)AcpiTableHob->Rsdp));
68 ASSERT (HobLength >= SerialPortInfo->Header.Length);
69 DEBUG ((DEBUG_INFO,
" Revision = 0x%x\n", SerialPortInfo->Header.Revision));
70 DEBUG ((DEBUG_INFO,
" Length = 0x%x\n", SerialPortInfo->Header.Length));
71 DEBUG ((DEBUG_INFO,
" UseMmio = 0x%x\n", SerialPortInfo->UseMmio));
72 DEBUG ((DEBUG_INFO,
" RegisterStride = 0x%x\n", SerialPortInfo->RegisterStride));
73 DEBUG ((DEBUG_INFO,
" BaudRate = %d\n", SerialPortInfo->BaudRate));
74 DEBUG ((DEBUG_INFO,
" RegisterBase = 0x%lx\n", SerialPortInfo->RegisterBase));
93 ASSERT (HobLength >= SmBiosTable->Header.Length);
94 DEBUG ((DEBUG_INFO,
" Revision = 0x%x\n", SmBiosTable->Header.Revision));
95 DEBUG ((DEBUG_INFO,
" Length = 0x%x\n", SmBiosTable->Header.Length));
96 DEBUG ((DEBUG_INFO,
" SmBiosEntryPoint = 0x%lx\n", (UINT64)SmBiosTable->SmBiosEntryPoint));
116 ASSERT (HobLength >= SmBiosTable->Header.Length);
117 DEBUG ((DEBUG_INFO,
" Revision = 0x%x\n", SmBiosTable->Header.Revision));
118 DEBUG ((DEBUG_INFO,
" Length = 0x%x\n", SmBiosTable->Header.Length));
119 DEBUG ((DEBUG_INFO,
" SmBiosEntryPoint = 0x%lx\n", (UINT64)SmBiosTable->SmBiosEntryPoint));
139 ASSERT (HobLength >=
sizeof (*AcpBoardInfo));
140 DEBUG ((DEBUG_INFO,
" Revision = 0x%x\n", AcpBoardInfo->Revision));
141 DEBUG ((DEBUG_INFO,
" Reserved0 = 0x%x\n", AcpBoardInfo->Reserved0));
142 DEBUG ((DEBUG_INFO,
" ResetValue = 0x%x\n", AcpBoardInfo->ResetValue));
143 DEBUG ((DEBUG_INFO,
" PmEvtBase = 0x%lx\n", AcpBoardInfo->PmEvtBase));
144 DEBUG ((DEBUG_INFO,
" PmGpeEnBase = 0x%lx\n", AcpBoardInfo->PmGpeEnBase));
145 DEBUG ((DEBUG_INFO,
" PmCtrlRegBase = 0x%lx\n", AcpBoardInfo->PmCtrlRegBase));
146 DEBUG ((DEBUG_INFO,
" PmTimerRegBase = 0x%lx\n", AcpBoardInfo->PmTimerRegBase));
147 DEBUG ((DEBUG_INFO,
" ResetRegAddress = 0x%lx\n", AcpBoardInfo->ResetRegAddress));
148 DEBUG ((DEBUG_INFO,
" PcieBaseAddress = 0x%lx\n", AcpBoardInfo->PcieBaseAddress));
149 DEBUG ((DEBUG_INFO,
" PcieBaseSize = 0x%lx\n", AcpBoardInfo->PcieBaseSize));
173 ASSERT (HobLength >= Length);
174 DEBUG ((DEBUG_INFO,
" Revision = 0x%x\n", PciRootBridges->Header.Revision));
175 DEBUG ((DEBUG_INFO,
" Length = 0x%x\n", PciRootBridges->Header.Length));
176 DEBUG ((DEBUG_INFO,
" Count = 0x%x\n", PciRootBridges->Count));
177 DEBUG ((DEBUG_INFO,
" ResourceAssigned = %a\n", (PciRootBridges->ResourceAssigned ?
"True" :
"False")));
179 while (Index < PciRootBridges->Count) {
180 DEBUG ((DEBUG_INFO,
" Root Bridge Index[%d]:\n", Index));
181 DEBUG ((DEBUG_INFO,
" Segment = 0x%x\n", PciRootBridges->RootBridge[Index].
Segment));
182 DEBUG ((DEBUG_INFO,
" Supports = 0x%lx\n", PciRootBridges->RootBridge[Index].
Supports));
183 DEBUG ((DEBUG_INFO,
" Attributes = 0x%lx\n", PciRootBridges->RootBridge[Index].
Attributes));
184 DEBUG ((DEBUG_INFO,
" DmaAbove4G = 0x%x\n", PciRootBridges->RootBridge[Index].
DmaAbove4G));
187 DEBUG ((DEBUG_INFO,
" Bus.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].
Bus.Base));
188 DEBUG ((DEBUG_INFO,
" Bus.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].
Bus.Limit));
189 DEBUG ((DEBUG_INFO,
" Bus.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].
Bus.Translation));
190 DEBUG ((DEBUG_INFO,
" Io.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].
Io.Base));
191 DEBUG ((DEBUG_INFO,
" Io.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].
Io.Limit));
192 DEBUG ((DEBUG_INFO,
" Io.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].
Io.Translation));
193 DEBUG ((DEBUG_INFO,
" Mem.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].
Mem.Base));
194 DEBUG ((DEBUG_INFO,
" Mem.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].
Mem.Limit));
195 DEBUG ((DEBUG_INFO,
" Mem.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].
Mem.Translation));
196 DEBUG ((DEBUG_INFO,
" MemAbove4G.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].
MemAbove4G.Base));
197 DEBUG ((DEBUG_INFO,
" MemAbove4G.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].
MemAbove4G.Limit));
198 DEBUG ((DEBUG_INFO,
" MemAbove4G.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].
MemAbove4G.Translation));
199 DEBUG ((DEBUG_INFO,
" PMem.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].
PMem.Base));
200 DEBUG ((DEBUG_INFO,
" PMem.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].
PMem.Limit));
201 DEBUG ((DEBUG_INFO,
" PMem.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].
PMem.Translation));
202 DEBUG ((DEBUG_INFO,
" PMemAbove4G.Base = 0x%lx\n", PciRootBridges->RootBridge[Index].
PMemAbove4G.Base));
203 DEBUG ((DEBUG_INFO,
" PMemAbove4G.Limit = 0x%lx\n", PciRootBridges->RootBridge[Index].
PMemAbove4G.Limit));
204 DEBUG ((DEBUG_INFO,
" PMemAbove4G.Translation = 0x%lx\n", PciRootBridges->RootBridge[Index].
PMemAbove4G.Translation));
231 ASSERT (HobLength >= Length);
232 DEBUG ((DEBUG_INFO,
" Revision = 0x%x\n", ExtraData->Header.Revision));
233 DEBUG ((DEBUG_INFO,
" Length = 0x%x\n", ExtraData->Header.Length));
234 DEBUG ((DEBUG_INFO,
" Count = 0x%x\n", ExtraData->Count));
236 while (Index < ExtraData->Count) {
237 DEBUG ((DEBUG_INFO,
" Id[%d] = %a\n", Index, ExtraData->Entry[Index].Identifier));
238 DEBUG ((DEBUG_INFO,
" Base[%d] = 0x%lx\n", Index, ExtraData->Entry[Index].Base));
239 DEBUG ((DEBUG_INFO,
" Size[%d] = 0x%lx\n", Index, ExtraData->Entry[Index].Size));
262 ASSERT (HobLength >=
sizeof (*MemoryTypeInfo));
263 DEBUG ((DEBUG_INFO,
" Type = 0x%x\n", MemoryTypeInfo->
Type));
273 { &gUniversalPayloadAcpiTableGuid,
PrintAcpiGuidHob,
"gUniversalPayloadAcpiTableGuid(ACPI table Guid)" },
274 { &gUniversalPayloadSerialPortInfoGuid,
PrintSerialGuidHob,
"gUniversalPayloadSerialPortInfoGuid(Serial Port Info)" },
275 { &gUniversalPayloadSmbios3TableGuid,
PrintSmbios3GuidHob,
"gUniversalPayloadSmbios3TableGuid(SmBios Guid)" },
276 { &gUniversalPayloadSmbiosTableGuid,
PrintSmbiosTablGuidHob,
"gUniversalPayloadSmbiosTableGuid(SmBios Guid)" },
279 { &gEfiMemoryTypeInformationGuid,
PrintMemoryTypeInfoGuidHob,
"gEfiMemoryTypeInformationGuid(Memory Type Information Guid)" },
280 { &gUniversalPayloadExtraDataGuid,
PrintExtraDataGuidHob,
"gUniversalPayloadExtraDataGuid(PayLoad Extra Data Guid)" }
300 Hob.Raw = (UINT8 *)HobStart;
301 ASSERT (HobLength >=
sizeof (Hob.Guid));
303 for (Index = 0; Index <
ARRAY_SIZE (GuidHobPrintHandleTable); Index++) {
304 if (
CompareGuid (&Hob.Guid->
Name, GuidHobPrintHandleTable[Index].Guid)) {
305 DEBUG ((DEBUG_INFO,
" Guid = %a\n", GuidHobPrintHandleTable[Index].GuidName));
306 Status = GuidHobPrintHandleTable[Index].PrintHandler (Hob.Raw, GET_GUID_HOB_DATA_SIZE (Hob.Raw));
311 return EFI_UNSUPPORTED;
346 Hob.Raw = (UINT8 *)HobStart;
348 if (Hob.Header->
HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
350 }
else if (Hob.Header->
HobType == EFI_HOB_TYPE_MEMORY_POOL) {
354 return EFI_UNSUPPORTED;
EFI_GUID gUefiAcpiBoardInfoGuid
BOOLEAN EFIAPI CompareGuid(IN CONST GUID *Guid1, IN CONST GUID *Guid2)
VOID EFIAPI PrintHobList(IN CONST VOID *HobStart, IN HOB_PRINT_HANDLER PrintHandler OPTIONAL)
#define ARRAY_SIZE(Array)
#define DEBUG(Expression)
VOID PrintHob(IN CONST VOID *HobStart)
EFI_STATUS PrintExtraDataGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
EFI_STATUS PrintAcpiBoardInfoGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
EFI_STATUS PrintSerialGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
EFI_STATUS PrintSmbios3GuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
EFI_STATUS InternalPrintMemoryPoolHob(IN VOID *HobStart, IN UINT16 HobLength)
EFI_STATUS PrintSmbiosTablGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
EFI_STATUS PrintMemoryTypeInfoGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
EFI_STATUS PrintPciRootBridgeInfoGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
EFI_STATUS InternalPrintGuidHob(IN VOID *HobStart, IN UINT16 HobLength)
EFI_STATUS PrintAcpiGuidHob(IN UINT8 *HobRaw, IN UINT16 HobLength)
EFI_STATUS InternalPrintHobs(IN VOID *HobStart, IN UINT16 HobLength)
UINT32 NumberOfPages
The pages of this type memory.
UINT32 Type
EFI memory type defined in UEFI specification.
UINT32 Segment
Segment number.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus
Bus aperture which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem
MMIO aperture below 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G
Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G
MMIO aperture above 4GB which can be used by the root bridge.
UINT64 AllocationAttributes
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem
Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io
IO aperture which can be used by the root bridge.
BOOLEAN NoExtendedConfigSpace