#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>

Macros
#define	RISCV_CACHE_BLOCK_SIZE 64

#define	RISCV_CPU_FEATURE_CMO_BITMASK 0x1

Enumerations
enum	CACHE_OP { CacheOpClean , CacheOpFlush , CacheOpInvld }

Functions
STATIC BOOLEAN	RiscVIsCMOEnabled (VOID)

STATIC VOID	CacheOpCacheRange (IN VOID *Address, IN UINTN Length, IN CACHE_OP Op)

VOID EFIAPI	InvalidateInstructionCache (VOID)

VOID *EFIAPI	InvalidateInstructionCacheRange (IN VOID *Address, IN UINTN Length)

VOID EFIAPI	WriteBackInvalidateDataCache (VOID)

VOID *EFIAPI	WriteBackInvalidateDataCacheRange (IN VOID *Address, IN UINTN Length)

VOID EFIAPI	WriteBackDataCache (VOID)

VOID *EFIAPI	WriteBackDataCacheRange (IN VOID *Address, IN UINTN Length)

VOID EFIAPI	InvalidateDataCache (VOID)

VOID *EFIAPI	InvalidateDataCacheRange (IN VOID *Address, IN UINTN Length)

Detailed Description

RISC-V specific functionality for cache.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file RiscVCache.c.

Macro Definition Documentation

◆ RISCV_CACHE_BLOCK_SIZE

#define RISCV_CACHE_BLOCK_SIZE 64

Definition at line 22 of file RiscVCache.c.

◆ RISCV_CPU_FEATURE_CMO_BITMASK

#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1

Definition at line 23 of file RiscVCache.c.

Enumeration Type Documentation

◆ CACHE_OP

enum CACHE_OP

Definition at line 25 of file RiscVCache.c.

Function Documentation

◆ CacheOpCacheRange()

STATIC VOID CacheOpCacheRange	(	IN VOID *	Address,
		IN UINTN	Length,
		IN CACHE_OP	Op
	)

Performs required opeartion on cache lines in the cache coherency domain of the calling CPU. If Address is not aligned on a cache line boundary, then entire cache line containing Address is operated. If Address + Length is not aligned on a cache line boundary, then the entire cache line containing Address + Length -1 is operated. If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

Parameters

Address	The base address of the cache lines to invalidate.
Length	The number of bytes to invalidate from the instruction cache.
Op	Type of CMO operation to be performed

Returns: Address.

Definition at line 64 of file RiscVCache.c.

◆ InvalidateDataCache()

VOID EFIAPI InvalidateDataCache ( VOID )

Invalidates the entire data cache in cache coherency domain of the calling CPU.

Invalidates the entire data cache in cache coherency domain of the calling CPU. This function must be used with care because dirty cache lines are not written back to system memory. It is typically used for cache diagnostics. If the CPU does not support invalidation of the entire data cache, then a write back and invalidate operation should be performed on the entire data cache.

Definition at line 305 of file RiscVCache.c.

◆ InvalidateDataCacheRange()

VOID *EFIAPI InvalidateDataCacheRange	(	IN VOID *	Address,
		IN UINTN	Length
	)

Invalidates a range of data cache lines in the cache coherency domain of the calling CPU.

Invalidates the data cache lines specified by Address and Length. If Address is not aligned on a cache line boundary, then entire data cache line containing Address is invalidated. If Address + Length is not aligned on a cache line boundary, then the entire data cache line containing Address + Length -1 is invalidated. This function must never invalidate any cache lines outside the specified range. If Length is 0, then no data cache lines are invalidated. Address is returned. This function must be used with care because dirty cache lines are not written back to system memory. It is typically used for cache diagnostics. If the CPU does not support invalidation of a data cache range, then a write back and invalidate operation should be performed on the data cache range.

If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

Parameters

Address	The base address of the data cache lines to invalidate.
Length	The number of bytes to invalidate from the data cache.

Returns: Address.

Definition at line 338 of file RiscVCache.c.

◆ InvalidateInstructionCache()

VOID EFIAPI InvalidateInstructionCache ( VOID )

Invalidates the entire instruction cache in cache coherency domain of the calling CPU. Risc-V does not have currently an CBO implementation which can invalidate the entire I-cache. Hence using Fence instruction for now. P.S. Fence instruction may or may not implement full I-cache invd functionality on all implementations.

Definition at line 127 of file RiscVCache.c.

◆ InvalidateInstructionCacheRange()

VOID *EFIAPI InvalidateInstructionCacheRange	(	IN VOID *	Address,
		IN UINTN	Length
	)

Invalidates a range of instruction cache lines in the cache coherency domain of the calling CPU.

An operation from a CMO instruction is defined to operate only on the copies of a cache block that are cached in the caches accessible by the explicit memory accesses performed by the set of coherent agents.In other words CMO operations are not applicable to instruction cache. Use fence.i instruction instead to achieve the same purpose.

Parameters

Address	The base address of the instruction cache lines to invalidate. If the CPU is in a physical addressing mode, then Address is a physical address. If the CPU is in a virtual addressing mode, then Address is a virtual address.
Length	The number of bytes to invalidate from the instruction cache.

Returns: Address.

Definition at line 155 of file RiscVCache.c.

◆ RiscVIsCMOEnabled()

STATIC BOOLEAN RiscVIsCMOEnabled ( VOID )

Verify CBOs are supported by this HW TODO: Use RISC-V CPU HOB once available.

Definition at line 38 of file RiscVCache.c.

◆ WriteBackDataCache()

VOID EFIAPI WriteBackDataCache ( VOID )

Writes back the entire data cache in cache coherency domain of the calling CPU.

Writes back the entire data cache in cache coherency domain of the calling CPU. This function guarantees that all dirty cache lines are written back to system memory. This function may also invalidate all the data cache lines in the cache coherency domain of the calling CPU.

Definition at line 247 of file RiscVCache.c.

◆ WriteBackDataCacheRange()

VOID *EFIAPI WriteBackDataCacheRange	(	IN VOID *	Address,
		IN UINTN	Length
	)

Writes back a range of data cache lines in the cache coherency domain of the calling CPU.

Writes back the data cache lines specified by Address and Length. If Address is not aligned on a cache line boundary, then entire data cache line containing Address is written back. If Address + Length is not aligned on a cache line boundary, then the entire data cache line containing Address + Length -1 is written back. This function may choose to write back the entire data cache if that is more efficient than writing back the specified range. If Length is 0, then no data cache lines are written back. This function may also invalidate all the data cache lines in the specified range of the cache coherency domain of the calling CPU. Address is returned.

If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

Parameters

Address	The base address of the data cache lines to write back.
Length	The number of bytes to write back from the data cache.

Returns: Address of cache written in main memory.

Definition at line 278 of file RiscVCache.c.

◆ WriteBackInvalidateDataCache()

VOID EFIAPI WriteBackInvalidateDataCache ( VOID )

Writes back and invalidates the entire data cache in cache coherency domain of the calling CPU.

Writes back and invalidates the entire data cache in cache coherency domain of the calling CPU. This function guarantees that all dirty cache lines are written back to system memory, and also invalidates all the data cache lines in the cache coherency domain of the calling CPU.

Definition at line 182 of file RiscVCache.c.

◆ WriteBackInvalidateDataCacheRange()

VOID *EFIAPI WriteBackInvalidateDataCacheRange	(	IN VOID *	Address,
		IN UINTN	Length
	)

Writes back and invalidates a range of data cache lines in the cache coherency domain of the calling CPU.

Writes back and invalidates the data cache lines specified by Address and Length. If Address is not aligned on a cache line boundary, then entire data cache line containing Address is written back and invalidated. If Address + Length is not aligned on a cache line boundary, then the entire data cache line containing Address + Length -1 is written back and invalidated. This function may choose to write back and invalidate the entire data cache if that is more efficient than writing back and invalidating the specified range. If Length is 0, then no data cache lines are written back and invalidated. Address is returned.

If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

Parameters

Address	The base address of the data cache lines to write back and invalidate. If the CPU is in a physical addressing mode, then Address is a physical address. If the CPU is in a virtual addressing mode, then Address is a virtual address.
Length	The number of bytes to write back and invalidate from the data cache.

Returns: Address of cache invalidation.

Definition at line 221 of file RiscVCache.c.

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ RISCV_CACHE_BLOCK_SIZE

◆ RISCV_CPU_FEATURE_CMO_BITMASK

Enumeration Type Documentation

◆ CACHE_OP

Function Documentation

◆ CacheOpCacheRange()

◆ InvalidateDataCache()

◆ InvalidateDataCacheRange()

◆ InvalidateInstructionCache()

◆ InvalidateInstructionCacheRange()

◆ RiscVIsCMOEnabled()

◆ WriteBackDataCache()

◆ WriteBackDataCacheRange()

◆ WriteBackInvalidateDataCache()

◆ WriteBackInvalidateDataCacheRange()