RiscVCache.c

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#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
 
//
// TODO: Grab cache block size and make Cache Management Operation
// enabling decision based on RISC-V CPU HOB in
// future when it is available and convert PcdRiscVFeatureOverride
// PCD to a pointer that contains pointer to bitmap structure
// which can be operated more elegantly.
//
#define RISCV_CACHE_BLOCK_SIZE         64
#define RISCV_CPU_FEATURE_CMO_BITMASK  0x1
 
typedef enum {
  CacheOpClean,
  CacheOpFlush,
  CacheOpInvld,
} CACHE_OP;
 
STATIC
BOOLEAN
RiscVIsCMOEnabled (
  VOID
  )
{
  // If CMO is disabled in HW, skip Override check
  // Otherwise this PCD can override settings
  return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) != 0);
}
 
STATIC
VOID
CacheOpCacheRange (
  IN VOID      *Address,
  IN UINTN     Length,
  IN CACHE_OP  Op
  )
{
  UINTN  CacheLineSize;
  UINTN  Start;
  UINTN  End;
 
  if (Length == 0) {
    return;
  }
 
  if ((Op != CacheOpInvld) && (Op != CacheOpFlush) && (Op != CacheOpClean)) {
    return;
  }
 
  ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
 
  CacheLineSize = RISCV_CACHE_BLOCK_SIZE;
 
  Start = (UINTN)Address;
  //
  // Calculate the cache line alignment
  //
  End    = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
  Start &= ~((UINTN)CacheLineSize - 1);
 
  DEBUG (
    (DEBUG_VERBOSE,
     "CacheOpCacheRange: Performing Cache Management Operation %d \n", Op)
    );
 
  do {
    switch (Op) {
      case CacheOpInvld:
        RiscVCpuCacheInvalCmoAsm (Start);
        break;
      case CacheOpFlush:
        RiscVCpuCacheFlushCmoAsm (Start);
        break;
      case CacheOpClean:
        RiscVCpuCacheCleanCmoAsm (Start);
        break;
      default:
        break;
    }
 
    Start = Start + CacheLineSize;
  } while (Start != End);
}
 
VOID
EFIAPI
InvalidateInstructionCache (
  VOID
  )
{
  RiscVInvalidateInstCacheFenceAsm ();
}
 
VOID *
EFIAPI
InvalidateInstructionCacheRange (
  IN VOID   *Address,
  IN UINTN  Length
  )
{
  DEBUG (
    (DEBUG_VERBOSE,
     "InvalidateInstructionCacheRange: RISC-V unsupported function.\n"
     "Invalidating the whole instruction cache instead.\n"
    )
    );
  InvalidateInstructionCache ();
  return Address;
}
 
VOID
EFIAPI
WriteBackInvalidateDataCache (
  VOID
  )
{
  ASSERT (FALSE);
  DEBUG ((
    DEBUG_ERROR,
    "WriteBackInvalidateDataCache: RISC-V unsupported function.\n"
    ));
}
 
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
  IN      VOID   *Address,
  IN      UINTN  Length
  )
{
  if (RiscVIsCMOEnabled ()) {
    CacheOpCacheRange (Address, Length, CacheOpFlush);
  } else {
    ASSERT (FALSE);
  }
 
  return Address;
}
 
VOID
EFIAPI
WriteBackDataCache (
  VOID
  )
{
  ASSERT (FALSE);
}
 
VOID *
EFIAPI
WriteBackDataCacheRange (
  IN      VOID   *Address,
  IN      UINTN  Length
  )
{
  if (RiscVIsCMOEnabled ()) {
    CacheOpCacheRange (Address, Length, CacheOpClean);
  } else {
    ASSERT (FALSE);
  }
 
  return Address;
}
 
VOID
EFIAPI
InvalidateDataCache (
  VOID
  )
{
  RiscVInvalidateDataCacheFenceAsm ();
}
 
VOID *
EFIAPI
InvalidateDataCacheRange (
  IN      VOID   *Address,
  IN      UINTN  Length
  )
{
  if (RiscVIsCMOEnabled ()) {
    CacheOpCacheRange (Address, Length, CacheOpInvld);
  } else {
    DEBUG (
      (DEBUG_VERBOSE,
       "InvalidateDataCacheRange: Zicbom not supported.\n"
       "Invalidating the whole Data cache instead.\n")
      );
    InvalidateDataCache ();
  }
 
  return Address;
}