36#define ALIGNED_2MB_MASK 0x1fffff
48 UINT32 AcceptPageSize;
69 if (
ALIGN_VALUE (StartAddress, SIZE_2MB) != StartAddress) {
70 StartAddress1 = StartAddress;
71 Length1 =
ALIGN_VALUE (StartAddress, SIZE_2MB) - StartAddress;
72 if (Length1 >= Size) {
76 StartAddress += Length1;
80 if (Size > SIZE_2MB) {
81 StartAddress2 = StartAddress;
82 Length2 = Size & ~(UINT64)ALIGNED_2MB_MASK;
83 StartAddress += Length2;
88 StartAddress3 = StartAddress;
94 Pages = Length1 / SIZE_4KB;
96 if (EFI_ERROR (Status)) {
102 Pages = Length2 / AcceptPageSize;
103 Status =
TdAcceptPages (StartAddress2, Pages, AcceptPageSize);
104 if (EFI_ERROR (Status)) {
110 Pages = Length3 / SIZE_4KB;
112 ASSERT (!EFI_ERROR (Status));
113 if (EFI_ERROR (Status)) {
130 RETURN_STATUS PcdStatus;
132 PcdStatus =
PcdSet64S (PcdConfidentialComputingGuestAttr, PlatformInfoHob->PcdConfidentialComputingGuestAttr);
134 PcdStatus =
PcdSetBoolS (PcdSetNxForStack, PlatformInfoHob->PcdSetNxForStack);
139 "HostBridgeDevId=0x%x, CCAttr=0x%x, SetNxForStack=%x\n",
140 PlatformInfoHob->HostBridgeDevId,
141 PlatformInfoHob->PcdConfidentialComputingGuestAttr,
142 PlatformInfoHob->PcdSetNxForStack
145 PcdStatus =
PcdSet32S (PcdCpuBootLogicalProcessorNumber, PlatformInfoHob->PcdCpuBootLogicalProcessorNumber);
147 PcdStatus =
PcdSet32S (PcdCpuMaxLogicalProcessorNumber, PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber);
152 "MaxCpuCount=0x%x, BootCpuCount=0x%x\n",
153 PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber,
154 PlatformInfoHob->PcdCpuBootLogicalProcessorNumber
157 PcdSet64S (PcdEmuVariableNvStoreReserved, PlatformInfoHob->PcdEmuVariableNvStoreReserved);
162 DEBUG ((DEBUG_INFO,
"TdxSharedBitMask=0x%llx\n",
PcdGet64 (PcdTdxSharedBitMask)));
165 PcdStatus =
PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);
167 PcdStatus =
PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);
169 PcdStatus =
PcdSet64S (PcdPciMmio32Base, PlatformInfoHob->PcdPciMmio32Base);
171 PcdStatus =
PcdSet64S (PcdPciMmio32Size, PlatformInfoHob->PcdPciMmio32Size);
173 PcdStatus =
PcdSet64S (PcdPciIoBase, PlatformInfoHob->PcdPciIoBase);
175 PcdStatus =
PcdSet64S (PcdPciIoSize, PlatformInfoHob->PcdPciIoSize);
199 Hob.Raw =
GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
200 while (Hob.Raw !=
NULL) {
203 "%a:%d: resource type 0x%x %llx %llx\n",
215 ResourceDescriptor = Hob.ResourceDescriptor;
219 Hob.Raw = GET_NEXT_HOB (Hob);
220 Hob.Raw =
GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw);
223 return ResourceDescriptor;
245 Hob.Raw =
GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
246 while (Hob.Raw !=
NULL) {
250 if (!ResourceDescriptor ||
253 ResourceDescriptor = Hob.ResourceDescriptor;
257 Hob.Raw = GET_NEXT_HOB (Hob);
258 Hob.Raw =
GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw);
261 return ResourceDescriptor;
287 while (!END_OF_HOB_LIST (Hob)) {
288 if ( (Hob.Header->
HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR)
289 && (Hob.ResourceDescriptor->
ResourceType == EFI_RESOURCE_MEMORY_MAPPED_IO))
298 Hob.Raw = GET_NEXT_HOB (Hob);
312 RETURN_STATUS PcdStatus;
317 UINT32 CpuMaxLogicalProcessorNumber;
324 if (GuidHob ==
NULL) {
325 return EFI_UNSUPPORTED;
332 ASSERT (PlatformInfo->HostBridgeDevId != 0);
333 PcdStatus =
PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfo->HostBridgeDevId);
336 #ifdef TDX_PEI_LESS_BOOT
341 SetPcdSettings (PlatformInfo);
349 gBS->InstallProtocolInterface (
351 &gEfiMpInitLibMpDepProtocolGuid,
365 gBS->InstallProtocolInterface (
367 &gEfiMpInitLibUpDepProtocolGuid,
375 Status =
gBS->InstallProtocolInterface (
377 &gEdkiiMemoryAcceptProtocolGuid,
379 &mMemoryAcceptProtocol
381 if (EFI_ERROR (Status)) {
382 DEBUG ((DEBUG_ERROR,
"Install EdkiiMemoryAcceptProtocol failed.\n"));
388 Status =
TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData);
391 CpuMaxLogicalProcessorNumber =
PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
397 if (CpuMaxLogicalProcessorNumber > TdReturnData.TdInfo.NumVcpus) {
398 PcdStatus =
PcdSet32S (PcdCpuMaxLogicalProcessorNumber, TdReturnData.TdInfo.NumVcpus);
407 Status =
gBS->CreateEvent (
415 Status =
gBS->RegisterProtocolNotify (
416 &gQemuAcpiTableNotifyProtocolGuid,
421 #define INIT_PCDSET(NAME, RES) do {\
422 PcdStatus = PcdSet64S (NAME##Base, (RES)->PhysicalStart); \
423 ASSERT_RETURN_ERROR (PcdStatus); \
424 PcdStatus = PcdSet64S (NAME##Size, (RES)->ResourceLength); \
425 ASSERT_RETURN_ERROR (PcdStatus); \
429 PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfo->HostBridgeDevId);
432 INIT_PCDSET (PcdPciMmio64, Res);
436 INIT_PCDSET (PcdPciIo, Res);
444 INIT_PCDSET (PcdPciMmio32, Res);
VOID *EFIAPI GetFirstHob(IN UINT16 Type)
VOID *EFIAPI GetFirstGuidHob(IN CONST EFI_GUID *Guid)
VOID *EFIAPI GetNextHob(IN UINT16 Type, IN CONST VOID *HobStart)
VOID *EFIAPI GetHobList(VOID)
UINTN EFIAPI TdCall(IN UINT64 Leaf, IN UINT64 Arg1, IN UINT64 Arg2, IN UINT64 Arg3, IN OUT VOID *Results)
#define ALIGN_VALUE(Value, Alignment)
#define ASSERT_RETURN_ERROR(StatusParameter)
#define DEBUG(Expression)
BOOLEAN EFIAPI TdIsEnabled()
RETURN_STATUS EFIAPI MemEncryptTdxSetPageSharedBit(IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages)
#define PcdGet64(TokenName)
#define FixedPcdGet32(TokenName)
#define PcdSetBoolS(TokenName, Value)
#define PcdGet32(TokenName)
#define PcdSet64S(TokenName, Value)
#define PcdSet32S(TokenName, Value)
#define PcdSet16S(TokenName, Value)
VOID EFIAPI AlterAcpiTable(IN EFI_EVENT Event, IN VOID *Context)
STATIC EFI_HOB_RESOURCE_DESCRIPTOR * GetResourceDescriptor(EFI_RESOURCE_TYPE Type, EFI_PHYSICAL_ADDRESS Start, EFI_PHYSICAL_ADDRESS End)
EFI_STATUS SetMmioSharedBit(VOID)
STATIC EFI_HOB_RESOURCE_DESCRIPTOR * GetHighestResourceDescriptor(EFI_RESOURCE_TYPE Type, EFI_PHYSICAL_ADDRESS End)
UINT64 EFIAPI TdSharedPageMask(VOID)
EFI_STATUS EFIAPI TdAcceptPages(IN UINT64 StartAddress, IN UINT64 NumberOfPages, IN UINT32 PageSize)
UINT64 EFI_PHYSICAL_ADDRESS
#define EFI_SIZE_TO_PAGES(Size)
EFI_PHYSICAL_ADDRESS PhysicalStart
EFI_RESOURCE_TYPE ResourceType