TianoCore EDK2 master
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Data Structures | |
struct | PTP_FIFO_REGISTERS |
union | PTP_FIFO_INTERFACE_IDENTIFIER |
union | PTP_FIFO_INTERFACE_CAPABILITY |
struct | PTP_CRB_REGISTERS |
union | PTP_CRB_INTERFACE_IDENTIFIER |
Typedefs | |
typedef PTP_FIFO_REGISTERS * | PTP_FIFO_REGISTERS_PTR |
typedef PTP_CRB_REGISTERS * | PTP_CRB_REGISTERS_PTR |
Platform TPM Profile Specification definition for TPM2.0. It covers both FIFO and CRB interface.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
Definition in file TpmPtp.h.
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0 |
#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0 |
#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1 |
Used by Software to indicate transition the TPM to and from the Idle state 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state. TPM SHALL complete this transition within TIMEOUT_C.
#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1 |
#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0 |
#define PTP_CRB_CONTROL_CANCEL BIT0 |
#define PTP_CRB_CONTROL_START BIT0 |
#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1 |
#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0 |
#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3 |
#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2 |
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) |
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) |
#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1 |
#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0 |
#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7 |
#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1 |
#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0 |
#define PTP_FIFO_ACC_ACTIVE BIT5 |
#define PTP_FIFO_ACC_ESTABLISH BIT0 |
#define PTP_FIFO_ACC_PENDIND BIT2 |
#define PTP_FIFO_ACC_RQUUSE BIT1 |
#define PTP_FIFO_ACC_SEIZE BIT3 |
#define PTP_FIFO_ACC_SEIZED BIT4 |
#define PTP_FIFO_STS_DATA BIT4 |
#define PTP_FIFO_STS_EX_CANCEL BIT0 |
#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) |
#define PTP_FIFO_STS_EXPECT BIT3 |
#define PTP_FIFO_STS_GO BIT5 |
#define PTP_FIFO_STS_READY BIT6 |
#define PTP_FIFO_STS_RETRY BIT1 |
#define PTP_FIFO_STS_SELFTEST_DONE BIT2 |
#define PTP_FIFO_STS_VALID BIT7 |
#define PTP_FIFO_VALID BIT7 |
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1 |
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0 |
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0 |
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0 |
typedef PTP_CRB_REGISTERS* PTP_CRB_REGISTERS_PTR |
typedef PTP_FIFO_REGISTERS* PTP_FIFO_REGISTERS_PTR |