TianoCore EDK2 master
X86UnitTestHost.c File Reference
#include "UnitTestHost.h"

Go to the source code of this file.

Macros

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS   0
 
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS   1
 
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES   2
 
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS   3
 
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS   4
 
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS   5
 
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR   6
 
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR   7
 

Functions

UINT32 EFIAPI UnitTestHostBaseLibAsmCpuid (IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
 
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuidEx (IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
 
VOID EFIAPI UnitTestHostBaseLibAsmDisableCache (VOID)
 
VOID EFIAPI UnitTestHostBaseLibAsmEnableCache (VOID)
 
UINT64 EFIAPI UnitTestHostBaseLibAsmReadMsr64 (IN UINT32 Index)
 
UINT64 EFIAPI UnitTestHostBaseLibAsmWriteMsr64 (IN UINT32 Index, IN UINT64 Value)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr0 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr2 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr3 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr4 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr0 (UINTN Cr0)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr2 (UINTN Cr2)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr3 (UINTN Cr3)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr4 (UINTN Cr4)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr0 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr1 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr2 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr3 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr4 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr5 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr6 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr7 (VOID)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr0 (UINTN Dr0)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr1 (UINTN Dr1)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr2 (UINTN Dr2)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr3 (UINTN Dr3)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr4 (UINTN Dr4)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr5 (UINTN Dr5)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr6 (UINTN Dr6)
 
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr7 (UINTN Dr7)
 
UINT16 EFIAPI UnitTestHostBaseLibAsmReadCs (VOID)
 
UINT16 EFIAPI UnitTestHostBaseLibAsmReadDs (VOID)
 
UINT16 EFIAPI UnitTestHostBaseLibAsmReadEs (VOID)
 
UINT16 EFIAPI UnitTestHostBaseLibAsmReadFs (VOID)
 
UINT16 EFIAPI UnitTestHostBaseLibAsmReadGs (VOID)
 
UINT16 EFIAPI UnitTestHostBaseLibAsmReadSs (VOID)
 
UINT16 EFIAPI UnitTestHostBaseLibAsmReadTr (VOID)
 
VOID EFIAPI UnitTestHostBaseLibAsmReadGdtr (OUT IA32_DESCRIPTOR *Gdtr)
 
VOID EFIAPI UnitTestHostBaseLibAsmWriteGdtr (IN CONST IA32_DESCRIPTOR *Gdtr)
 
VOID EFIAPI UnitTestHostBaseLibAsmReadIdtr (OUT IA32_DESCRIPTOR *Idtr)
 
VOID EFIAPI UnitTestHostBaseLibAsmWriteIdtr (IN CONST IA32_DESCRIPTOR *Idtr)
 
UINT16 EFIAPI UnitTestHostBaseLibAsmReadLdtr (VOID)
 
VOID EFIAPI UnitTestHostBaseLibAsmWriteLdtr (IN UINT16 Ldtr)
 
UINT64 EFIAPI UnitTestHostBaseLibAsmReadPmc (IN UINT32 Index)
 
UINTN EFIAPI UnitTestHostBaseLibAsmMonitor (IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
 
UINTN EFIAPI UnitTestHostBaseLibAsmMwait (IN UINTN Eax, IN UINTN Ecx)
 
VOID EFIAPI UnitTestHostBaseLibAsmWbinvd (VOID)
 
VOID EFIAPI UnitTestHostBaseLibAsmInvd (VOID)
 
VOID *EFIAPI UnitTestHostBaseLibAsmFlushCacheLine (IN VOID *LinearAddress)
 
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging32 (IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
 
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging32 (IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
 
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging64 (IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
 
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging64 (IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
 
VOID EFIAPI UnitTestHostBaseLibAsmGetThunk16Properties (OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
 
VOID EFIAPI UnitTestHostBaseLibAsmPrepareThunk16 (IN OUT THUNK_CONTEXT *ThunkContext)
 
VOID EFIAPI UnitTestHostBaseLibAsmThunk16 (IN OUT THUNK_CONTEXT *ThunkContext)
 
VOID EFIAPI UnitTestHostBaseLibAsmPrepareAndThunk16 (IN OUT THUNK_CONTEXT *ThunkContext)
 
VOID EFIAPI UnitTestHostBaseLibAsmWriteTr (IN UINT16 Selector)
 
VOID EFIAPI UnitTestHostBaseLibAsmLfence (VOID)
 
VOID EFIAPI UnitTestHostBaseLibPatchInstructionX86 (OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
 
UINT32 EFIAPI AsmCpuid (IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
 
UINT32 EFIAPI AsmCpuidEx (IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
 
VOID EFIAPI AsmDisableCache (VOID)
 
VOID EFIAPI AsmEnableCache (VOID)
 
UINT64 EFIAPI AsmReadMsr64 (IN UINT32 Index)
 
UINT64 EFIAPI AsmWriteMsr64 (IN UINT32 Index, IN UINT64 Value)
 
UINTN EFIAPI AsmReadCr0 (VOID)
 
UINTN EFIAPI AsmReadCr2 (VOID)
 
UINTN EFIAPI AsmReadCr3 (VOID)
 
UINTN EFIAPI AsmReadCr4 (VOID)
 
UINTN EFIAPI AsmWriteCr0 (UINTN Cr0)
 
UINTN EFIAPI AsmWriteCr2 (UINTN Cr2)
 
UINTN EFIAPI AsmWriteCr3 (UINTN Cr3)
 
UINTN EFIAPI AsmWriteCr4 (UINTN Cr4)
 
UINTN EFIAPI AsmReadDr0 (VOID)
 
UINTN EFIAPI AsmReadDr1 (VOID)
 
UINTN EFIAPI AsmReadDr2 (VOID)
 
UINTN EFIAPI AsmReadDr3 (VOID)
 
UINTN EFIAPI AsmReadDr4 (VOID)
 
UINTN EFIAPI AsmReadDr5 (VOID)
 
UINTN EFIAPI AsmReadDr6 (VOID)
 
UINTN EFIAPI AsmReadDr7 (VOID)
 
UINTN EFIAPI AsmWriteDr0 (UINTN Dr0)
 
UINTN EFIAPI AsmWriteDr1 (UINTN Dr1)
 
UINTN EFIAPI AsmWriteDr2 (UINTN Dr2)
 
UINTN EFIAPI AsmWriteDr3 (UINTN Dr3)
 
UINTN EFIAPI AsmWriteDr4 (UINTN Dr4)
 
UINTN EFIAPI AsmWriteDr5 (UINTN Dr5)
 
UINTN EFIAPI AsmWriteDr6 (UINTN Dr6)
 
UINTN EFIAPI AsmWriteDr7 (UINTN Dr7)
 
UINT16 EFIAPI AsmReadCs (VOID)
 
UINT16 EFIAPI AsmReadDs (VOID)
 
UINT16 EFIAPI AsmReadEs (VOID)
 
UINT16 EFIAPI AsmReadFs (VOID)
 
UINT16 EFIAPI AsmReadGs (VOID)
 
UINT16 EFIAPI AsmReadSs (VOID)
 
UINT16 EFIAPI AsmReadTr (VOID)
 
VOID EFIAPI AsmReadGdtr (OUT IA32_DESCRIPTOR *Gdtr)
 
VOID EFIAPI AsmWriteGdtr (IN CONST IA32_DESCRIPTOR *Gdtr)
 
VOID EFIAPI AsmReadIdtr (OUT IA32_DESCRIPTOR *Idtr)
 
VOID EFIAPI AsmWriteIdtr (IN CONST IA32_DESCRIPTOR *Idtr)
 
UINT16 EFIAPI AsmReadLdtr (VOID)
 
VOID EFIAPI AsmWriteLdtr (IN UINT16 Ldtr)
 
UINT64 EFIAPI AsmReadPmc (IN UINT32 Index)
 
UINTN EFIAPI AsmMonitor (IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
 
UINTN EFIAPI AsmMwait (IN UINTN Eax, IN UINTN Ecx)
 
VOID EFIAPI AsmWbinvd (VOID)
 
VOID EFIAPI AsmInvd (VOID)
 
VOID *EFIAPI AsmFlushCacheLine (IN VOID *LinearAddress)
 
VOID EFIAPI AsmEnablePaging32 (IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
 
VOID EFIAPI AsmDisablePaging32 (IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
 
VOID EFIAPI AsmEnablePaging64 (IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
 
VOID EFIAPI AsmDisablePaging64 (IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
 
VOID EFIAPI AsmGetThunk16Properties (OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
 
VOID EFIAPI AsmPrepareThunk16 (IN OUT THUNK_CONTEXT *ThunkContext)
 
VOID EFIAPI AsmThunk16 (IN OUT THUNK_CONTEXT *ThunkContext)
 
VOID EFIAPI AsmPrepareAndThunk16 (IN OUT THUNK_CONTEXT *ThunkContext)
 
VOID EFIAPI AsmWriteTr (IN UINT16 Selector)
 
VOID EFIAPI AsmLfence (VOID)
 
VOID EFIAPI PatchInstructionX86 (OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
 

Variables

STATIC UINT64 mUnitTestHostBaseLibMsr [2][0x1000]
 
STATIC UINTN mUnitTestHostBaseLibCr [5]
 
STATIC UINTN mUnitTestHostBaseLibDr [8]
 
STATIC UINT16 mUnitTestHostBaseLibSegment [8]
 
STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr
 
STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr
 
STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
 
STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86
 
UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib
 

Detailed Description

IA32/X64 specific Unit Test Host functions.

Copyright (c) 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file X86UnitTestHost.c.

Macro Definition Documentation

◆ UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS   0

Defines for mUnitTestHostBaseLibSegment indexes

Definition at line 14 of file X86UnitTestHost.c.

◆ UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS   1

Definition at line 15 of file X86UnitTestHost.c.

◆ UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES   2

Definition at line 16 of file X86UnitTestHost.c.

◆ UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS   3

Definition at line 17 of file X86UnitTestHost.c.

◆ UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS   4

Definition at line 18 of file X86UnitTestHost.c.

◆ UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR   7

Definition at line 21 of file X86UnitTestHost.c.

◆ UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS   5

Definition at line 19 of file X86UnitTestHost.c.

◆ UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR

#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR   6

Definition at line 20 of file X86UnitTestHost.c.

Function Documentation

◆ AsmCpuid()

UINT32 EFIAPI AsmCpuid ( IN UINT32  Index,
OUT UINT32 *Eax  OPTIONAL,
OUT UINT32 *Ebx  OPTIONAL,
OUT UINT32 *Ecx  OPTIONAL,
OUT UINT32 *Edx  OPTIONAL 
)

Retrieves CPUID information.

Executes the CPUID instruction with EAX set to the value specified by Index. This function always returns Index. If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. This function is only available on IA-32 and x64.

Parameters
IndexThe 32-bit value to load into EAX prior to invoking the CPUID instruction.
EaxThe pointer to the 32-bit EAX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EbxThe pointer to the 32-bit EBX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EcxThe pointer to the 32-bit ECX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EdxThe pointer to the 32-bit EDX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
Returns
Index.

Definition at line 1525 of file X86UnitTestHost.c.

◆ AsmCpuidEx()

UINT32 EFIAPI AsmCpuidEx ( IN UINT32  Index,
IN UINT32  SubIndex,
OUT UINT32 *Eax  OPTIONAL,
OUT UINT32 *Ebx  OPTIONAL,
OUT UINT32 *Ecx  OPTIONAL,
OUT UINT32 *Edx  OPTIONAL 
)

Retrieves CPUID information using an extended leaf identifier.

Executes the CPUID instruction with EAX set to the value specified by Index and ECX set to the value specified by SubIndex. This function always returns Index. This function is only available on IA-32 and x64.

If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.

Parameters
IndexThe 32-bit value to load into EAX prior to invoking the CPUID instruction.
SubIndexThe 32-bit value to load into ECX prior to invoking the CPUID instruction.
EaxThe pointer to the 32-bit EAX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EbxThe pointer to the 32-bit EBX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EcxThe pointer to the 32-bit ECX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EdxThe pointer to the 32-bit EDX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
Returns
Index.

Definition at line 1570 of file X86UnitTestHost.c.

◆ AsmDisableCache()

VOID EFIAPI AsmDisableCache ( VOID  )

Set CD bit and clear NW bit of CR0 followed by a WBINVD.

Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0, and executing a WBINVD instruction. This function is only available on IA-32 and x64.

Definition at line 1591 of file X86UnitTestHost.c.

◆ AsmDisablePaging32()

VOID EFIAPI AsmDisablePaging32 ( IN SWITCH_STACK_ENTRY_POINT  EntryPoint,
IN VOID *Context1  OPTIONAL,
IN VOID *Context2  OPTIONAL,
IN VOID NewStack 
)

Disables the 32-bit paging mode on the CPU.

Disables the 32-bit paging mode on the CPU and returns to 32-bit protected mode. This function assumes the current execution mode is 32-paged protected mode. This function is only available on IA-32. After the 32-bit paging mode is disabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and may be NULL. The function EntryPoint must never return.

If the current execution mode is not 32-bit paged mode, then ASSERT(). If EntryPoint is NULL, then ASSERT(). If NewStack is NULL, then ASSERT().

There are a number of constraints that must be followed before calling this function: 1) Interrupts must be disabled. 2) The caller must be in 32-bit paged mode. 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode. 4) CR3 must point to valid page tables that guarantee that the pages for this function and the stack are identity mapped.

Parameters
EntryPointA pointer to function to call with the new stack after paging is disabled.
Context1A pointer to the context to pass into the EntryPoint function as the first parameter after paging is disabled.
Context2A pointer to the context to pass into the EntryPoint function as the second parameter after paging is disabled.
NewStackA pointer to the new stack to use for the EntryPoint function after paging is disabled.

Definition at line 2586 of file X86UnitTestHost.c.

◆ AsmDisablePaging64()

VOID EFIAPI AsmDisablePaging64 ( IN UINT16  Cs,
IN UINT32  EntryPoint,
IN UINT32 Context1  OPTIONAL,
IN UINT32 Context2  OPTIONAL,
IN UINT32  NewStack 
)

Disables the 64-bit paging mode on the CPU.

Disables the 64-bit paging mode on the CPU and returns to 32-bit protected mode. This function assumes the current execution mode is 64-paging mode. This function is only available on x64. After the 64-bit paging mode is disabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and may be 0. The function EntryPoint must never return.

If the current execution mode is not 64-bit paged mode, then ASSERT(). If EntryPoint is 0, then ASSERT(). If NewStack is 0, then ASSERT().

Parameters
CsThe 16-bit selector to load in the CS before EntryPoint is called. The descriptor in the GDT that this selector references must be setup for 32-bit protected mode.
EntryPointThe 64-bit virtual address of the function to call with the new stack after paging is disabled.
Context1The 64-bit virtual address of the context to pass into the EntryPoint function as the first parameter after paging is disabled.
Context2The 64-bit virtual address of the context to pass into the EntryPoint function as the second parameter after paging is disabled.
NewStackThe 64-bit virtual address of the new stack to use for the EntryPoint function after paging is disabled.

Definition at line 2673 of file X86UnitTestHost.c.

◆ AsmEnableCache()

VOID EFIAPI AsmEnableCache ( VOID  )

Perform a WBINVD and clear both the CD and NW bits of CR0.

Enables the caches by executing a WBINVD instruction and then clear both the CD and NW bits of CR0 to 0. This function is only available on IA-32 and x64.

Definition at line 1607 of file X86UnitTestHost.c.

◆ AsmEnablePaging32()

VOID EFIAPI AsmEnablePaging32 ( IN SWITCH_STACK_ENTRY_POINT  EntryPoint,
IN VOID *Context1  OPTIONAL,
IN VOID *Context2  OPTIONAL,
IN VOID NewStack 
)

Enables the 32-bit paging mode on the CPU.

Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables must be properly initialized prior to calling this service. This function assumes the current execution mode is 32-bit protected mode. This function is only available on IA-32. After the 32-bit paging mode is enabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and may be NULL. The function EntryPoint must never return.

If the current execution mode is not 32-bit protected mode, then ASSERT(). If EntryPoint is NULL, then ASSERT(). If NewStack is NULL, then ASSERT().

There are a number of constraints that must be followed before calling this function: 1) Interrupts must be disabled. 2) The caller must be in 32-bit protected mode with flat descriptors. This means all descriptors must have a base of 0 and a limit of 4GB. 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat descriptors. 4) CR3 must point to valid page tables that will be used once the transition is complete, and those page tables must guarantee that the pages for this function and the stack are identity mapped.

Parameters
EntryPointA pointer to function to call with the new stack after paging is enabled.
Context1A pointer to the context to pass into the EntryPoint function as the first parameter after paging is enabled.
Context2A pointer to the context to pass into the EntryPoint function as the second parameter after paging is enabled.
NewStackA pointer to the new stack to use for the EntryPoint function after paging is enabled.

Definition at line 2540 of file X86UnitTestHost.c.

◆ AsmEnablePaging64()

VOID EFIAPI AsmEnablePaging64 ( IN UINT16  Cs,
IN UINT64  EntryPoint,
IN UINT64 Context1  OPTIONAL,
IN UINT64 Context2  OPTIONAL,
IN UINT64  NewStack 
)

Enables the 64-bit paging mode on the CPU.

Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables must be properly initialized prior to calling this service. This function assumes the current execution mode is 32-bit protected mode with flat descriptors. This function is only available on IA-32. After the 64-bit paging mode is enabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and may be 0. The function EntryPoint must never return.

If the current execution mode is not 32-bit protected mode with flat descriptors, then ASSERT(). If EntryPoint is 0, then ASSERT(). If NewStack is 0, then ASSERT().

Parameters
CsThe 16-bit selector to load in the CS before EntryPoint is called. The descriptor in the GDT that this selector references must be setup for long mode.
EntryPointThe 64-bit virtual address of the function to call with the new stack after paging is enabled.
Context1The 64-bit virtual address of the context to pass into the EntryPoint function as the first parameter after paging is enabled.
Context2The 64-bit virtual address of the context to pass into the EntryPoint function as the second parameter after paging is enabled.
NewStackThe 64-bit virtual address of the new stack to use for the EntryPoint function after paging is enabled.

Definition at line 2630 of file X86UnitTestHost.c.

◆ AsmFlushCacheLine()

VOID *EFIAPI AsmFlushCacheLine ( IN VOID LinearAddress)

Flushes a cache line from all the instruction and data caches within the coherency domain of the CPU.

Flushed the cache line specified by LinearAddress, and returns LinearAddress. This function is only available on IA-32 and x64.

Parameters
LinearAddressThe address of the cache line to flush. If the CPU is in a physical addressing mode, then LinearAddress is a physical address. If the CPU is in a virtual addressing mode, then LinearAddress is a virtual address.
Returns
LinearAddress.

Definition at line 2494 of file X86UnitTestHost.c.

◆ AsmGetThunk16Properties()

VOID EFIAPI AsmGetThunk16Properties ( OUT UINT32 RealModeBufferSize,
OUT UINT32 ExtraStackSize 
)

Retrieves the properties for 16-bit thunk functions.

Computes the size of the buffer and stack below 1MB required to use the AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This buffer size is returned in RealModeBufferSize, and the stack size is returned in ExtraStackSize. If parameters are passed to the 16-bit real mode code, then the actual minimum stack size is ExtraStackSize plus the maximum number of bytes that need to be passed to the 16-bit real mode code.

If RealModeBufferSize is NULL, then ASSERT(). If ExtraStackSize is NULL, then ASSERT().

Parameters
RealModeBufferSizeA pointer to the size of the buffer below 1MB required to use the 16-bit thunk functions.
ExtraStackSizeA pointer to the extra size of stack below 1MB that the 16-bit thunk functions require for temporary storage in the transition to and from 16-bit real mode.

Definition at line 2707 of file X86UnitTestHost.c.

◆ AsmInvd()

VOID EFIAPI AsmInvd ( VOID  )

Executes a INVD instruction.

Executes a INVD instruction. This function is only available on IA-32 and x64.

Definition at line 2470 of file X86UnitTestHost.c.

◆ AsmLfence()

VOID EFIAPI AsmLfence ( VOID  )

Performs a serializing operation on all load-from-memory instructions that were issued prior the AsmLfence function.

Executes a LFENCE instruction. This function is only available on IA-32 and x64.

Definition at line 2852 of file X86UnitTestHost.c.

◆ AsmMonitor()

UINTN EFIAPI AsmMonitor ( IN UINTN  Eax,
IN UINTN  Ecx,
IN UINTN  Edx 
)

Sets up a monitor buffer that is used by AsmMwait().

Executes a MONITOR instruction with the register state specified by Eax, Ecx and Edx. Returns Eax. This function is only available on IA-32 and x64.

Parameters
EaxThe value to load into EAX or RAX before executing the MONITOR instruction.
EcxThe value to load into ECX or RCX before executing the MONITOR instruction.
EdxThe value to load into EDX or RDX before executing the MONITOR instruction.
Returns
Eax

Definition at line 2412 of file X86UnitTestHost.c.

◆ AsmMwait()

UINTN EFIAPI AsmMwait ( IN UINTN  Eax,
IN UINTN  Ecx 
)

Executes an MWAIT instruction.

Executes an MWAIT instruction with the register state specified by Eax and Ecx. Returns Eax. This function is only available on IA-32 and x64.

Parameters
EaxThe value to load into EAX or RAX before executing the MONITOR instruction.
EcxThe value to load into ECX or RCX before executing the MONITOR instruction.
Returns
Eax

Definition at line 2437 of file X86UnitTestHost.c.

◆ AsmPrepareAndThunk16()

VOID EFIAPI AsmPrepareAndThunk16 ( IN OUT THUNK_CONTEXT *  ThunkContext)

Prepares all structures and code for a 16-bit real mode thunk, transfers control to a 16-bit real mode entry point, and returns the results.

Prepares all structures and code for a 16-bit real mode thunk, transfers control to a 16-bit real mode entry point, and returns the results. If the caller only need to perform a single 16-bit real mode thunk, then this service should be used. If the caller intends to make more than one 16-bit real mode thunk, then it is more efficient if AsmPrepareThunk16() is called once and AsmThunk16() can be called for each 16-bit real mode thunk.

This interface is limited to be used in either physical mode or virtual modes with paging enabled where the virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.

See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.

Parameters
ThunkContextA pointer to the context structure that describes the 16-bit real mode code to call.

Definition at line 2822 of file X86UnitTestHost.c.

◆ AsmPrepareThunk16()

VOID EFIAPI AsmPrepareThunk16 ( IN OUT THUNK_CONTEXT *  ThunkContext)

Prepares all structures a code required to use AsmThunk16().

Prepares all structures and code required to use AsmThunk16().

This interface is limited to be used in either physical mode or virtual modes with paging enabled where the virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.

If ThunkContext is NULL, then ASSERT().

Parameters
ThunkContextA pointer to the context structure that describes the 16-bit real mode code to call.

Definition at line 2731 of file X86UnitTestHost.c.

◆ AsmReadCr0()

UINTN EFIAPI AsmReadCr0 ( VOID  )

Reads the current value of the Control Register 0 (CR0).

Reads and returns the current value of CR0. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of the Control Register 0 (CR0).

Definition at line 1676 of file X86UnitTestHost.c.

◆ AsmReadCr2()

UINTN EFIAPI AsmReadCr2 ( VOID  )

Reads the current value of the Control Register 2 (CR2).

Reads and returns the current value of CR2. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of the Control Register 2 (CR2).

Definition at line 1695 of file X86UnitTestHost.c.

◆ AsmReadCr3()

UINTN EFIAPI AsmReadCr3 ( VOID  )

Reads the current value of the Control Register 3 (CR3).

Reads and returns the current value of CR3. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of the Control Register 3 (CR3).

Definition at line 1714 of file X86UnitTestHost.c.

◆ AsmReadCr4()

UINTN EFIAPI AsmReadCr4 ( VOID  )

Reads the current value of the Control Register 4 (CR4).

Reads and returns the current value of CR4. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of the Control Register 4 (CR4).

Definition at line 1733 of file X86UnitTestHost.c.

◆ AsmReadCs()

UINT16 EFIAPI AsmReadCs ( VOID  )

Reads the current value of Code Segment Register (CS).

Reads and returns the current value of CS. This function is only available on IA-32 and x64.

Returns
The current value of CS.

Definition at line 2143 of file X86UnitTestHost.c.

◆ AsmReadDr0()

UINTN EFIAPI AsmReadDr0 ( VOID  )

Reads the current value of Debug Register 0 (DR0).

Reads and returns the current value of DR0. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 0 (DR0).

Definition at line 1832 of file X86UnitTestHost.c.

◆ AsmReadDr1()

UINTN EFIAPI AsmReadDr1 ( VOID  )

Reads the current value of Debug Register 1 (DR1).

Reads and returns the current value of DR1. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 1 (DR1).

Definition at line 1851 of file X86UnitTestHost.c.

◆ AsmReadDr2()

UINTN EFIAPI AsmReadDr2 ( VOID  )

Reads the current value of Debug Register 2 (DR2).

Reads and returns the current value of DR2. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 2 (DR2).

Definition at line 1870 of file X86UnitTestHost.c.

◆ AsmReadDr3()

UINTN EFIAPI AsmReadDr3 ( VOID  )

Reads the current value of Debug Register 3 (DR3).

Reads and returns the current value of DR3. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 3 (DR3).

Definition at line 1889 of file X86UnitTestHost.c.

◆ AsmReadDr4()

UINTN EFIAPI AsmReadDr4 ( VOID  )

Reads the current value of Debug Register 4 (DR4).

Reads and returns the current value of DR4. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 4 (DR4).

Definition at line 1908 of file X86UnitTestHost.c.

◆ AsmReadDr5()

UINTN EFIAPI AsmReadDr5 ( VOID  )

Reads the current value of Debug Register 5 (DR5).

Reads and returns the current value of DR5. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 5 (DR5).

Definition at line 1927 of file X86UnitTestHost.c.

◆ AsmReadDr6()

UINTN EFIAPI AsmReadDr6 ( VOID  )

Reads the current value of Debug Register 6 (DR6).

Reads and returns the current value of DR6. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 6 (DR6).

Definition at line 1946 of file X86UnitTestHost.c.

◆ AsmReadDr7()

UINTN EFIAPI AsmReadDr7 ( VOID  )

Reads the current value of Debug Register 7 (DR7).

Reads and returns the current value of DR7. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 7 (DR7).

Definition at line 1965 of file X86UnitTestHost.c.

◆ AsmReadDs()

UINT16 EFIAPI AsmReadDs ( VOID  )

Reads the current value of Data Segment Register (DS).

Reads and returns the current value of DS. This function is only available on IA-32 and x64.

Returns
The current value of DS.

Definition at line 2161 of file X86UnitTestHost.c.

◆ AsmReadEs()

UINT16 EFIAPI AsmReadEs ( VOID  )

Reads the current value of Extra Segment Register (ES).

Reads and returns the current value of ES. This function is only available on IA-32 and x64.

Returns
The current value of ES.

Definition at line 2179 of file X86UnitTestHost.c.

◆ AsmReadFs()

UINT16 EFIAPI AsmReadFs ( VOID  )

Reads the current value of FS Data Segment Register (FS).

Reads and returns the current value of FS. This function is only available on IA-32 and x64.

Returns
The current value of FS.

Definition at line 2197 of file X86UnitTestHost.c.

◆ AsmReadGdtr()

VOID EFIAPI AsmReadGdtr ( OUT IA32_DESCRIPTOR *  Gdtr)

Reads the current Global Descriptor Table Register(GDTR) descriptor.

Reads and returns the current GDTR descriptor and returns it in Gdtr. This function is only available on IA-32 and x64.

If Gdtr is NULL, then ASSERT().

Parameters
GdtrThe pointer to a GDTR descriptor.

Definition at line 2271 of file X86UnitTestHost.c.

◆ AsmReadGs()

UINT16 EFIAPI AsmReadGs ( VOID  )

Reads the current value of GS Data Segment Register (GS).

Reads and returns the current value of GS. This function is only available on IA-32 and x64.

Returns
The current value of GS.

Definition at line 2215 of file X86UnitTestHost.c.

◆ AsmReadIdtr()

VOID EFIAPI AsmReadIdtr ( OUT IA32_DESCRIPTOR *  Idtr)

Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.

Reads and returns the current IDTR descriptor and returns it in Idtr. This function is only available on IA-32 and x64.

If Idtr is NULL, then ASSERT().

Parameters
IdtrThe pointer to a IDTR descriptor.

Definition at line 2311 of file X86UnitTestHost.c.

◆ AsmReadLdtr()

UINT16 EFIAPI AsmReadLdtr ( VOID  )

Reads the current Local Descriptor Table Register(LDTR) selector.

Reads and returns the current 16-bit LDTR descriptor value. This function is only available on IA-32 and x64.

Returns
The current selector of LDT.

Definition at line 2349 of file X86UnitTestHost.c.

◆ AsmReadMsr64()

UINT64 EFIAPI AsmReadMsr64 ( IN UINT32  Index)

Returns a 64-bit Machine Specific Register(MSR).

Reads and returns the 64-bit MSR specified by Index. No parameter checking is performed on Index, and some Index values may cause CPU exceptions. The caller must either guarantee that Index is valid, or the caller must set up exception handlers to catch the exceptions. This function is only available on IA-32 and x64.

Parameters
IndexThe 32-bit MSR index to read.
Returns
The value of the MSR identified by Index.

Definition at line 1630 of file X86UnitTestHost.c.

◆ AsmReadPmc()

UINT64 EFIAPI AsmReadPmc ( IN UINT32  Index)

Reads the current value of a Performance Counter (PMC).

Reads and returns the current value of performance counter specified by Index. This function is only available on IA-32 and x64.

Parameters
IndexThe 32-bit Performance Counter index to read.
Returns
The value of the PMC specified by Index.

Definition at line 2387 of file X86UnitTestHost.c.

◆ AsmReadSs()

UINT16 EFIAPI AsmReadSs ( VOID  )

Reads the current value of Stack Segment Register (SS).

Reads and returns the current value of SS. This function is only available on IA-32 and x64.

Returns
The current value of SS.

Definition at line 2233 of file X86UnitTestHost.c.

◆ AsmReadTr()

UINT16 EFIAPI AsmReadTr ( VOID  )

Reads the current value of Task Register (TR).

Reads and returns the current value of TR. This function is only available on IA-32 and x64.

Returns
The current value of TR.

Definition at line 2251 of file X86UnitTestHost.c.

◆ AsmThunk16()

VOID EFIAPI AsmThunk16 ( IN OUT THUNK_CONTEXT *  ThunkContext)

Transfers control to a 16-bit real mode entry point and returns the results.

Transfers control to a 16-bit real mode entry point and returns the results. AsmPrepareThunk16() must be called with ThunkContext before this function is used. This function must be called with interrupts disabled.

The register state from the RealModeState field of ThunkContext is restored just prior to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState, which is used to set the interrupt state when a 16-bit real mode entry point is called. Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState. The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function. The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction, so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry point must exit with a RETF instruction. The register state is captured into RealModeState immediately after the RETF instruction is executed.

If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.

If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode. This includes the base vectors, the interrupt masks, and the edge/level trigger mode.

If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.

If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to disable the A20 mask.

If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.

If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.

If ThunkContext is NULL, then ASSERT(). If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT(). If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in ThunkAttributes, then ASSERT().

This interface is limited to be used in either physical mode or virtual modes with paging enabled where the virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.

Parameters
ThunkContextA pointer to the context structure that describes the 16-bit real mode code to call.

Definition at line 2793 of file X86UnitTestHost.c.

◆ AsmWbinvd()

VOID EFIAPI AsmWbinvd ( VOID  )

Executes a WBINVD instruction.

Executes a WBINVD instruction. This function is only available on IA-32 and x64.

Definition at line 2454 of file X86UnitTestHost.c.

◆ AsmWriteCr0()

UINTN EFIAPI AsmWriteCr0 ( UINTN  Cr0)

Writes a value to Control Register 0 (CR0).

Writes and returns a new value to CR0. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Cr0The value to write to CR0.
Returns
The value written to CR0.

Definition at line 1753 of file X86UnitTestHost.c.

◆ AsmWriteCr2()

UINTN EFIAPI AsmWriteCr2 ( UINTN  Cr2)

Writes a value to Control Register 2 (CR2).

Writes and returns a new value to CR2. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Cr2The value to write to CR2.
Returns
The value written to CR2.

Definition at line 1773 of file X86UnitTestHost.c.

◆ AsmWriteCr3()

UINTN EFIAPI AsmWriteCr3 ( UINTN  Cr3)

Writes a value to Control Register 3 (CR3).

Writes and returns a new value to CR3. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Cr3The value to write to CR3.
Returns
The value written to CR3.

Definition at line 1793 of file X86UnitTestHost.c.

◆ AsmWriteCr4()

UINTN EFIAPI AsmWriteCr4 ( UINTN  Cr4)

Writes a value to Control Register 4 (CR4).

Writes and returns a new value to CR4. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Cr4The value to write to CR4.
Returns
The value written to CR4.

Definition at line 1813 of file X86UnitTestHost.c.

◆ AsmWriteDr0()

UINTN EFIAPI AsmWriteDr0 ( UINTN  Dr0)

Writes a value to Debug Register 0 (DR0).

Writes and returns a new value to DR0. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr0The value to write to Dr0.
Returns
The value written to Debug Register 0 (DR0).

Definition at line 1985 of file X86UnitTestHost.c.

◆ AsmWriteDr1()

UINTN EFIAPI AsmWriteDr1 ( UINTN  Dr1)

Writes a value to Debug Register 1 (DR1).

Writes and returns a new value to DR1. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr1The value to write to Dr1.
Returns
The value written to Debug Register 1 (DR1).

Definition at line 2005 of file X86UnitTestHost.c.

◆ AsmWriteDr2()

UINTN EFIAPI AsmWriteDr2 ( UINTN  Dr2)

Writes a value to Debug Register 2 (DR2).

Writes and returns a new value to DR2. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr2The value to write to Dr2.
Returns
The value written to Debug Register 2 (DR2).

Definition at line 2025 of file X86UnitTestHost.c.

◆ AsmWriteDr3()

UINTN EFIAPI AsmWriteDr3 ( UINTN  Dr3)

Writes a value to Debug Register 3 (DR3).

Writes and returns a new value to DR3. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr3The value to write to Dr3.
Returns
The value written to Debug Register 3 (DR3).

Definition at line 2045 of file X86UnitTestHost.c.

◆ AsmWriteDr4()

UINTN EFIAPI AsmWriteDr4 ( UINTN  Dr4)

Writes a value to Debug Register 4 (DR4).

Writes and returns a new value to DR4. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr4The value to write to Dr4.
Returns
The value written to Debug Register 4 (DR4).

Definition at line 2065 of file X86UnitTestHost.c.

◆ AsmWriteDr5()

UINTN EFIAPI AsmWriteDr5 ( UINTN  Dr5)

Writes a value to Debug Register 5 (DR5).

Writes and returns a new value to DR5. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr5The value to write to Dr5.
Returns
The value written to Debug Register 5 (DR5).

Definition at line 2085 of file X86UnitTestHost.c.

◆ AsmWriteDr6()

UINTN EFIAPI AsmWriteDr6 ( UINTN  Dr6)

Writes a value to Debug Register 6 (DR6).

Writes and returns a new value to DR6. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr6The value to write to Dr6.
Returns
The value written to Debug Register 6 (DR6).

Definition at line 2105 of file X86UnitTestHost.c.

◆ AsmWriteDr7()

UINTN EFIAPI AsmWriteDr7 ( UINTN  Dr7)

Writes a value to Debug Register 7 (DR7).

Writes and returns a new value to DR7. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr7The value to write to Dr7.
Returns
The value written to Debug Register 7 (DR7).

Definition at line 2125 of file X86UnitTestHost.c.

◆ AsmWriteGdtr()

VOID EFIAPI AsmWriteGdtr ( IN CONST IA32_DESCRIPTOR *  Gdtr)

Writes the current Global Descriptor Table Register (GDTR) descriptor.

Writes and the current GDTR descriptor specified by Gdtr. This function is only available on IA-32 and x64.

If Gdtr is NULL, then ASSERT().

Parameters
GdtrThe pointer to a GDTR descriptor.

Definition at line 2291 of file X86UnitTestHost.c.

◆ AsmWriteIdtr()

VOID EFIAPI AsmWriteIdtr ( IN CONST IA32_DESCRIPTOR *  Idtr)

Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.

Writes the current IDTR descriptor and returns it in Idtr. This function is only available on IA-32 and x64.

If Idtr is NULL, then ASSERT().

Parameters
IdtrThe pointer to a IDTR descriptor.

Definition at line 2331 of file X86UnitTestHost.c.

◆ AsmWriteLdtr()

VOID EFIAPI AsmWriteLdtr ( IN UINT16  Ldtr)

Writes the current Local Descriptor Table Register (LDTR) selector.

Writes and the current LDTR descriptor specified by Ldtr. This function is only available on IA-32 and x64.

Parameters
Ldtr16-bit LDTR selector value.

Definition at line 2367 of file X86UnitTestHost.c.

◆ AsmWriteMsr64()

UINT64 EFIAPI AsmWriteMsr64 ( IN UINT32  Index,
IN UINT64  Value 
)

Writes a 64-bit value to a Machine Specific Register(MSR), and returns the value.

Writes the 64-bit value specified by Value to the MSR specified by Index. The 64-bit value written to the MSR is returned. No parameter checking is performed on Index or Value, and some of these may cause CPU exceptions. The caller must either guarantee that Index and Value are valid, or the caller must establish proper exception handlers. This function is only available on IA-32 and x64.

Parameters
IndexThe 32-bit MSR index to write.
ValueThe 64-bit value to write to the MSR.
Returns
Value

Definition at line 1656 of file X86UnitTestHost.c.

◆ AsmWriteTr()

VOID EFIAPI AsmWriteTr ( IN UINT16  Selector)

Load given selector into TR register.

Parameters
[in]SelectorTask segment selector

Definition at line 2836 of file X86UnitTestHost.c.

◆ PatchInstructionX86()

VOID EFIAPI PatchInstructionX86 ( OUT X86_ASSEMBLY_PATCH_LABEL *  InstructionEnd,
IN UINT64  PatchValue,
IN UINTN  ValueSize 
)

Patch the immediate operand of an IA32 or X64 instruction such that the byte, word, dword or qword operand is encoded at the end of the instruction's binary representation.

This function should be used to update object code that was compiled with NASM from assembly source code. Example:

NASM source code:

  mov     eax, strict dword 0 ; the imm32 zero operand will be patched

ASM_PFX(gPatchCr3): mov cr3, eax

C source code:

X86_ASSEMBLY_PATCH_LABEL gPatchCr3; PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);

Parameters
[out]InstructionEndPointer right past the instruction to patch. The immediate operand to patch is expected to comprise the trailing bytes of the instruction. If InstructionEnd is closer to address 0 than ValueSize permits, then ASSERT().
[in]PatchValueThe constant to write to the immediate operand. The caller is responsible for ensuring that PatchValue can be represented in the byte, word, dword or qword operand (as indicated through ValueSize); otherwise ASSERT().
[in]ValueSizeThe size of the operand in bytes; must be 1, 2, 4, or 8. ASSERT() otherwise.

Definition at line 2895 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmCpuid()

UINT32 EFIAPI UnitTestHostBaseLibAsmCpuid ( IN UINT32  Index,
OUT UINT32 *Eax  OPTIONAL,
OUT UINT32 *Ebx  OPTIONAL,
OUT UINT32 *Ecx  OPTIONAL,
OUT UINT32 *Edx  OPTIONAL 
)

Retrieves CPUID information.

Executes the CPUID instruction with EAX set to the value specified by Index. This function always returns Index. If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. This function is only available on IA-32 and x64.

Parameters
IndexThe 32-bit value to load into EAX prior to invoking the CPUID instruction.
EaxThe pointer to the 32-bit EAX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EbxThe pointer to the 32-bit EBX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EcxThe pointer to the 32-bit ECX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EdxThe pointer to the 32-bit EDX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
Returns
Index.

Definition at line 61 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmCpuidEx()

UINT32 EFIAPI UnitTestHostBaseLibAsmCpuidEx ( IN UINT32  Index,
IN UINT32  SubIndex,
OUT UINT32 *Eax  OPTIONAL,
OUT UINT32 *Ebx  OPTIONAL,
OUT UINT32 *Ecx  OPTIONAL,
OUT UINT32 *Edx  OPTIONAL 
)

Retrieves CPUID information using an extended leaf identifier.

Executes the CPUID instruction with EAX set to the value specified by Index and ECX set to the value specified by SubIndex. This function always returns Index. This function is only available on IA-32 and x64.

If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.

Parameters
IndexThe 32-bit value to load into EAX prior to invoking the CPUID instruction.
SubIndexThe 32-bit value to load into ECX prior to invoking the CPUID instruction.
EaxThe pointer to the 32-bit EAX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EbxThe pointer to the 32-bit EBX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EcxThe pointer to the 32-bit ECX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
EdxThe pointer to the 32-bit EDX value returned by the CPUID instruction. This is an optional parameter that may be NULL.
Returns
Index.

Definition at line 122 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmDisableCache()

VOID EFIAPI UnitTestHostBaseLibAsmDisableCache ( VOID  )

Set CD bit and clear NW bit of CR0 followed by a WBINVD.

Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0, and executing a WBINVD instruction. This function is only available on IA-32 and x64.

Definition at line 159 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmDisablePaging32()

VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging32 ( IN SWITCH_STACK_ENTRY_POINT  EntryPoint,
IN VOID *Context1  OPTIONAL,
IN VOID *Context2  OPTIONAL,
IN VOID NewStack 
)

Disables the 32-bit paging mode on the CPU.

Disables the 32-bit paging mode on the CPU and returns to 32-bit protected mode. This function assumes the current execution mode is 32-paged protected mode. This function is only available on IA-32. After the 32-bit paging mode is disabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and may be NULL. The function EntryPoint must never return.

If the current execution mode is not 32-bit paged mode, then ASSERT(). If EntryPoint is NULL, then ASSERT(). If NewStack is NULL, then ASSERT().

There are a number of constraints that must be followed before calling this function: 1) Interrupts must be disabled. 2) The caller must be in 32-bit paged mode. 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode. 4) CR3 must point to valid page tables that guarantee that the pages for this function and the stack are identity mapped.

Parameters
EntryPointA pointer to function to call with the new stack after paging is disabled.
Context1A pointer to the context to pass into the EntryPoint function as the first parameter after paging is disabled.
Context2A pointer to the context to pass into the EntryPoint function as the second parameter after paging is disabled.
NewStackA pointer to the new stack to use for the EntryPoint function after paging is disabled.

Definition at line 1178 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmDisablePaging64()

VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging64 ( IN UINT16  Cs,
IN UINT32  EntryPoint,
IN UINT32 Context1  OPTIONAL,
IN UINT32 Context2  OPTIONAL,
IN UINT32  NewStack 
)

Disables the 64-bit paging mode on the CPU.

Disables the 64-bit paging mode on the CPU and returns to 32-bit protected mode. This function assumes the current execution mode is 64-paging mode. This function is only available on x64. After the 64-bit paging mode is disabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and may be 0. The function EntryPoint must never return.

If the current execution mode is not 64-bit paged mode, then ASSERT(). If EntryPoint is 0, then ASSERT(). If NewStack is 0, then ASSERT().

Parameters
CsThe 16-bit selector to load in the CS before EntryPoint is called. The descriptor in the GDT that this selector references must be setup for 32-bit protected mode.
EntryPointThe 64-bit virtual address of the function to call with the new stack after paging is disabled.
Context1The 64-bit virtual address of the context to pass into the EntryPoint function as the first parameter after paging is disabled.
Context2The 64-bit virtual address of the context to pass into the EntryPoint function as the second parameter after paging is disabled.
NewStackThe 64-bit virtual address of the new stack to use for the EntryPoint function after paging is disabled.

Definition at line 1268 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmEnableCache()

VOID EFIAPI UnitTestHostBaseLibAsmEnableCache ( VOID  )

Perform a WBINVD and clear both the CD and NW bits of CR0.

Enables the caches by executing a WBINVD instruction and then clear both the CD and NW bits of CR0 to 0. This function is only available on IA-32 and x64.

Definition at line 174 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmEnablePaging32()

VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging32 ( IN SWITCH_STACK_ENTRY_POINT  EntryPoint,
IN VOID *Context1  OPTIONAL,
IN VOID *Context2  OPTIONAL,
IN VOID NewStack 
)

Enables the 32-bit paging mode on the CPU.

Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables must be properly initialized prior to calling this service. This function assumes the current execution mode is 32-bit protected mode. This function is only available on IA-32. After the 32-bit paging mode is enabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and may be NULL. The function EntryPoint must never return.

If the current execution mode is not 32-bit protected mode, then ASSERT(). If EntryPoint is NULL, then ASSERT(). If NewStack is NULL, then ASSERT().

There are a number of constraints that must be followed before calling this function: 1) Interrupts must be disabled. 2) The caller must be in 32-bit protected mode with flat descriptors. This means all descriptors must have a base of 0 and a limit of 4GB. 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat descriptors. 4) CR3 must point to valid page tables that will be used once the transition is complete, and those page tables must guarantee that the pages for this function and the stack are identity mapped.

Parameters
EntryPointA pointer to function to call with the new stack after paging is enabled.
Context1A pointer to the context to pass into the EntryPoint function as the first parameter after paging is enabled.
Context2A pointer to the context to pass into the EntryPoint function as the second parameter after paging is enabled.
NewStackA pointer to the new stack to use for the EntryPoint function after paging is enabled.

Definition at line 1132 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmEnablePaging64()

VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging64 ( IN UINT16  Cs,
IN UINT64  EntryPoint,
IN UINT64 Context1  OPTIONAL,
IN UINT64 Context2  OPTIONAL,
IN UINT64  NewStack 
)

Enables the 64-bit paging mode on the CPU.

Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables must be properly initialized prior to calling this service. This function assumes the current execution mode is 32-bit protected mode with flat descriptors. This function is only available on IA-32. After the 64-bit paging mode is enabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and may be 0. The function EntryPoint must never return.

If the current execution mode is not 32-bit protected mode with flat descriptors, then ASSERT(). If EntryPoint is 0, then ASSERT(). If NewStack is 0, then ASSERT().

Parameters
CsThe 16-bit selector to load in the CS before EntryPoint is called. The descriptor in the GDT that this selector references must be setup for long mode.
EntryPointThe 64-bit virtual address of the function to call with the new stack after paging is enabled.
Context1The 64-bit virtual address of the context to pass into the EntryPoint function as the first parameter after paging is enabled.
Context2The 64-bit virtual address of the context to pass into the EntryPoint function as the second parameter after paging is enabled.
NewStackThe 64-bit virtual address of the new stack to use for the EntryPoint function after paging is enabled.

Definition at line 1222 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmFlushCacheLine()

VOID *EFIAPI UnitTestHostBaseLibAsmFlushCacheLine ( IN VOID LinearAddress)

Flushes a cache line from all the instruction and data caches within the coherency domain of the CPU.

Flushed the cache line specified by LinearAddress, and returns LinearAddress. This function is only available on IA-32 and x64.

Parameters
LinearAddressThe address of the cache line to flush. If the CPU is in a physical addressing mode, then LinearAddress is a physical address. If the CPU is in a virtual addressing mode, then LinearAddress is a virtual address.
Returns
LinearAddress.

Definition at line 1086 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmGetThunk16Properties()

VOID EFIAPI UnitTestHostBaseLibAsmGetThunk16Properties ( OUT UINT32 RealModeBufferSize,
OUT UINT32 ExtraStackSize 
)

Retrieves the properties for 16-bit thunk functions.

Computes the size of the buffer and stack below 1MB required to use the AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This buffer size is returned in RealModeBufferSize, and the stack size is returned in ExtraStackSize. If parameters are passed to the 16-bit real mode code, then the actual minimum stack size is ExtraStackSize plus the maximum number of bytes that need to be passed to the 16-bit real mode code.

If RealModeBufferSize is NULL, then ASSERT(). If ExtraStackSize is NULL, then ASSERT().

Parameters
RealModeBufferSizeA pointer to the size of the buffer below 1MB required to use the 16-bit thunk functions.
ExtraStackSizeA pointer to the extra size of stack below 1MB that the 16-bit thunk functions require for temporary storage in the transition to and from 16-bit real mode.

Definition at line 1305 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmInvd()

VOID EFIAPI UnitTestHostBaseLibAsmInvd ( VOID  )

Executes a INVD instruction.

Executes a INVD instruction. This function is only available on IA-32 and x64.

Definition at line 1063 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmLfence()

VOID EFIAPI UnitTestHostBaseLibAsmLfence ( VOID  )

Performs a serializing operation on all load-from-memory instructions that were issued prior the AsmLfence function.

Executes a LFENCE instruction. This function is only available on IA-32 and x64.

Definition at line 1448 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmMonitor()

UINTN EFIAPI UnitTestHostBaseLibAsmMonitor ( IN UINTN  Eax,
IN UINTN  Ecx,
IN UINTN  Edx 
)

Sets up a monitor buffer that is used by AsmMwait().

Executes a MONITOR instruction with the register state specified by Eax, Ecx and Edx. Returns Eax. This function is only available on IA-32 and x64.

Parameters
EaxThe value to load into EAX or RAX before executing the MONITOR instruction.
EcxThe value to load into ECX or RCX before executing the MONITOR instruction.
EdxThe value to load into EDX or RDX before executing the MONITOR instruction.
Returns
Eax

Definition at line 1006 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmMwait()

UINTN EFIAPI UnitTestHostBaseLibAsmMwait ( IN UINTN  Eax,
IN UINTN  Ecx 
)

Executes an MWAIT instruction.

Executes an MWAIT instruction with the register state specified by Eax and Ecx. Returns Eax. This function is only available on IA-32 and x64.

Parameters
EaxThe value to load into EAX or RAX before executing the MONITOR instruction.
EcxThe value to load into ECX or RCX before executing the MONITOR instruction.
Returns
Eax

Definition at line 1031 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmPrepareAndThunk16()

VOID EFIAPI UnitTestHostBaseLibAsmPrepareAndThunk16 ( IN OUT THUNK_CONTEXT *  ThunkContext)

Prepares all structures and code for a 16-bit real mode thunk, transfers control to a 16-bit real mode entry point, and returns the results.

Prepares all structures and code for a 16-bit real mode thunk, transfers control to a 16-bit real mode entry point, and returns the results. If the caller only need to perform a single 16-bit real mode thunk, then this service should be used. If the caller intends to make more than one 16-bit real mode thunk, then it is more efficient if AsmPrepareThunk16() is called once and AsmThunk16() can be called for each 16-bit real mode thunk.

This interface is limited to be used in either physical mode or virtual modes with paging enabled where the virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.

See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.

Parameters
ThunkContextA pointer to the context structure that describes the 16-bit real mode code to call.

Definition at line 1419 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmPrepareThunk16()

VOID EFIAPI UnitTestHostBaseLibAsmPrepareThunk16 ( IN OUT THUNK_CONTEXT *  ThunkContext)

Prepares all structures a code required to use AsmThunk16().

Prepares all structures and code required to use AsmThunk16().

This interface is limited to be used in either physical mode or virtual modes with paging enabled where the virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.

If ThunkContext is NULL, then ASSERT().

Parameters
ThunkContextA pointer to the context structure that describes the 16-bit real mode code to call.

Definition at line 1330 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadCr0()

UINTN EFIAPI UnitTestHostBaseLibAsmReadCr0 ( VOID  )

Reads the current value of the Control Register 0 (CR0).

Reads and returns the current value of CR0. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of the Control Register 0 (CR0).

Definition at line 258 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadCr2()

UINTN EFIAPI UnitTestHostBaseLibAsmReadCr2 ( VOID  )

Reads the current value of the Control Register 2 (CR2).

Reads and returns the current value of CR2. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of the Control Register 2 (CR2).

Definition at line 277 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadCr3()

UINTN EFIAPI UnitTestHostBaseLibAsmReadCr3 ( VOID  )

Reads the current value of the Control Register 3 (CR3).

Reads and returns the current value of CR3. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of the Control Register 3 (CR3).

Definition at line 296 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadCr4()

UINTN EFIAPI UnitTestHostBaseLibAsmReadCr4 ( VOID  )

Reads the current value of the Control Register 4 (CR4).

Reads and returns the current value of CR4. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of the Control Register 4 (CR4).

Definition at line 315 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadCs()

UINT16 EFIAPI UnitTestHostBaseLibAsmReadCs ( VOID  )

Reads the current value of Code Segment Register (CS).

Reads and returns the current value of CS. This function is only available on IA-32 and x64.

Returns
The current value of CS.

Definition at line 737 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDr0()

UINTN EFIAPI UnitTestHostBaseLibAsmReadDr0 ( VOID  )

Reads the current value of Debug Register 0 (DR0).

Reads and returns the current value of DR0. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 0 (DR0).

Definition at line 418 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDr1()

UINTN EFIAPI UnitTestHostBaseLibAsmReadDr1 ( VOID  )

Reads the current value of Debug Register 1 (DR1).

Reads and returns the current value of DR1. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 1 (DR1).

Definition at line 437 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDr2()

UINTN EFIAPI UnitTestHostBaseLibAsmReadDr2 ( VOID  )

Reads the current value of Debug Register 2 (DR2).

Reads and returns the current value of DR2. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 2 (DR2).

Definition at line 456 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDr3()

UINTN EFIAPI UnitTestHostBaseLibAsmReadDr3 ( VOID  )

Reads the current value of Debug Register 3 (DR3).

Reads and returns the current value of DR3. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 3 (DR3).

Definition at line 475 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDr4()

UINTN EFIAPI UnitTestHostBaseLibAsmReadDr4 ( VOID  )

Reads the current value of Debug Register 4 (DR4).

Reads and returns the current value of DR4. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 4 (DR4).

Definition at line 494 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDr5()

UINTN EFIAPI UnitTestHostBaseLibAsmReadDr5 ( VOID  )

Reads the current value of Debug Register 5 (DR5).

Reads and returns the current value of DR5. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 5 (DR5).

Definition at line 513 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDr6()

UINTN EFIAPI UnitTestHostBaseLibAsmReadDr6 ( VOID  )

Reads the current value of Debug Register 6 (DR6).

Reads and returns the current value of DR6. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 6 (DR6).

Definition at line 532 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDr7()

UINTN EFIAPI UnitTestHostBaseLibAsmReadDr7 ( VOID  )

Reads the current value of Debug Register 7 (DR7).

Reads and returns the current value of DR7. This function is only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on x64.

Returns
The value of Debug Register 7 (DR7).

Definition at line 551 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadDs()

UINT16 EFIAPI UnitTestHostBaseLibAsmReadDs ( VOID  )

Reads the current value of Data Segment Register (DS).

Reads and returns the current value of DS. This function is only available on IA-32 and x64.

Returns
The current value of DS.

Definition at line 755 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadEs()

UINT16 EFIAPI UnitTestHostBaseLibAsmReadEs ( VOID  )

Reads the current value of Extra Segment Register (ES).

Reads and returns the current value of ES. This function is only available on IA-32 and x64.

Returns
The current value of ES.

Definition at line 773 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadFs()

UINT16 EFIAPI UnitTestHostBaseLibAsmReadFs ( VOID  )

Reads the current value of FS Data Segment Register (FS).

Reads and returns the current value of FS. This function is only available on IA-32 and x64.

Returns
The current value of FS.

Definition at line 791 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadGdtr()

VOID EFIAPI UnitTestHostBaseLibAsmReadGdtr ( OUT IA32_DESCRIPTOR *  Gdtr)

Reads the current Global Descriptor Table Register(GDTR) descriptor.

Reads and returns the current GDTR descriptor and returns it in Gdtr. This function is only available on IA-32 and x64.

If Gdtr is NULL, then ASSERT().

Parameters
GdtrThe pointer to a GDTR descriptor.

Definition at line 865 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadGs()

UINT16 EFIAPI UnitTestHostBaseLibAsmReadGs ( VOID  )

Reads the current value of GS Data Segment Register (GS).

Reads and returns the current value of GS. This function is only available on IA-32 and x64.

Returns
The current value of GS.

Definition at line 809 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadIdtr()

VOID EFIAPI UnitTestHostBaseLibAsmReadIdtr ( OUT IA32_DESCRIPTOR *  Idtr)

Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.

Reads and returns the current IDTR descriptor and returns it in Idtr. This function is only available on IA-32 and x64.

If Idtr is NULL, then ASSERT().

Parameters
IdtrThe pointer to a IDTR descriptor.

Definition at line 905 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadLdtr()

UINT16 EFIAPI UnitTestHostBaseLibAsmReadLdtr ( VOID  )

Reads the current Local Descriptor Table Register(LDTR) selector.

Reads and returns the current 16-bit LDTR descriptor value. This function is only available on IA-32 and x64.

Returns
The current selector of LDT.

Definition at line 943 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadMsr64()

UINT64 EFIAPI UnitTestHostBaseLibAsmReadMsr64 ( IN UINT32  Index)

Returns a 64-bit Machine Specific Register(MSR).

Reads and returns the 64-bit MSR specified by Index. No parameter checking is performed on Index, and some Index values may cause CPU exceptions. The caller must either guarantee that Index is valid, or the caller must set up exception handlers to catch the exceptions. This function is only available on IA-32 and x64.

Parameters
IndexThe 32-bit MSR index to read.
Returns
The value of the MSR identified by Index.

Definition at line 196 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadPmc()

UINT64 EFIAPI UnitTestHostBaseLibAsmReadPmc ( IN UINT32  Index)

Reads the current value of a Performance Counter (PMC).

Reads and returns the current value of performance counter specified by Index. This function is only available on IA-32 and x64.

Parameters
IndexThe 32-bit Performance Counter index to read.
Returns
The value of the PMC specified by Index.

Definition at line 981 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadSs()

UINT16 EFIAPI UnitTestHostBaseLibAsmReadSs ( VOID  )

Reads the current value of Stack Segment Register (SS).

Reads and returns the current value of SS. This function is only available on IA-32 and x64.

Returns
The current value of SS.

Definition at line 827 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmReadTr()

UINT16 EFIAPI UnitTestHostBaseLibAsmReadTr ( VOID  )

Reads the current value of Task Register (TR).

Reads and returns the current value of TR. This function is only available on IA-32 and x64.

Returns
The current value of TR.

Definition at line 845 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmThunk16()

VOID EFIAPI UnitTestHostBaseLibAsmThunk16 ( IN OUT THUNK_CONTEXT *  ThunkContext)

Transfers control to a 16-bit real mode entry point and returns the results.

Transfers control to a 16-bit real mode entry point and returns the results. AsmPrepareThunk16() must be called with ThunkContext before this function is used. This function must be called with interrupts disabled.

The register state from the RealModeState field of ThunkContext is restored just prior to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState, which is used to set the interrupt state when a 16-bit real mode entry point is called. Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState. The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function. The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction, so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry point must exit with a RETF instruction. The register state is captured into RealModeState immediately after the RETF instruction is executed.

If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.

If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode. This includes the base vectors, the interrupt masks, and the edge/level trigger mode.

If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.

If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to disable the A20 mask.

If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.

If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.

If ThunkContext is NULL, then ASSERT(). If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT(). If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in ThunkAttributes, then ASSERT().

This interface is limited to be used in either physical mode or virtual modes with paging enabled where the virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.

Parameters
ThunkContextA pointer to the context structure that describes the 16-bit real mode code to call.

Definition at line 1391 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWbinvd()

VOID EFIAPI UnitTestHostBaseLibAsmWbinvd ( VOID  )

Executes a WBINVD instruction.

Executes a WBINVD instruction. This function is only available on IA-32 and x64.

Definition at line 1048 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteCr0()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr0 ( UINTN  Cr0)

Writes a value to Control Register 0 (CR0).

Writes and returns a new value to CR0. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Cr0The value to write to CR0.
Returns
The value written to CR0.

Definition at line 335 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteCr2()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr2 ( UINTN  Cr2)

Writes a value to Control Register 2 (CR2).

Writes and returns a new value to CR2. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Cr2The value to write to CR2.
Returns
The value written to CR2.

Definition at line 356 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteCr3()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr3 ( UINTN  Cr3)

Writes a value to Control Register 3 (CR3).

Writes and returns a new value to CR3. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Cr3The value to write to CR3.
Returns
The value written to CR3.

Definition at line 377 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteCr4()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr4 ( UINTN  Cr4)

Writes a value to Control Register 4 (CR4).

Writes and returns a new value to CR4. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Cr4The value to write to CR4.
Returns
The value written to CR4.

Definition at line 398 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteDr0()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr0 ( UINTN  Dr0)

Writes a value to Debug Register 0 (DR0).

Writes and returns a new value to DR0. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr0The value to write to Dr0.
Returns
The value written to Debug Register 0 (DR0).

Definition at line 571 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteDr1()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr1 ( UINTN  Dr1)

Writes a value to Debug Register 1 (DR1).

Writes and returns a new value to DR1. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr1The value to write to Dr1.
Returns
The value written to Debug Register 1 (DR1).

Definition at line 592 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteDr2()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr2 ( UINTN  Dr2)

Writes a value to Debug Register 2 (DR2).

Writes and returns a new value to DR2. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr2The value to write to Dr2.
Returns
The value written to Debug Register 2 (DR2).

Definition at line 613 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteDr3()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr3 ( UINTN  Dr3)

Writes a value to Debug Register 3 (DR3).

Writes and returns a new value to DR3. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr3The value to write to Dr3.
Returns
The value written to Debug Register 3 (DR3).

Definition at line 634 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteDr4()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr4 ( UINTN  Dr4)

Writes a value to Debug Register 4 (DR4).

Writes and returns a new value to DR4. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr4The value to write to Dr4.
Returns
The value written to Debug Register 4 (DR4).

Definition at line 655 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteDr5()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr5 ( UINTN  Dr5)

Writes a value to Debug Register 5 (DR5).

Writes and returns a new value to DR5. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr5The value to write to Dr5.
Returns
The value written to Debug Register 5 (DR5).

Definition at line 676 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteDr6()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr6 ( UINTN  Dr6)

Writes a value to Debug Register 6 (DR6).

Writes and returns a new value to DR6. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr6The value to write to Dr6.
Returns
The value written to Debug Register 6 (DR6).

Definition at line 697 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteDr7()

UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr7 ( UINTN  Dr7)

Writes a value to Debug Register 7 (DR7).

Writes and returns a new value to DR7. This function is only available on IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.

Parameters
Dr7The value to write to Dr7.
Returns
The value written to Debug Register 7 (DR7).

Definition at line 718 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteGdtr()

VOID EFIAPI UnitTestHostBaseLibAsmWriteGdtr ( IN CONST IA32_DESCRIPTOR *  Gdtr)

Writes the current Global Descriptor Table Register (GDTR) descriptor.

Writes and the current GDTR descriptor specified by Gdtr. This function is only available on IA-32 and x64.

If Gdtr is NULL, then ASSERT().

Parameters
GdtrThe pointer to a GDTR descriptor.

Definition at line 885 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteIdtr()

VOID EFIAPI UnitTestHostBaseLibAsmWriteIdtr ( IN CONST IA32_DESCRIPTOR *  Idtr)

Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.

Writes the current IDTR descriptor and returns it in Idtr. This function is only available on IA-32 and x64.

If Idtr is NULL, then ASSERT().

Parameters
IdtrThe pointer to a IDTR descriptor.

Definition at line 925 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteLdtr()

VOID EFIAPI UnitTestHostBaseLibAsmWriteLdtr ( IN UINT16  Ldtr)

Writes the current Local Descriptor Table Register (LDTR) selector.

Writes and the current LDTR descriptor specified by Ldtr. This function is only available on IA-32 and x64.

Parameters
Ldtr16-bit LDTR selector value.

Definition at line 961 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteMsr64()

UINT64 EFIAPI UnitTestHostBaseLibAsmWriteMsr64 ( IN UINT32  Index,
IN UINT64  Value 
)

Writes a 64-bit value to a Machine Specific Register(MSR), and returns the value.

Writes the 64-bit value specified by Value to the MSR specified by Index. The 64-bit value written to the MSR is returned. No parameter checking is performed on Index or Value, and some of these may cause CPU exceptions. The caller must either guarantee that Index and Value are valid, or the caller must establish proper exception handlers. This function is only available on IA-32 and x64.

Parameters
IndexThe 32-bit MSR index to write.
ValueThe 64-bit value to write to the MSR.
Returns
Value

Definition at line 230 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibAsmWriteTr()

VOID EFIAPI UnitTestHostBaseLibAsmWriteTr ( IN UINT16  Selector)

Load given selector into TR register.

Parameters
[in]SelectorTask segment selector

Definition at line 1432 of file X86UnitTestHost.c.

◆ UnitTestHostBaseLibPatchInstructionX86()

VOID EFIAPI UnitTestHostBaseLibPatchInstructionX86 ( OUT X86_ASSEMBLY_PATCH_LABEL *  InstructionEnd,
IN UINT64  PatchValue,
IN UINTN  ValueSize 
)

Patch the immediate operand of an IA32 or X64 instruction such that the byte, word, dword or qword operand is encoded at the end of the instruction's binary representation.

This function should be used to update object code that was compiled with NASM from assembly source code. Example:

NASM source code:

  mov     eax, strict dword 0 ; the imm32 zero operand will be patched

ASM_PFX(gPatchCr3): mov cr3, eax

C source code:

X86_ASSEMBLY_PATCH_LABEL gPatchCr3; PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);

Parameters
[out]InstructionEndPointer right past the instruction to patch. The immediate operand to patch is expected to comprise the trailing bytes of the instruction. If InstructionEnd is closer to address 0 than ValueSize permits, then ASSERT().
[in]PatchValueThe constant to write to the immediate operand. The caller is responsible for ensuring that PatchValue can be represented in the byte, word, dword or qword operand (as indicated through ValueSize); otherwise ASSERT().
[in]ValueSizeThe size of the operand in bytes; must be 1, 2, 4, or 8. ASSERT() otherwise.

Definition at line 1490 of file X86UnitTestHost.c.

Variable Documentation

◆ gUnitTestHostBaseLib

UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib
Initial value:
= {
}
STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86

Structure of hook functions for BaseLib functions that can not be used from a host application. A simple emulation of these function is provided by default. A specific unit test can provide its own implementation for any of these functions.

Definition at line 2986 of file X86UnitTestHost.c.

◆ mUnitTestHostBaseLibCommon

STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
Initial value:
= {
}
VOID EFIAPI UnitTestHostBaseLibEnableDisableInterrupts(VOID)
Definition: UnitTestHost.c:49
VOID EFIAPI UnitTestHostBaseLibEnableInterrupts(VOID)
Definition: UnitTestHost.c:22
BOOLEAN EFIAPI UnitTestHostBaseLibGetInterruptState(VOID)
Definition: UnitTestHost.c:72
VOID EFIAPI UnitTestHostBaseLibDisableInterrupts(VOID)
Definition: UnitTestHost.c:35

Common services

Definition at line 2907 of file X86UnitTestHost.c.

◆ mUnitTestHostBaseLibCr

STATIC UINTN mUnitTestHostBaseLibCr[5]

Definition at line 28 of file X86UnitTestHost.c.

◆ mUnitTestHostBaseLibDr

STATIC UINTN mUnitTestHostBaseLibDr[8]

Definition at line 29 of file X86UnitTestHost.c.

◆ mUnitTestHostBaseLibGdtr

STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr

Definition at line 31 of file X86UnitTestHost.c.

◆ mUnitTestHostBaseLibIdtr

STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr

Definition at line 32 of file X86UnitTestHost.c.

◆ mUnitTestHostBaseLibMsr

STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000]

Module global variables for simple system emulation of MSRs, CRx, DRx, GDTR, IDTR, and Segment Selectors.

Definition at line 27 of file X86UnitTestHost.c.

◆ mUnitTestHostBaseLibSegment

STATIC UINT16 mUnitTestHostBaseLibSegment[8]

Definition at line 30 of file X86UnitTestHost.c.

◆ mUnitTestHostBaseLibX86

STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86

IA32/X64 services

Definition at line 2917 of file X86UnitTestHost.c.