TianoCore EDK2 master
X86UnitTestHost.c
Go to the documentation of this file.
1
9#include "UnitTestHost.h"
10
14#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0
15#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1
16#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2
17#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3
18#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4
19#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5
20#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6
21#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7
22
28STATIC UINTN mUnitTestHostBaseLibCr[5];
29STATIC UINTN mUnitTestHostBaseLibDr[8];
30STATIC UINT16 mUnitTestHostBaseLibSegment[8];
31STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr;
32STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr;
33
59UINT32
60EFIAPI
62 IN UINT32 Index,
63 OUT UINT32 *Eax OPTIONAL,
64 OUT UINT32 *Ebx OPTIONAL,
65 OUT UINT32 *Ecx OPTIONAL,
66 OUT UINT32 *Edx OPTIONAL
67 )
68{
69 if (Eax != NULL) {
70 *Eax = 0;
71 }
72
73 if (Ebx != NULL) {
74 *Ebx = 0;
75 }
76
77 if (Ecx != NULL) {
78 *Ecx = 0;
79 }
80
81 if (Edx != NULL) {
82 *Edx = 0;
83 }
84
85 return Index;
86}
87
120UINT32
121EFIAPI
123 IN UINT32 Index,
124 IN UINT32 SubIndex,
125 OUT UINT32 *Eax OPTIONAL,
126 OUT UINT32 *Ebx OPTIONAL,
127 OUT UINT32 *Ecx OPTIONAL,
128 OUT UINT32 *Edx OPTIONAL
129 )
130{
131 if (Eax != NULL) {
132 *Eax = 0;
133 }
134
135 if (Ebx != NULL) {
136 *Ebx = 0;
137 }
138
139 if (Ecx != NULL) {
140 *Ecx = 0;
141 }
142
143 if (Edx != NULL) {
144 *Edx = 0;
145 }
146
147 return Index;
148}
149
157VOID
158EFIAPI
160 VOID
161 )
162{
163}
164
172VOID
173EFIAPI
175 VOID
176 )
177{
178}
179
194UINT64
195EFIAPI
197 IN UINT32 Index
198 )
199{
200 if (Index < 0x1000) {
201 return mUnitTestHostBaseLibMsr[0][Index];
202 }
203
204 if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
205 return mUnitTestHostBaseLibMsr[1][Index];
206 }
207
208 return 0;
209}
210
228UINT64
229EFIAPI
231 IN UINT32 Index,
232 IN UINT64 Value
233 )
234{
235 if (Index < 0x1000) {
236 mUnitTestHostBaseLibMsr[0][Index] = Value;
237 }
238
239 if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
240 mUnitTestHostBaseLibMsr[1][Index - 0xC00000000] = Value;
241 }
242
243 return Value;
244}
245
256UINTN
257EFIAPI
259 VOID
260 )
261{
262 return mUnitTestHostBaseLibCr[0];
263}
264
275UINTN
276EFIAPI
278 VOID
279 )
280{
281 return mUnitTestHostBaseLibCr[2];
282}
283
294UINTN
295EFIAPI
297 VOID
298 )
299{
300 return mUnitTestHostBaseLibCr[3];
301}
302
313UINTN
314EFIAPI
316 VOID
317 )
318{
319 return mUnitTestHostBaseLibCr[4];
320}
321
333UINTN
334EFIAPI
336 UINTN Cr0
337 )
338{
339 mUnitTestHostBaseLibCr[0] = Cr0;
340 return Cr0;
341}
342
354UINTN
355EFIAPI
357 UINTN Cr2
358 )
359{
360 mUnitTestHostBaseLibCr[2] = Cr2;
361 return Cr2;
362}
363
375UINTN
376EFIAPI
378 UINTN Cr3
379 )
380{
381 mUnitTestHostBaseLibCr[3] = Cr3;
382 return Cr3;
383}
384
396UINTN
397EFIAPI
399 UINTN Cr4
400 )
401{
402 mUnitTestHostBaseLibCr[4] = Cr4;
403 return Cr4;
404}
405
416UINTN
417EFIAPI
419 VOID
420 )
421{
422 return mUnitTestHostBaseLibDr[0];
423}
424
435UINTN
436EFIAPI
438 VOID
439 )
440{
441 return mUnitTestHostBaseLibDr[1];
442}
443
454UINTN
455EFIAPI
457 VOID
458 )
459{
460 return mUnitTestHostBaseLibDr[2];
461}
462
473UINTN
474EFIAPI
476 VOID
477 )
478{
479 return mUnitTestHostBaseLibDr[3];
480}
481
492UINTN
493EFIAPI
495 VOID
496 )
497{
498 return mUnitTestHostBaseLibDr[4];
499}
500
511UINTN
512EFIAPI
514 VOID
515 )
516{
517 return mUnitTestHostBaseLibDr[5];
518}
519
530UINTN
531EFIAPI
533 VOID
534 )
535{
536 return mUnitTestHostBaseLibDr[6];
537}
538
549UINTN
550EFIAPI
552 VOID
553 )
554{
555 return mUnitTestHostBaseLibDr[7];
556}
557
569UINTN
570EFIAPI
572 UINTN Dr0
573 )
574{
575 mUnitTestHostBaseLibDr[0] = Dr0;
576 return Dr0;
577}
578
590UINTN
591EFIAPI
593 UINTN Dr1
594 )
595{
596 mUnitTestHostBaseLibDr[1] = Dr1;
597 return Dr1;
598}
599
611UINTN
612EFIAPI
614 UINTN Dr2
615 )
616{
617 mUnitTestHostBaseLibDr[2] = Dr2;
618 return Dr2;
619}
620
632UINTN
633EFIAPI
635 UINTN Dr3
636 )
637{
638 mUnitTestHostBaseLibDr[3] = Dr3;
639 return Dr3;
640}
641
653UINTN
654EFIAPI
656 UINTN Dr4
657 )
658{
659 mUnitTestHostBaseLibDr[4] = Dr4;
660 return Dr4;
661}
662
674UINTN
675EFIAPI
677 UINTN Dr5
678 )
679{
680 mUnitTestHostBaseLibDr[5] = Dr5;
681 return Dr5;
682}
683
695UINTN
696EFIAPI
698 UINTN Dr6
699 )
700{
701 mUnitTestHostBaseLibDr[6] = Dr6;
702 return Dr6;
703}
704
716UINTN
717EFIAPI
719 UINTN Dr7
720 )
721{
722 mUnitTestHostBaseLibDr[7] = Dr7;
723 return Dr7;
724}
725
735UINT16
736EFIAPI
738 VOID
739 )
740{
741 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS];
742}
743
753UINT16
754EFIAPI
756 VOID
757 )
758{
759 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS];
760}
761
771UINT16
772EFIAPI
774 VOID
775 )
776{
777 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES];
778}
779
789UINT16
790EFIAPI
792 VOID
793 )
794{
795 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS];
796}
797
807UINT16
808EFIAPI
810 VOID
811 )
812{
813 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS];
814}
815
825UINT16
826EFIAPI
828 VOID
829 )
830{
831 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS];
832}
833
843UINT16
844EFIAPI
846 VOID
847 )
848{
849 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR];
850}
851
863VOID
864EFIAPI
866 OUT IA32_DESCRIPTOR *Gdtr
867 )
868{
869 Gdtr = &mUnitTestHostBaseLibGdtr;
870}
871
883VOID
884EFIAPI
886 IN CONST IA32_DESCRIPTOR *Gdtr
887 )
888{
889 CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr, sizeof (IA32_DESCRIPTOR));
890}
891
903VOID
904EFIAPI
906 OUT IA32_DESCRIPTOR *Idtr
907 )
908{
909 Idtr = &mUnitTestHostBaseLibIdtr;
910}
911
923VOID
924EFIAPI
926 IN CONST IA32_DESCRIPTOR *Idtr
927 )
928{
929 CopyMem (&mUnitTestHostBaseLibIdtr, Idtr, sizeof (IA32_DESCRIPTOR));
930}
931
941UINT16
942EFIAPI
944 VOID
945 )
946{
947 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR];
948}
949
959VOID
960EFIAPI
962 IN UINT16 Ldtr
963 )
964{
965 mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;
966}
967
979UINT64
980EFIAPI
982 IN UINT32 Index
983 )
984{
985 return 0;
986}
987
1004UINTN
1005EFIAPI
1007 IN UINTN Eax,
1008 IN UINTN Ecx,
1009 IN UINTN Edx
1010 )
1011{
1012 return Eax;
1013}
1014
1029UINTN
1030EFIAPI
1032 IN UINTN Eax,
1033 IN UINTN Ecx
1034 )
1035{
1036 return Eax;
1037}
1038
1046VOID
1047EFIAPI
1049 VOID
1050 )
1051{
1052}
1053
1061VOID
1062EFIAPI
1064 VOID
1065 )
1066{
1067}
1068
1084VOID *
1085EFIAPI
1087 IN VOID *LinearAddress
1088 )
1089{
1090 return LinearAddress;
1091}
1092
1130VOID
1131EFIAPI
1133 IN SWITCH_STACK_ENTRY_POINT EntryPoint,
1134 IN VOID *Context1 OPTIONAL,
1135 IN VOID *Context2 OPTIONAL,
1136 IN VOID *NewStack
1137 )
1138{
1139 EntryPoint (Context1, Context2);
1140}
1141
1176VOID
1177EFIAPI
1179 IN SWITCH_STACK_ENTRY_POINT EntryPoint,
1180 IN VOID *Context1 OPTIONAL,
1181 IN VOID *Context2 OPTIONAL,
1182 IN VOID *NewStack
1183 )
1184{
1185 EntryPoint (Context1, Context2);
1186}
1187
1220VOID
1221EFIAPI
1223 IN UINT16 Cs,
1224 IN UINT64 EntryPoint,
1225 IN UINT64 Context1 OPTIONAL,
1226 IN UINT64 Context2 OPTIONAL,
1227 IN UINT64 NewStack
1228 )
1229{
1230 SWITCH_STACK_ENTRY_POINT NewEntryPoint;
1231
1232 NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);
1233 NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);
1234}
1235
1266VOID
1267EFIAPI
1269 IN UINT16 Cs,
1270 IN UINT32 EntryPoint,
1271 IN UINT32 Context1 OPTIONAL,
1272 IN UINT32 Context2 OPTIONAL,
1273 IN UINT32 NewStack
1274 )
1275{
1276 SWITCH_STACK_ENTRY_POINT NewEntryPoint;
1277
1278 NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);
1279 NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);
1280}
1281
1303VOID
1304EFIAPI
1306 OUT UINT32 *RealModeBufferSize,
1307 OUT UINT32 *ExtraStackSize
1308 )
1309{
1310 *RealModeBufferSize = 0;
1311 *ExtraStackSize = 0;
1312}
1313
1328VOID
1329EFIAPI
1331 IN OUT THUNK_CONTEXT *ThunkContext
1332 )
1333{
1334}
1335
1389VOID
1390EFIAPI
1392 IN OUT THUNK_CONTEXT *ThunkContext
1393 )
1394{
1395}
1396
1417VOID
1418EFIAPI
1420 IN OUT THUNK_CONTEXT *ThunkContext
1421 )
1422{
1423}
1424
1430VOID
1431EFIAPI
1433 IN UINT16 Selector
1434 )
1435{
1436 mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;
1437}
1438
1446VOID
1447EFIAPI
1449 VOID
1450 )
1451{
1452}
1453
1488VOID
1489EFIAPI
1491 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
1492 IN UINT64 PatchValue,
1493 IN UINTN ValueSize
1494 )
1495{
1496}
1497
1523UINT32
1524EFIAPI
1526 IN UINT32 Index,
1527 OUT UINT32 *Eax OPTIONAL,
1528 OUT UINT32 *Ebx OPTIONAL,
1529 OUT UINT32 *Ecx OPTIONAL,
1530 OUT UINT32 *Edx OPTIONAL
1531 )
1532{
1533 return gUnitTestHostBaseLib.X86->AsmCpuid (Index, Eax, Ebx, Ecx, Edx);
1534}
1535
1568UINT32
1569EFIAPI
1571 IN UINT32 Index,
1572 IN UINT32 SubIndex,
1573 OUT UINT32 *Eax OPTIONAL,
1574 OUT UINT32 *Ebx OPTIONAL,
1575 OUT UINT32 *Ecx OPTIONAL,
1576 OUT UINT32 *Edx OPTIONAL
1577 )
1578{
1579 return gUnitTestHostBaseLib.X86->AsmCpuidEx (Index, SubIndex, Eax, Ebx, Ecx, Edx);
1580}
1581
1589VOID
1590EFIAPI
1592 VOID
1593 )
1594{
1595 gUnitTestHostBaseLib.X86->AsmDisableCache ();
1596}
1597
1605VOID
1606EFIAPI
1608 VOID
1609 )
1610{
1611 gUnitTestHostBaseLib.X86->AsmEnableCache ();
1612}
1613
1628UINT64
1629EFIAPI
1631 IN UINT32 Index
1632 )
1633{
1634 return gUnitTestHostBaseLib.X86->AsmReadMsr64 (Index);
1635}
1636
1654UINT64
1655EFIAPI
1657 IN UINT32 Index,
1658 IN UINT64 Value
1659 )
1660{
1661 return gUnitTestHostBaseLib.X86->AsmWriteMsr64 (Index, Value);
1662}
1663
1674UINTN
1675EFIAPI
1677 VOID
1678 )
1679{
1680 return gUnitTestHostBaseLib.X86->AsmReadCr0 ();
1681}
1682
1693UINTN
1694EFIAPI
1696 VOID
1697 )
1698{
1699 return gUnitTestHostBaseLib.X86->AsmReadCr2 ();
1700}
1701
1712UINTN
1713EFIAPI
1715 VOID
1716 )
1717{
1718 return gUnitTestHostBaseLib.X86->AsmReadCr3 ();
1719}
1720
1731UINTN
1732EFIAPI
1734 VOID
1735 )
1736{
1737 return gUnitTestHostBaseLib.X86->AsmReadCr4 ();
1738}
1739
1751UINTN
1752EFIAPI
1754 UINTN Cr0
1755 )
1756{
1757 return gUnitTestHostBaseLib.X86->AsmWriteCr0 (Cr0);
1758}
1759
1771UINTN
1772EFIAPI
1774 UINTN Cr2
1775 )
1776{
1777 return gUnitTestHostBaseLib.X86->AsmWriteCr2 (Cr2);
1778}
1779
1791UINTN
1792EFIAPI
1794 UINTN Cr3
1795 )
1796{
1797 return gUnitTestHostBaseLib.X86->AsmWriteCr3 (Cr3);
1798}
1799
1811UINTN
1812EFIAPI
1814 UINTN Cr4
1815 )
1816{
1817 return gUnitTestHostBaseLib.X86->AsmWriteCr4 (Cr4);
1818}
1819
1830UINTN
1831EFIAPI
1833 VOID
1834 )
1835{
1836 return gUnitTestHostBaseLib.X86->AsmReadDr0 ();
1837}
1838
1849UINTN
1850EFIAPI
1852 VOID
1853 )
1854{
1855 return gUnitTestHostBaseLib.X86->AsmReadDr1 ();
1856}
1857
1868UINTN
1869EFIAPI
1871 VOID
1872 )
1873{
1874 return gUnitTestHostBaseLib.X86->AsmReadDr2 ();
1875}
1876
1887UINTN
1888EFIAPI
1890 VOID
1891 )
1892{
1893 return gUnitTestHostBaseLib.X86->AsmReadDr3 ();
1894}
1895
1906UINTN
1907EFIAPI
1909 VOID
1910 )
1911{
1912 return gUnitTestHostBaseLib.X86->AsmReadDr4 ();
1913}
1914
1925UINTN
1926EFIAPI
1928 VOID
1929 )
1930{
1931 return gUnitTestHostBaseLib.X86->AsmReadDr5 ();
1932}
1933
1944UINTN
1945EFIAPI
1947 VOID
1948 )
1949{
1950 return gUnitTestHostBaseLib.X86->AsmReadDr6 ();
1951}
1952
1963UINTN
1964EFIAPI
1966 VOID
1967 )
1968{
1969 return gUnitTestHostBaseLib.X86->AsmReadDr7 ();
1970}
1971
1983UINTN
1984EFIAPI
1986 UINTN Dr0
1987 )
1988{
1989 return gUnitTestHostBaseLib.X86->AsmWriteDr0 (Dr0);
1990}
1991
2003UINTN
2004EFIAPI
2006 UINTN Dr1
2007 )
2008{
2009 return gUnitTestHostBaseLib.X86->AsmWriteDr1 (Dr1);
2010}
2011
2023UINTN
2024EFIAPI
2026 UINTN Dr2
2027 )
2028{
2029 return gUnitTestHostBaseLib.X86->AsmWriteDr2 (Dr2);
2030}
2031
2043UINTN
2044EFIAPI
2046 UINTN Dr3
2047 )
2048{
2049 return gUnitTestHostBaseLib.X86->AsmWriteDr3 (Dr3);
2050}
2051
2063UINTN
2064EFIAPI
2066 UINTN Dr4
2067 )
2068{
2069 return gUnitTestHostBaseLib.X86->AsmWriteDr4 (Dr4);
2070}
2071
2083UINTN
2084EFIAPI
2086 UINTN Dr5
2087 )
2088{
2089 return gUnitTestHostBaseLib.X86->AsmWriteDr5 (Dr5);
2090}
2091
2103UINTN
2104EFIAPI
2106 UINTN Dr6
2107 )
2108{
2109 return gUnitTestHostBaseLib.X86->AsmWriteDr6 (Dr6);
2110}
2111
2123UINTN
2124EFIAPI
2126 UINTN Dr7
2127 )
2128{
2129 return gUnitTestHostBaseLib.X86->AsmWriteDr7 (Dr7);
2130}
2131
2141UINT16
2142EFIAPI
2144 VOID
2145 )
2146{
2147 return gUnitTestHostBaseLib.X86->AsmReadCs ();
2148}
2149
2159UINT16
2160EFIAPI
2162 VOID
2163 )
2164{
2165 return gUnitTestHostBaseLib.X86->AsmReadDs ();
2166}
2167
2177UINT16
2178EFIAPI
2180 VOID
2181 )
2182{
2183 return gUnitTestHostBaseLib.X86->AsmReadEs ();
2184}
2185
2195UINT16
2196EFIAPI
2198 VOID
2199 )
2200{
2201 return gUnitTestHostBaseLib.X86->AsmReadFs ();
2202}
2203
2213UINT16
2214EFIAPI
2216 VOID
2217 )
2218{
2219 return gUnitTestHostBaseLib.X86->AsmReadGs ();
2220}
2221
2231UINT16
2232EFIAPI
2234 VOID
2235 )
2236{
2237 return gUnitTestHostBaseLib.X86->AsmReadSs ();
2238}
2239
2249UINT16
2250EFIAPI
2252 VOID
2253 )
2254{
2255 return gUnitTestHostBaseLib.X86->AsmReadTr ();
2256}
2257
2269VOID
2270EFIAPI
2272 OUT IA32_DESCRIPTOR *Gdtr
2273 )
2274{
2275 gUnitTestHostBaseLib.X86->AsmReadGdtr (Gdtr);
2276}
2277
2289VOID
2290EFIAPI
2292 IN CONST IA32_DESCRIPTOR *Gdtr
2293 )
2294{
2295 gUnitTestHostBaseLib.X86->AsmWriteGdtr (Gdtr);
2296}
2297
2309VOID
2310EFIAPI
2312 OUT IA32_DESCRIPTOR *Idtr
2313 )
2314{
2315 gUnitTestHostBaseLib.X86->AsmReadIdtr (Idtr);
2316}
2317
2329VOID
2330EFIAPI
2332 IN CONST IA32_DESCRIPTOR *Idtr
2333 )
2334{
2335 gUnitTestHostBaseLib.X86->AsmWriteIdtr (Idtr);
2336}
2337
2347UINT16
2348EFIAPI
2350 VOID
2351 )
2352{
2353 return gUnitTestHostBaseLib.X86->AsmReadLdtr ();
2354}
2355
2365VOID
2366EFIAPI
2368 IN UINT16 Ldtr
2369 )
2370{
2371 gUnitTestHostBaseLib.X86->AsmWriteLdtr (Ldtr);
2372}
2373
2385UINT64
2386EFIAPI
2388 IN UINT32 Index
2389 )
2390{
2391 return gUnitTestHostBaseLib.X86->AsmReadPmc (Index);
2392}
2393
2410UINTN
2411EFIAPI
2413 IN UINTN Eax,
2414 IN UINTN Ecx,
2415 IN UINTN Edx
2416 )
2417{
2418 return gUnitTestHostBaseLib.X86->AsmMonitor (Eax, Ecx, Edx);
2419}
2420
2435UINTN
2436EFIAPI
2438 IN UINTN Eax,
2439 IN UINTN Ecx
2440 )
2441{
2442 return gUnitTestHostBaseLib.X86->AsmMwait (Eax, Ecx);
2443}
2444
2452VOID
2453EFIAPI
2455 VOID
2456 )
2457{
2458 gUnitTestHostBaseLib.X86->AsmWbinvd ();
2459}
2460
2468VOID
2469EFIAPI
2471 VOID
2472 )
2473{
2474 gUnitTestHostBaseLib.X86->AsmInvd ();
2475}
2476
2492VOID *
2493EFIAPI
2495 IN VOID *LinearAddress
2496 )
2497{
2498 return gUnitTestHostBaseLib.X86->AsmFlushCacheLine (LinearAddress);
2499}
2500
2538VOID
2539EFIAPI
2541 IN SWITCH_STACK_ENTRY_POINT EntryPoint,
2542 IN VOID *Context1 OPTIONAL,
2543 IN VOID *Context2 OPTIONAL,
2544 IN VOID *NewStack
2545 )
2546{
2547 gUnitTestHostBaseLib.X86->AsmEnablePaging32 (EntryPoint, Context1, Context2, NewStack);
2548}
2549
2584VOID
2585EFIAPI
2587 IN SWITCH_STACK_ENTRY_POINT EntryPoint,
2588 IN VOID *Context1 OPTIONAL,
2589 IN VOID *Context2 OPTIONAL,
2590 IN VOID *NewStack
2591 )
2592{
2593 gUnitTestHostBaseLib.X86->AsmDisablePaging32 (EntryPoint, Context1, Context2, NewStack);
2594}
2595
2628VOID
2629EFIAPI
2631 IN UINT16 Cs,
2632 IN UINT64 EntryPoint,
2633 IN UINT64 Context1 OPTIONAL,
2634 IN UINT64 Context2 OPTIONAL,
2635 IN UINT64 NewStack
2636 )
2637{
2638 gUnitTestHostBaseLib.X86->AsmEnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
2639}
2640
2671VOID
2672EFIAPI
2674 IN UINT16 Cs,
2675 IN UINT32 EntryPoint,
2676 IN UINT32 Context1 OPTIONAL,
2677 IN UINT32 Context2 OPTIONAL,
2678 IN UINT32 NewStack
2679 )
2680{
2681 gUnitTestHostBaseLib.X86->AsmDisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
2682}
2683
2705VOID
2706EFIAPI
2708 OUT UINT32 *RealModeBufferSize,
2709 OUT UINT32 *ExtraStackSize
2710 )
2711{
2712 gUnitTestHostBaseLib.X86->AsmGetThunk16Properties (RealModeBufferSize, ExtraStackSize);
2713}
2714
2729VOID
2730EFIAPI
2732 IN OUT THUNK_CONTEXT *ThunkContext
2733 )
2734{
2735 gUnitTestHostBaseLib.X86->AsmPrepareThunk16 (ThunkContext);
2736}
2737
2791VOID
2792EFIAPI
2794 IN OUT THUNK_CONTEXT *ThunkContext
2795 )
2796{
2797 gUnitTestHostBaseLib.X86->AsmThunk16 (ThunkContext);
2798}
2799
2820VOID
2821EFIAPI
2823 IN OUT THUNK_CONTEXT *ThunkContext
2824 )
2825{
2826 gUnitTestHostBaseLib.X86->AsmPrepareAndThunk16 (ThunkContext);
2827}
2828
2834VOID
2835EFIAPI
2837 IN UINT16 Selector
2838 )
2839{
2840 gUnitTestHostBaseLib.X86->AsmWriteTr (Selector);
2841}
2842
2850VOID
2851EFIAPI
2853 VOID
2854 )
2855{
2856 gUnitTestHostBaseLib.X86->AsmLfence ();
2857}
2858
2893VOID
2894EFIAPI
2896 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
2897 IN UINT64 PatchValue,
2898 IN UINTN ValueSize
2899 )
2900{
2901 gUnitTestHostBaseLib.X86->PatchInstructionX86 (InstructionEnd, PatchValue, ValueSize);
2902}
2903
2912};
2913
2978};
2979
2989};
UINT64 UINTN
#define NULL
Definition: Base.h:312
#define CONST
Definition: Base.h:259
#define STATIC
Definition: Base.h:264
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
VOID(EFIAPI * SWITCH_STACK_ENTRY_POINT)(IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL)
Definition: BaseLib.h:4519
VOID *EFIAPI CopyMem(OUT VOID *DestinationBuffer, IN CONST VOID *SourceBuffer, IN UINTN Length)
VOID EFIAPI UnitTestHostBaseLibEnableDisableInterrupts(VOID)
Definition: UnitTestHost.c:49
VOID EFIAPI UnitTestHostBaseLibEnableInterrupts(VOID)
Definition: UnitTestHost.c:22
BOOLEAN EFIAPI UnitTestHostBaseLibGetInterruptState(VOID)
Definition: UnitTestHost.c:72
VOID EFIAPI UnitTestHostBaseLibDisableInterrupts(VOID)
Definition: UnitTestHost.c:35
UINTN EFIAPI AsmWriteDr1(UINTN Dr1)
VOID EFIAPI AsmDisablePaging64(IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuid(IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
UINT16 EFIAPI AsmReadTr(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmDisableCache(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr4(UINTN Cr4)
STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr7(UINTN Dr7)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmMonitor(IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr2(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmMwait(IN UINTN Eax, IN UINTN Ecx)
VOID EFIAPI AsmReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
VOID EFIAPI UnitTestHostBaseLibAsmPrepareAndThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT16 EFIAPI AsmReadLdtr(VOID)
VOID EFIAPI AsmReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr1(VOID)
UINTN EFIAPI AsmWriteDr4(UINTN Dr4)
UINTN EFIAPI AsmReadDr1(VOID)
VOID EFIAPI AsmEnableCache(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWriteTr(IN UINT16 Selector)
UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib
VOID EFIAPI UnitTestHostBaseLibAsmPrepareThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
VOID EFIAPI AsmInvd(VOID)
UINTN EFIAPI AsmReadDr0(VOID)
UINT16 EFIAPI AsmReadFs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr2(UINTN Dr2)
UINTN EFIAPI AsmWriteDr7(UINTN Dr7)
UINT64 EFIAPI UnitTestHostBaseLibAsmReadPmc(IN UINT32 Index)
VOID EFIAPI UnitTestHostBaseLibAsmInvd(VOID)
UINTN EFIAPI AsmWriteDr3(UINTN Dr3)
UINT16 EFIAPI AsmReadEs(VOID)
UINTN EFIAPI AsmReadCr3(VOID)
STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr3(UINTN Cr3)
VOID EFIAPI AsmGetThunk16Properties(OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
UINTN EFIAPI AsmReadDr2(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadGs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr0(VOID)
VOID EFIAPI AsmWriteTr(IN UINT16 Selector)
VOID EFIAPI AsmPrepareThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINTN EFIAPI AsmWriteCr2(UINTN Cr2)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr2(UINTN Cr2)
UINT64 EFIAPI UnitTestHostBaseLibAsmReadMsr64(IN UINT32 Index)
UINTN EFIAPI AsmMonitor(IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
VOID EFIAPI UnitTestHostBaseLibAsmLfence(VOID)
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadFs(VOID)
UINTN EFIAPI AsmMwait(IN UINTN Eax, IN UINTN Ecx)
VOID EFIAPI UnitTestHostBaseLibAsmThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadDs(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWbinvd(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr3(UINTN Dr3)
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging64(IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
UINTN EFIAPI AsmWriteCr3(UINTN Cr3)
VOID EFIAPI UnitTestHostBaseLibAsmGetThunk16Properties(OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
VOID EFIAPI AsmDisablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr1(UINTN Dr1)
UINTN EFIAPI AsmWriteCr4(UINTN Cr4)
VOID EFIAPI AsmPrepareAndThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT32 EFIAPI AsmCpuid(IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
VOID EFIAPI UnitTestHostBaseLibAsmReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr0(UINTN Cr0)
VOID EFIAPI UnitTestHostBaseLibAsmEnableCache(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr4(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
VOID EFIAPI UnitTestHostBaseLibAsmWriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
VOID EFIAPI AsmThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
VOID EFIAPI AsmWbinvd(VOID)
VOID EFIAPI UnitTestHostBaseLibPatchInstructionX86(OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
VOID EFIAPI UnitTestHostBaseLibAsmWriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr7(VOID)
UINTN EFIAPI AsmReadCr0(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr0(UINTN Dr0)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadLdtr(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmWriteDr2(UINTN Dr2)
UINT64 EFIAPI UnitTestHostBaseLibAsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINTN EFIAPI AsmWriteDr0(UINTN Dr0)
VOID EFIAPI AsmDisableCache(VOID)
UINT32 EFIAPI AsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
UINT16 EFIAPI AsmReadGs(VOID)
UINTN EFIAPI AsmWriteCr0(UINTN Cr0)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr5(UINTN Dr5)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr5(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr2(VOID)
VOID *EFIAPI AsmFlushCacheLine(IN VOID *LinearAddress)
UINTN EFIAPI AsmWriteDr5(UINTN Dr5)
VOID EFIAPI AsmEnablePaging64(IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr0(VOID)
VOID EFIAPI AsmWriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI AsmReadCr2(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr4(UINTN Dr4)
UINT16 EFIAPI AsmReadSs(VOID)
UINT16 EFIAPI AsmReadCs(VOID)
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadEs(VOID)
UINTN EFIAPI AsmReadDr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr4(VOID)
VOID EFIAPI AsmWriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
VOID EFIAPI AsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmReadCr4(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadTr(VOID)
UINTN EFIAPI AsmReadDr6(VOID)
UINTN EFIAPI AsmWriteDr6(UINTN Dr6)
UINT64 EFIAPI AsmReadPmc(IN UINT32 Index)
VOID EFIAPI AsmEnablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINT16 EFIAPI AsmReadDs(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadSs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr6(UINTN Dr6)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadCs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr6(VOID)
UINTN EFIAPI AsmReadDr4(VOID)
UINTN EFIAPI AsmReadDr7(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging64(IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
VOID *EFIAPI UnitTestHostBaseLibAsmFlushCacheLine(IN VOID *LinearAddress)
STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000]
UINTN EFIAPI AsmReadDr5(VOID)
VOID EFIAPI AsmLfence(VOID)
VOID EFIAPI PatchInstructionX86(OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS