TianoCore EDK2 master
Loading...
Searching...
No Matches
X86UnitTestHost.c
Go to the documentation of this file.
1
9#include "UnitTestHost.h"
10
14#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0
15#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1
16#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2
17#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3
18#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4
19#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5
20#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6
21#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7
22
28STATIC UINTN mUnitTestHostBaseLibCr[5];
29STATIC UINTN mUnitTestHostBaseLibDr[8];
30STATIC UINT16 mUnitTestHostBaseLibSegment[8];
31STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr;
32STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr;
33
59UINT32
60EFIAPI
62 IN UINT32 Index,
63 OUT UINT32 *Eax OPTIONAL,
64 OUT UINT32 *Ebx OPTIONAL,
65 OUT UINT32 *Ecx OPTIONAL,
66 OUT UINT32 *Edx OPTIONAL
67 )
68{
69 UINT32 RetEcx;
70
71 RetEcx = 0;
72 switch (Index) {
73 case 1:
74 RetEcx |= BIT30; /* RdRand */
75 break;
76 }
77
78 if (Eax != NULL) {
79 *Eax = 0;
80 }
81
82 if (Ebx != NULL) {
83 *Ebx = 0;
84 }
85
86 if (Ecx != NULL) {
87 *Ecx = RetEcx;
88 }
89
90 if (Edx != NULL) {
91 *Edx = 0;
92 }
93
94 return Index;
95}
96
129UINT32
130EFIAPI
132 IN UINT32 Index,
133 IN UINT32 SubIndex,
134 OUT UINT32 *Eax OPTIONAL,
135 OUT UINT32 *Ebx OPTIONAL,
136 OUT UINT32 *Ecx OPTIONAL,
137 OUT UINT32 *Edx OPTIONAL
138 )
139{
140 if (Eax != NULL) {
141 *Eax = 0;
142 }
143
144 if (Ebx != NULL) {
145 *Ebx = 0;
146 }
147
148 if (Ecx != NULL) {
149 *Ecx = 0;
150 }
151
152 if (Edx != NULL) {
153 *Edx = 0;
154 }
155
156 return Index;
157}
158
166VOID
167EFIAPI
169 VOID
170 )
171{
172}
173
181VOID
182EFIAPI
184 VOID
185 )
186{
187}
188
203UINT64
204EFIAPI
206 IN UINT32 Index
207 )
208{
209 if (Index < 0x1000) {
210 return mUnitTestHostBaseLibMsr[0][Index];
211 }
212
213 if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
214 return mUnitTestHostBaseLibMsr[1][Index];
215 }
216
217 return 0;
218}
219
237UINT64
238EFIAPI
240 IN UINT32 Index,
241 IN UINT64 Value
242 )
243{
244 if (Index < 0x1000) {
245 mUnitTestHostBaseLibMsr[0][Index] = Value;
246 }
247
248 if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
249 mUnitTestHostBaseLibMsr[1][Index - 0xC00000000] = Value;
250 }
251
252 return Value;
253}
254
265UINTN
266EFIAPI
268 VOID
269 )
270{
271 return mUnitTestHostBaseLibCr[0];
272}
273
284UINTN
285EFIAPI
287 VOID
288 )
289{
290 return mUnitTestHostBaseLibCr[2];
291}
292
303UINTN
304EFIAPI
306 VOID
307 )
308{
309 return mUnitTestHostBaseLibCr[3];
310}
311
322UINTN
323EFIAPI
325 VOID
326 )
327{
328 return mUnitTestHostBaseLibCr[4];
329}
330
342UINTN
343EFIAPI
345 UINTN Cr0
346 )
347{
348 mUnitTestHostBaseLibCr[0] = Cr0;
349 return Cr0;
350}
351
363UINTN
364EFIAPI
366 UINTN Cr2
367 )
368{
369 mUnitTestHostBaseLibCr[2] = Cr2;
370 return Cr2;
371}
372
384UINTN
385EFIAPI
387 UINTN Cr3
388 )
389{
390 mUnitTestHostBaseLibCr[3] = Cr3;
391 return Cr3;
392}
393
405UINTN
406EFIAPI
408 UINTN Cr4
409 )
410{
411 mUnitTestHostBaseLibCr[4] = Cr4;
412 return Cr4;
413}
414
425UINTN
426EFIAPI
428 VOID
429 )
430{
431 return mUnitTestHostBaseLibDr[0];
432}
433
444UINTN
445EFIAPI
447 VOID
448 )
449{
450 return mUnitTestHostBaseLibDr[1];
451}
452
463UINTN
464EFIAPI
466 VOID
467 )
468{
469 return mUnitTestHostBaseLibDr[2];
470}
471
482UINTN
483EFIAPI
485 VOID
486 )
487{
488 return mUnitTestHostBaseLibDr[3];
489}
490
501UINTN
502EFIAPI
504 VOID
505 )
506{
507 return mUnitTestHostBaseLibDr[4];
508}
509
520UINTN
521EFIAPI
523 VOID
524 )
525{
526 return mUnitTestHostBaseLibDr[5];
527}
528
539UINTN
540EFIAPI
542 VOID
543 )
544{
545 return mUnitTestHostBaseLibDr[6];
546}
547
558UINTN
559EFIAPI
561 VOID
562 )
563{
564 return mUnitTestHostBaseLibDr[7];
565}
566
578UINTN
579EFIAPI
581 UINTN Dr0
582 )
583{
584 mUnitTestHostBaseLibDr[0] = Dr0;
585 return Dr0;
586}
587
599UINTN
600EFIAPI
602 UINTN Dr1
603 )
604{
605 mUnitTestHostBaseLibDr[1] = Dr1;
606 return Dr1;
607}
608
620UINTN
621EFIAPI
623 UINTN Dr2
624 )
625{
626 mUnitTestHostBaseLibDr[2] = Dr2;
627 return Dr2;
628}
629
641UINTN
642EFIAPI
644 UINTN Dr3
645 )
646{
647 mUnitTestHostBaseLibDr[3] = Dr3;
648 return Dr3;
649}
650
662UINTN
663EFIAPI
665 UINTN Dr4
666 )
667{
668 mUnitTestHostBaseLibDr[4] = Dr4;
669 return Dr4;
670}
671
683UINTN
684EFIAPI
686 UINTN Dr5
687 )
688{
689 mUnitTestHostBaseLibDr[5] = Dr5;
690 return Dr5;
691}
692
704UINTN
705EFIAPI
707 UINTN Dr6
708 )
709{
710 mUnitTestHostBaseLibDr[6] = Dr6;
711 return Dr6;
712}
713
725UINTN
726EFIAPI
728 UINTN Dr7
729 )
730{
731 mUnitTestHostBaseLibDr[7] = Dr7;
732 return Dr7;
733}
734
744UINT16
745EFIAPI
747 VOID
748 )
749{
750 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS];
751}
752
762UINT16
763EFIAPI
765 VOID
766 )
767{
768 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS];
769}
770
780UINT16
781EFIAPI
783 VOID
784 )
785{
786 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES];
787}
788
798UINT16
799EFIAPI
801 VOID
802 )
803{
804 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS];
805}
806
816UINT16
817EFIAPI
819 VOID
820 )
821{
822 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS];
823}
824
834UINT16
835EFIAPI
837 VOID
838 )
839{
840 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS];
841}
842
852UINT16
853EFIAPI
855 VOID
856 )
857{
858 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR];
859}
860
872VOID
873EFIAPI
875 OUT IA32_DESCRIPTOR *Gdtr
876 )
877{
878 Gdtr = &mUnitTestHostBaseLibGdtr;
879}
880
892VOID
893EFIAPI
895 IN CONST IA32_DESCRIPTOR *Gdtr
896 )
897{
898 CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr, sizeof (IA32_DESCRIPTOR));
899}
900
912VOID
913EFIAPI
915 OUT IA32_DESCRIPTOR *Idtr
916 )
917{
918 Idtr = &mUnitTestHostBaseLibIdtr;
919}
920
932VOID
933EFIAPI
935 IN CONST IA32_DESCRIPTOR *Idtr
936 )
937{
938 CopyMem (&mUnitTestHostBaseLibIdtr, Idtr, sizeof (IA32_DESCRIPTOR));
939}
940
950UINT16
951EFIAPI
953 VOID
954 )
955{
956 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR];
957}
958
968VOID
969EFIAPI
971 IN UINT16 Ldtr
972 )
973{
974 mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;
975}
976
988UINT64
989EFIAPI
991 IN UINT32 Index
992 )
993{
994 return 0;
995}
996
1013UINTN
1014EFIAPI
1016 IN UINTN Eax,
1017 IN UINTN Ecx,
1018 IN UINTN Edx
1019 )
1020{
1021 return Eax;
1022}
1023
1038UINTN
1039EFIAPI
1041 IN UINTN Eax,
1042 IN UINTN Ecx
1043 )
1044{
1045 return Eax;
1046}
1047
1055VOID
1056EFIAPI
1058 VOID
1059 )
1060{
1061}
1062
1070VOID
1071EFIAPI
1073 VOID
1074 )
1075{
1076}
1077
1093VOID *
1094EFIAPI
1096 IN VOID *LinearAddress
1097 )
1098{
1099 return LinearAddress;
1100}
1101
1139VOID
1140EFIAPI
1142 IN SWITCH_STACK_ENTRY_POINT EntryPoint,
1143 IN VOID *Context1 OPTIONAL,
1144 IN VOID *Context2 OPTIONAL,
1145 IN VOID *NewStack
1146 )
1147{
1148 EntryPoint (Context1, Context2);
1149}
1150
1185VOID
1186EFIAPI
1188 IN SWITCH_STACK_ENTRY_POINT EntryPoint,
1189 IN VOID *Context1 OPTIONAL,
1190 IN VOID *Context2 OPTIONAL,
1191 IN VOID *NewStack
1192 )
1193{
1194 EntryPoint (Context1, Context2);
1195}
1196
1229VOID
1230EFIAPI
1232 IN UINT16 Cs,
1233 IN UINT64 EntryPoint,
1234 IN UINT64 Context1 OPTIONAL,
1235 IN UINT64 Context2 OPTIONAL,
1236 IN UINT64 NewStack
1237 )
1238{
1239 SWITCH_STACK_ENTRY_POINT NewEntryPoint;
1240
1241 NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);
1242 NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);
1243}
1244
1275VOID
1276EFIAPI
1278 IN UINT16 Cs,
1279 IN UINT32 EntryPoint,
1280 IN UINT32 Context1 OPTIONAL,
1281 IN UINT32 Context2 OPTIONAL,
1282 IN UINT32 NewStack
1283 )
1284{
1285 SWITCH_STACK_ENTRY_POINT NewEntryPoint;
1286
1287 NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);
1288 NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);
1289}
1290
1312VOID
1313EFIAPI
1315 OUT UINT32 *RealModeBufferSize,
1316 OUT UINT32 *ExtraStackSize
1317 )
1318{
1319 *RealModeBufferSize = 0;
1320 *ExtraStackSize = 0;
1321}
1322
1337VOID
1338EFIAPI
1340 IN OUT THUNK_CONTEXT *ThunkContext
1341 )
1342{
1343}
1344
1398VOID
1399EFIAPI
1401 IN OUT THUNK_CONTEXT *ThunkContext
1402 )
1403{
1404}
1405
1426VOID
1427EFIAPI
1429 IN OUT THUNK_CONTEXT *ThunkContext
1430 )
1431{
1432}
1433
1439VOID
1440EFIAPI
1442 IN UINT16 Selector
1443 )
1444{
1445 mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;
1446}
1447
1455VOID
1456EFIAPI
1458 VOID
1459 )
1460{
1461}
1462
1497VOID
1498EFIAPI
1500 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
1501 IN UINT64 PatchValue,
1502 IN UINTN ValueSize
1503 )
1504{
1505}
1506
1532UINT32
1533EFIAPI
1535 IN UINT32 Index,
1536 OUT UINT32 *Eax OPTIONAL,
1537 OUT UINT32 *Ebx OPTIONAL,
1538 OUT UINT32 *Ecx OPTIONAL,
1539 OUT UINT32 *Edx OPTIONAL
1540 )
1541{
1542 return gUnitTestHostBaseLib.X86->AsmCpuid (Index, Eax, Ebx, Ecx, Edx);
1543}
1544
1577UINT32
1578EFIAPI
1580 IN UINT32 Index,
1581 IN UINT32 SubIndex,
1582 OUT UINT32 *Eax OPTIONAL,
1583 OUT UINT32 *Ebx OPTIONAL,
1584 OUT UINT32 *Ecx OPTIONAL,
1585 OUT UINT32 *Edx OPTIONAL
1586 )
1587{
1588 return gUnitTestHostBaseLib.X86->AsmCpuidEx (Index, SubIndex, Eax, Ebx, Ecx, Edx);
1589}
1590
1598VOID
1599EFIAPI
1601 VOID
1602 )
1603{
1604 gUnitTestHostBaseLib.X86->AsmDisableCache ();
1605}
1606
1614VOID
1615EFIAPI
1617 VOID
1618 )
1619{
1620 gUnitTestHostBaseLib.X86->AsmEnableCache ();
1621}
1622
1637UINT64
1638EFIAPI
1640 IN UINT32 Index
1641 )
1642{
1643 return gUnitTestHostBaseLib.X86->AsmReadMsr64 (Index);
1644}
1645
1663UINT64
1664EFIAPI
1666 IN UINT32 Index,
1667 IN UINT64 Value
1668 )
1669{
1670 return gUnitTestHostBaseLib.X86->AsmWriteMsr64 (Index, Value);
1671}
1672
1683UINTN
1684EFIAPI
1686 VOID
1687 )
1688{
1689 return gUnitTestHostBaseLib.X86->AsmReadCr0 ();
1690}
1691
1702UINTN
1703EFIAPI
1705 VOID
1706 )
1707{
1708 return gUnitTestHostBaseLib.X86->AsmReadCr2 ();
1709}
1710
1721UINTN
1722EFIAPI
1724 VOID
1725 )
1726{
1727 return gUnitTestHostBaseLib.X86->AsmReadCr3 ();
1728}
1729
1740UINTN
1741EFIAPI
1743 VOID
1744 )
1745{
1746 return gUnitTestHostBaseLib.X86->AsmReadCr4 ();
1747}
1748
1760UINTN
1761EFIAPI
1763 UINTN Cr0
1764 )
1765{
1766 return gUnitTestHostBaseLib.X86->AsmWriteCr0 (Cr0);
1767}
1768
1780UINTN
1781EFIAPI
1783 UINTN Cr2
1784 )
1785{
1786 return gUnitTestHostBaseLib.X86->AsmWriteCr2 (Cr2);
1787}
1788
1800UINTN
1801EFIAPI
1803 UINTN Cr3
1804 )
1805{
1806 return gUnitTestHostBaseLib.X86->AsmWriteCr3 (Cr3);
1807}
1808
1820UINTN
1821EFIAPI
1823 UINTN Cr4
1824 )
1825{
1826 return gUnitTestHostBaseLib.X86->AsmWriteCr4 (Cr4);
1827}
1828
1839UINTN
1840EFIAPI
1842 VOID
1843 )
1844{
1845 return gUnitTestHostBaseLib.X86->AsmReadDr0 ();
1846}
1847
1858UINTN
1859EFIAPI
1861 VOID
1862 )
1863{
1864 return gUnitTestHostBaseLib.X86->AsmReadDr1 ();
1865}
1866
1877UINTN
1878EFIAPI
1880 VOID
1881 )
1882{
1883 return gUnitTestHostBaseLib.X86->AsmReadDr2 ();
1884}
1885
1896UINTN
1897EFIAPI
1899 VOID
1900 )
1901{
1902 return gUnitTestHostBaseLib.X86->AsmReadDr3 ();
1903}
1904
1915UINTN
1916EFIAPI
1918 VOID
1919 )
1920{
1921 return gUnitTestHostBaseLib.X86->AsmReadDr4 ();
1922}
1923
1934UINTN
1935EFIAPI
1937 VOID
1938 )
1939{
1940 return gUnitTestHostBaseLib.X86->AsmReadDr5 ();
1941}
1942
1953UINTN
1954EFIAPI
1956 VOID
1957 )
1958{
1959 return gUnitTestHostBaseLib.X86->AsmReadDr6 ();
1960}
1961
1972UINTN
1973EFIAPI
1975 VOID
1976 )
1977{
1978 return gUnitTestHostBaseLib.X86->AsmReadDr7 ();
1979}
1980
1992UINTN
1993EFIAPI
1995 UINTN Dr0
1996 )
1997{
1998 return gUnitTestHostBaseLib.X86->AsmWriteDr0 (Dr0);
1999}
2000
2012UINTN
2013EFIAPI
2015 UINTN Dr1
2016 )
2017{
2018 return gUnitTestHostBaseLib.X86->AsmWriteDr1 (Dr1);
2019}
2020
2032UINTN
2033EFIAPI
2035 UINTN Dr2
2036 )
2037{
2038 return gUnitTestHostBaseLib.X86->AsmWriteDr2 (Dr2);
2039}
2040
2052UINTN
2053EFIAPI
2055 UINTN Dr3
2056 )
2057{
2058 return gUnitTestHostBaseLib.X86->AsmWriteDr3 (Dr3);
2059}
2060
2072UINTN
2073EFIAPI
2075 UINTN Dr4
2076 )
2077{
2078 return gUnitTestHostBaseLib.X86->AsmWriteDr4 (Dr4);
2079}
2080
2092UINTN
2093EFIAPI
2095 UINTN Dr5
2096 )
2097{
2098 return gUnitTestHostBaseLib.X86->AsmWriteDr5 (Dr5);
2099}
2100
2112UINTN
2113EFIAPI
2115 UINTN Dr6
2116 )
2117{
2118 return gUnitTestHostBaseLib.X86->AsmWriteDr6 (Dr6);
2119}
2120
2132UINTN
2133EFIAPI
2135 UINTN Dr7
2136 )
2137{
2138 return gUnitTestHostBaseLib.X86->AsmWriteDr7 (Dr7);
2139}
2140
2150UINT16
2151EFIAPI
2153 VOID
2154 )
2155{
2156 return gUnitTestHostBaseLib.X86->AsmReadCs ();
2157}
2158
2168UINT16
2169EFIAPI
2171 VOID
2172 )
2173{
2174 return gUnitTestHostBaseLib.X86->AsmReadDs ();
2175}
2176
2186UINT16
2187EFIAPI
2189 VOID
2190 )
2191{
2192 return gUnitTestHostBaseLib.X86->AsmReadEs ();
2193}
2194
2204UINT16
2205EFIAPI
2207 VOID
2208 )
2209{
2210 return gUnitTestHostBaseLib.X86->AsmReadFs ();
2211}
2212
2222UINT16
2223EFIAPI
2225 VOID
2226 )
2227{
2228 return gUnitTestHostBaseLib.X86->AsmReadGs ();
2229}
2230
2240UINT16
2241EFIAPI
2243 VOID
2244 )
2245{
2246 return gUnitTestHostBaseLib.X86->AsmReadSs ();
2247}
2248
2258UINT16
2259EFIAPI
2261 VOID
2262 )
2263{
2264 return gUnitTestHostBaseLib.X86->AsmReadTr ();
2265}
2266
2278VOID
2279EFIAPI
2281 OUT IA32_DESCRIPTOR *Gdtr
2282 )
2283{
2284 gUnitTestHostBaseLib.X86->AsmReadGdtr (Gdtr);
2285}
2286
2298VOID
2299EFIAPI
2301 IN CONST IA32_DESCRIPTOR *Gdtr
2302 )
2303{
2304 gUnitTestHostBaseLib.X86->AsmWriteGdtr (Gdtr);
2305}
2306
2318VOID
2319EFIAPI
2321 OUT IA32_DESCRIPTOR *Idtr
2322 )
2323{
2324 gUnitTestHostBaseLib.X86->AsmReadIdtr (Idtr);
2325}
2326
2338VOID
2339EFIAPI
2341 IN CONST IA32_DESCRIPTOR *Idtr
2342 )
2343{
2344 gUnitTestHostBaseLib.X86->AsmWriteIdtr (Idtr);
2345}
2346
2356UINT16
2357EFIAPI
2359 VOID
2360 )
2361{
2362 return gUnitTestHostBaseLib.X86->AsmReadLdtr ();
2363}
2364
2374VOID
2375EFIAPI
2377 IN UINT16 Ldtr
2378 )
2379{
2380 gUnitTestHostBaseLib.X86->AsmWriteLdtr (Ldtr);
2381}
2382
2394UINT64
2395EFIAPI
2397 IN UINT32 Index
2398 )
2399{
2400 return gUnitTestHostBaseLib.X86->AsmReadPmc (Index);
2401}
2402
2419UINTN
2420EFIAPI
2422 IN UINTN Eax,
2423 IN UINTN Ecx,
2424 IN UINTN Edx
2425 )
2426{
2427 return gUnitTestHostBaseLib.X86->AsmMonitor (Eax, Ecx, Edx);
2428}
2429
2444UINTN
2445EFIAPI
2447 IN UINTN Eax,
2448 IN UINTN Ecx
2449 )
2450{
2451 return gUnitTestHostBaseLib.X86->AsmMwait (Eax, Ecx);
2452}
2453
2461VOID
2462EFIAPI
2464 VOID
2465 )
2466{
2467 gUnitTestHostBaseLib.X86->AsmWbinvd ();
2468}
2469
2477VOID
2478EFIAPI
2480 VOID
2481 )
2482{
2483 gUnitTestHostBaseLib.X86->AsmInvd ();
2484}
2485
2501VOID *
2502EFIAPI
2504 IN VOID *LinearAddress
2505 )
2506{
2507 return gUnitTestHostBaseLib.X86->AsmFlushCacheLine (LinearAddress);
2508}
2509
2547VOID
2548EFIAPI
2550 IN SWITCH_STACK_ENTRY_POINT EntryPoint,
2551 IN VOID *Context1 OPTIONAL,
2552 IN VOID *Context2 OPTIONAL,
2553 IN VOID *NewStack
2554 )
2555{
2556 gUnitTestHostBaseLib.X86->AsmEnablePaging32 (EntryPoint, Context1, Context2, NewStack);
2557}
2558
2593VOID
2594EFIAPI
2596 IN SWITCH_STACK_ENTRY_POINT EntryPoint,
2597 IN VOID *Context1 OPTIONAL,
2598 IN VOID *Context2 OPTIONAL,
2599 IN VOID *NewStack
2600 )
2601{
2602 gUnitTestHostBaseLib.X86->AsmDisablePaging32 (EntryPoint, Context1, Context2, NewStack);
2603}
2604
2637VOID
2638EFIAPI
2640 IN UINT16 Cs,
2641 IN UINT64 EntryPoint,
2642 IN UINT64 Context1 OPTIONAL,
2643 IN UINT64 Context2 OPTIONAL,
2644 IN UINT64 NewStack
2645 )
2646{
2647 gUnitTestHostBaseLib.X86->AsmEnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
2648}
2649
2680VOID
2681EFIAPI
2683 IN UINT16 Cs,
2684 IN UINT32 EntryPoint,
2685 IN UINT32 Context1 OPTIONAL,
2686 IN UINT32 Context2 OPTIONAL,
2687 IN UINT32 NewStack
2688 )
2689{
2690 gUnitTestHostBaseLib.X86->AsmDisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
2691}
2692
2714VOID
2715EFIAPI
2717 OUT UINT32 *RealModeBufferSize,
2718 OUT UINT32 *ExtraStackSize
2719 )
2720{
2721 gUnitTestHostBaseLib.X86->AsmGetThunk16Properties (RealModeBufferSize, ExtraStackSize);
2722}
2723
2738VOID
2739EFIAPI
2741 IN OUT THUNK_CONTEXT *ThunkContext
2742 )
2743{
2744 gUnitTestHostBaseLib.X86->AsmPrepareThunk16 (ThunkContext);
2745}
2746
2800VOID
2801EFIAPI
2803 IN OUT THUNK_CONTEXT *ThunkContext
2804 )
2805{
2806 gUnitTestHostBaseLib.X86->AsmThunk16 (ThunkContext);
2807}
2808
2829VOID
2830EFIAPI
2832 IN OUT THUNK_CONTEXT *ThunkContext
2833 )
2834{
2835 gUnitTestHostBaseLib.X86->AsmPrepareAndThunk16 (ThunkContext);
2836}
2837
2843VOID
2844EFIAPI
2846 IN UINT16 Selector
2847 )
2848{
2849 gUnitTestHostBaseLib.X86->AsmWriteTr (Selector);
2850}
2851
2859VOID
2860EFIAPI
2862 VOID
2863 )
2864{
2865 gUnitTestHostBaseLib.X86->AsmLfence ();
2866}
2867
2902VOID
2903EFIAPI
2905 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
2906 IN UINT64 PatchValue,
2907 IN UINTN ValueSize
2908 )
2909{
2910 gUnitTestHostBaseLib.X86->PatchInstructionX86 (InstructionEnd, PatchValue, ValueSize);
2911}
2912
2921};
2922
2987};
2988
2998};
UINT64 UINTN
VOID(EFIAPI * SWITCH_STACK_ENTRY_POINT)(IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL)
Definition: BaseLib.h:5019
VOID *EFIAPI CopyMem(OUT VOID *DestinationBuffer, IN CONST VOID *SourceBuffer, IN UINTN Length)
#define NULL
Definition: Base.h:319
#define CONST
Definition: Base.h:259
#define STATIC
Definition: Base.h:264
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
VOID EFIAPI UnitTestHostBaseLibEnableDisableInterrupts(VOID)
Definition: UnitTestHost.c:49
VOID EFIAPI UnitTestHostBaseLibEnableInterrupts(VOID)
Definition: UnitTestHost.c:22
BOOLEAN EFIAPI UnitTestHostBaseLibGetInterruptState(VOID)
Definition: UnitTestHost.c:72
VOID EFIAPI UnitTestHostBaseLibDisableInterrupts(VOID)
Definition: UnitTestHost.c:35
UINTN EFIAPI AsmWriteDr1(UINTN Dr1)
VOID EFIAPI AsmDisablePaging64(IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuid(IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
UINT16 EFIAPI AsmReadTr(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmDisableCache(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr4(UINTN Cr4)
STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr7(UINTN Dr7)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmMonitor(IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr2(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmMwait(IN UINTN Eax, IN UINTN Ecx)
VOID EFIAPI AsmReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
VOID EFIAPI UnitTestHostBaseLibAsmPrepareAndThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT16 EFIAPI AsmReadLdtr(VOID)
VOID EFIAPI AsmReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr1(VOID)
UINTN EFIAPI AsmWriteDr4(UINTN Dr4)
UINTN EFIAPI AsmReadDr1(VOID)
VOID EFIAPI AsmEnableCache(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWriteTr(IN UINT16 Selector)
UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib
VOID EFIAPI UnitTestHostBaseLibAsmPrepareThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
VOID EFIAPI AsmInvd(VOID)
UINTN EFIAPI AsmReadDr0(VOID)
UINT16 EFIAPI AsmReadFs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr2(UINTN Dr2)
UINTN EFIAPI AsmWriteDr7(UINTN Dr7)
UINT64 EFIAPI UnitTestHostBaseLibAsmReadPmc(IN UINT32 Index)
VOID EFIAPI UnitTestHostBaseLibAsmInvd(VOID)
UINTN EFIAPI AsmWriteDr3(UINTN Dr3)
UINT16 EFIAPI AsmReadEs(VOID)
UINTN EFIAPI AsmReadCr3(VOID)
STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr3(UINTN Cr3)
VOID EFIAPI AsmGetThunk16Properties(OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
UINTN EFIAPI AsmReadDr2(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadGs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr0(VOID)
VOID EFIAPI AsmWriteTr(IN UINT16 Selector)
VOID EFIAPI AsmPrepareThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINTN EFIAPI AsmWriteCr2(UINTN Cr2)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr2(UINTN Cr2)
UINT64 EFIAPI UnitTestHostBaseLibAsmReadMsr64(IN UINT32 Index)
UINTN EFIAPI AsmMonitor(IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
VOID EFIAPI UnitTestHostBaseLibAsmLfence(VOID)
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadFs(VOID)
UINTN EFIAPI AsmMwait(IN UINTN Eax, IN UINTN Ecx)
VOID EFIAPI UnitTestHostBaseLibAsmThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadDs(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWbinvd(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr3(UINTN Dr3)
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging64(IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
UINTN EFIAPI AsmWriteCr3(UINTN Cr3)
VOID EFIAPI UnitTestHostBaseLibAsmGetThunk16Properties(OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
VOID EFIAPI AsmDisablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr1(UINTN Dr1)
UINTN EFIAPI AsmWriteCr4(UINTN Cr4)
VOID EFIAPI AsmPrepareAndThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT32 EFIAPI AsmCpuid(IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
VOID EFIAPI UnitTestHostBaseLibAsmReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr0(UINTN Cr0)
VOID EFIAPI UnitTestHostBaseLibAsmEnableCache(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr4(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
VOID EFIAPI UnitTestHostBaseLibAsmWriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
VOID EFIAPI AsmThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
VOID EFIAPI AsmWbinvd(VOID)
VOID EFIAPI UnitTestHostBaseLibPatchInstructionX86(OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
VOID EFIAPI UnitTestHostBaseLibAsmWriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr7(VOID)
UINTN EFIAPI AsmReadCr0(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr0(UINTN Dr0)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadLdtr(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmWriteDr2(UINTN Dr2)
UINT64 EFIAPI UnitTestHostBaseLibAsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINTN EFIAPI AsmWriteDr0(UINTN Dr0)
VOID EFIAPI AsmDisableCache(VOID)
UINT32 EFIAPI AsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
UINT16 EFIAPI AsmReadGs(VOID)
UINTN EFIAPI AsmWriteCr0(UINTN Cr0)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr5(UINTN Dr5)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr5(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr2(VOID)
VOID *EFIAPI AsmFlushCacheLine(IN VOID *LinearAddress)
UINTN EFIAPI AsmWriteDr5(UINTN Dr5)
VOID EFIAPI AsmEnablePaging64(IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr0(VOID)
VOID EFIAPI AsmWriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI AsmReadCr2(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr4(UINTN Dr4)
UINT16 EFIAPI AsmReadSs(VOID)
UINT16 EFIAPI AsmReadCs(VOID)
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadEs(VOID)
UINTN EFIAPI AsmReadDr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr4(VOID)
VOID EFIAPI AsmWriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
VOID EFIAPI AsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmReadCr4(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadTr(VOID)
UINTN EFIAPI AsmReadDr6(VOID)
UINTN EFIAPI AsmWriteDr6(UINTN Dr6)
UINT64 EFIAPI AsmReadPmc(IN UINT32 Index)
VOID EFIAPI AsmEnablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINT16 EFIAPI AsmReadDs(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadSs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr6(UINTN Dr6)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadCs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr6(VOID)
UINTN EFIAPI AsmReadDr4(VOID)
UINTN EFIAPI AsmReadDr7(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging64(IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
VOID *EFIAPI UnitTestHostBaseLibAsmFlushCacheLine(IN VOID *LinearAddress)
STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000]
UINTN EFIAPI AsmReadDr5(VOID)
VOID EFIAPI AsmLfence(VOID)
VOID EFIAPI PatchInstructionX86(OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS