14#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0
15#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1
16#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2
17#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3
18#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4
19#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5
20#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6
21#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7
30STATIC UINT16 mUnitTestHostBaseLibSegment[8];
31STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr;
32STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr;
63 OUT UINT32 *Eax OPTIONAL,
64 OUT UINT32 *Ebx OPTIONAL,
65 OUT UINT32 *Ecx OPTIONAL,
66 OUT UINT32 *Edx OPTIONAL
125 OUT UINT32 *Eax OPTIONAL,
126 OUT UINT32 *Ebx OPTIONAL,
127 OUT UINT32 *Ecx OPTIONAL,
128 OUT UINT32 *Edx OPTIONAL
200 if (Index < 0x1000) {
204 if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
235 if (Index < 0x1000) {
239 if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
262 return mUnitTestHostBaseLibCr[0];
281 return mUnitTestHostBaseLibCr[2];
300 return mUnitTestHostBaseLibCr[3];
319 return mUnitTestHostBaseLibCr[4];
339 mUnitTestHostBaseLibCr[0] = Cr0;
360 mUnitTestHostBaseLibCr[2] = Cr2;
381 mUnitTestHostBaseLibCr[3] = Cr3;
402 mUnitTestHostBaseLibCr[4] = Cr4;
422 return mUnitTestHostBaseLibDr[0];
441 return mUnitTestHostBaseLibDr[1];
460 return mUnitTestHostBaseLibDr[2];
479 return mUnitTestHostBaseLibDr[3];
498 return mUnitTestHostBaseLibDr[4];
517 return mUnitTestHostBaseLibDr[5];
536 return mUnitTestHostBaseLibDr[6];
555 return mUnitTestHostBaseLibDr[7];
575 mUnitTestHostBaseLibDr[0] = Dr0;
596 mUnitTestHostBaseLibDr[1] = Dr1;
617 mUnitTestHostBaseLibDr[2] = Dr2;
638 mUnitTestHostBaseLibDr[3] = Dr3;
659 mUnitTestHostBaseLibDr[4] = Dr4;
680 mUnitTestHostBaseLibDr[5] = Dr5;
701 mUnitTestHostBaseLibDr[6] = Dr6;
722 mUnitTestHostBaseLibDr[7] = Dr7;
759 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS];
777 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES];
795 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS];
813 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS];
831 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS];
849 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR];
866 OUT IA32_DESCRIPTOR *Gdtr
869 Gdtr = &mUnitTestHostBaseLibGdtr;
889 CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr,
sizeof (IA32_DESCRIPTOR));
906 OUT IA32_DESCRIPTOR *Idtr
909 Idtr = &mUnitTestHostBaseLibIdtr;
929 CopyMem (&mUnitTestHostBaseLibIdtr, Idtr,
sizeof (IA32_DESCRIPTOR));
947 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR];
965 mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;
1087 IN VOID *LinearAddress
1090 return LinearAddress;
1134 IN VOID *Context1 OPTIONAL,
1135 IN VOID *Context2 OPTIONAL,
1139 EntryPoint (Context1, Context2);
1180 IN VOID *Context1 OPTIONAL,
1181 IN VOID *Context2 OPTIONAL,
1185 EntryPoint (Context1, Context2);
1224 IN UINT64 EntryPoint,
1225 IN UINT64 Context1 OPTIONAL,
1226 IN UINT64 Context2 OPTIONAL,
1233 NewEntryPoint ((VOID *)(
UINTN)Context1, (VOID *)(
UINTN)Context2);
1270 IN UINT32 EntryPoint,
1271 IN UINT32 Context1 OPTIONAL,
1272 IN UINT32 Context2 OPTIONAL,
1279 NewEntryPoint ((VOID *)(
UINTN)Context1, (VOID *)(
UINTN)Context2);
1306 OUT UINT32 *RealModeBufferSize,
1307 OUT UINT32 *ExtraStackSize
1310 *RealModeBufferSize = 0;
1311 *ExtraStackSize = 0;
1331 IN OUT THUNK_CONTEXT *ThunkContext
1392 IN OUT THUNK_CONTEXT *ThunkContext
1420 IN OUT THUNK_CONTEXT *ThunkContext
1436 mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;
1491 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
1492 IN UINT64 PatchValue,
1527 OUT UINT32 *Eax OPTIONAL,
1528 OUT UINT32 *Ebx OPTIONAL,
1529 OUT UINT32 *Ecx OPTIONAL,
1530 OUT UINT32 *Edx OPTIONAL
1573 OUT UINT32 *Eax OPTIONAL,
1574 OUT UINT32 *Ebx OPTIONAL,
1575 OUT UINT32 *Ecx OPTIONAL,
1576 OUT UINT32 *Edx OPTIONAL
2272 OUT IA32_DESCRIPTOR *Gdtr
2292 IN CONST IA32_DESCRIPTOR *Gdtr
2312 OUT IA32_DESCRIPTOR *Idtr
2332 IN CONST IA32_DESCRIPTOR *Idtr
2495 IN VOID *LinearAddress
2542 IN VOID *Context1 OPTIONAL,
2543 IN VOID *Context2 OPTIONAL,
2588 IN VOID *Context1 OPTIONAL,
2589 IN VOID *Context2 OPTIONAL,
2632 IN UINT64 EntryPoint,
2633 IN UINT64 Context1 OPTIONAL,
2634 IN UINT64 Context2 OPTIONAL,
2675 IN UINT32 EntryPoint,
2676 IN UINT32 Context1 OPTIONAL,
2677 IN UINT32 Context2 OPTIONAL,
2708 OUT UINT32 *RealModeBufferSize,
2709 OUT UINT32 *ExtraStackSize
2732 IN OUT THUNK_CONTEXT *ThunkContext
2794 IN OUT THUNK_CONTEXT *ThunkContext
2823 IN OUT THUNK_CONTEXT *ThunkContext
2896 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
2897 IN UINT64 PatchValue,
VOID(EFIAPI * SWITCH_STACK_ENTRY_POINT)(IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL)
VOID *EFIAPI CopyMem(OUT VOID *DestinationBuffer, IN CONST VOID *SourceBuffer, IN UINTN Length)
VOID EFIAPI UnitTestHostBaseLibEnableDisableInterrupts(VOID)
VOID EFIAPI UnitTestHostBaseLibEnableInterrupts(VOID)
BOOLEAN EFIAPI UnitTestHostBaseLibGetInterruptState(VOID)
VOID EFIAPI UnitTestHostBaseLibDisableInterrupts(VOID)
UINTN EFIAPI AsmWriteDr1(UINTN Dr1)
VOID EFIAPI AsmDisablePaging64(IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuid(IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
UINT16 EFIAPI AsmReadTr(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmDisableCache(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr4(UINTN Cr4)
STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr7(UINTN Dr7)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmMonitor(IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr2(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmMwait(IN UINTN Eax, IN UINTN Ecx)
VOID EFIAPI AsmReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
VOID EFIAPI UnitTestHostBaseLibAsmPrepareAndThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT16 EFIAPI AsmReadLdtr(VOID)
VOID EFIAPI AsmReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr1(VOID)
UINTN EFIAPI AsmWriteDr4(UINTN Dr4)
UINTN EFIAPI AsmReadDr1(VOID)
VOID EFIAPI AsmEnableCache(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWriteTr(IN UINT16 Selector)
UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib
VOID EFIAPI UnitTestHostBaseLibAsmPrepareThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
VOID EFIAPI AsmInvd(VOID)
UINTN EFIAPI AsmReadDr0(VOID)
UINT16 EFIAPI AsmReadFs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr2(UINTN Dr2)
UINTN EFIAPI AsmWriteDr7(UINTN Dr7)
UINT64 EFIAPI UnitTestHostBaseLibAsmReadPmc(IN UINT32 Index)
VOID EFIAPI UnitTestHostBaseLibAsmInvd(VOID)
UINTN EFIAPI AsmWriteDr3(UINTN Dr3)
UINT16 EFIAPI AsmReadEs(VOID)
UINTN EFIAPI AsmReadCr3(VOID)
STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr3(UINTN Cr3)
VOID EFIAPI AsmGetThunk16Properties(OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
UINTN EFIAPI AsmReadDr2(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadGs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr0(VOID)
VOID EFIAPI AsmWriteTr(IN UINT16 Selector)
VOID EFIAPI AsmPrepareThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINTN EFIAPI AsmWriteCr2(UINTN Cr2)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr2(UINTN Cr2)
UINT64 EFIAPI UnitTestHostBaseLibAsmReadMsr64(IN UINT32 Index)
UINTN EFIAPI AsmMonitor(IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
VOID EFIAPI UnitTestHostBaseLibAsmLfence(VOID)
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadFs(VOID)
UINTN EFIAPI AsmMwait(IN UINTN Eax, IN UINTN Ecx)
VOID EFIAPI UnitTestHostBaseLibAsmThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadDs(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWbinvd(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr3(UINTN Dr3)
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging64(IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
UINTN EFIAPI AsmWriteCr3(UINTN Cr3)
VOID EFIAPI UnitTestHostBaseLibAsmGetThunk16Properties(OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
VOID EFIAPI AsmDisablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr1(UINTN Dr1)
UINTN EFIAPI AsmWriteCr4(UINTN Cr4)
VOID EFIAPI AsmPrepareAndThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT32 EFIAPI AsmCpuid(IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
VOID EFIAPI UnitTestHostBaseLibAsmReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr0(UINTN Cr0)
VOID EFIAPI UnitTestHostBaseLibAsmEnableCache(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr4(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
VOID EFIAPI UnitTestHostBaseLibAsmWriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
VOID EFIAPI AsmThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
VOID EFIAPI AsmWbinvd(VOID)
VOID EFIAPI UnitTestHostBaseLibPatchInstructionX86(OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
VOID EFIAPI UnitTestHostBaseLibAsmWriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr7(VOID)
UINTN EFIAPI AsmReadCr0(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr0(UINTN Dr0)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadLdtr(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmWriteDr2(UINTN Dr2)
UINT64 EFIAPI UnitTestHostBaseLibAsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINTN EFIAPI AsmWriteDr0(UINTN Dr0)
VOID EFIAPI AsmDisableCache(VOID)
UINT32 EFIAPI AsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
UINT16 EFIAPI AsmReadGs(VOID)
UINTN EFIAPI AsmWriteCr0(UINTN Cr0)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr5(UINTN Dr5)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr5(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr2(VOID)
VOID *EFIAPI AsmFlushCacheLine(IN VOID *LinearAddress)
UINTN EFIAPI AsmWriteDr5(UINTN Dr5)
VOID EFIAPI AsmEnablePaging64(IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr0(VOID)
VOID EFIAPI AsmWriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI AsmReadCr2(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr4(UINTN Dr4)
UINT16 EFIAPI AsmReadSs(VOID)
UINT16 EFIAPI AsmReadCs(VOID)
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadEs(VOID)
UINTN EFIAPI AsmReadDr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr4(VOID)
VOID EFIAPI AsmWriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
VOID EFIAPI AsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmReadCr4(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadTr(VOID)
UINTN EFIAPI AsmReadDr6(VOID)
UINTN EFIAPI AsmWriteDr6(UINTN Dr6)
UINT64 EFIAPI AsmReadPmc(IN UINT32 Index)
VOID EFIAPI AsmEnablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINT16 EFIAPI AsmReadDs(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadSs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr6(UINTN Dr6)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadCs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr6(VOID)
UINTN EFIAPI AsmReadDr4(VOID)
UINTN EFIAPI AsmReadDr7(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging64(IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
VOID *EFIAPI UnitTestHostBaseLibAsmFlushCacheLine(IN VOID *LinearAddress)
STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000]
UINTN EFIAPI AsmReadDr5(VOID)
VOID EFIAPI AsmLfence(VOID)
VOID EFIAPI PatchInstructionX86(OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS