14#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0
15#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1
16#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2
17#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3
18#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4
19#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5
20#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6
21#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7
30STATIC UINT16 mUnitTestHostBaseLibSegment[8];
31STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr;
32STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr;
63 OUT UINT32 *Eax OPTIONAL,
64 OUT UINT32 *Ebx OPTIONAL,
65 OUT UINT32 *Ecx OPTIONAL,
66 OUT UINT32 *Edx OPTIONAL
134 OUT UINT32 *Eax OPTIONAL,
135 OUT UINT32 *Ebx OPTIONAL,
136 OUT UINT32 *Ecx OPTIONAL,
137 OUT UINT32 *Edx OPTIONAL
209 if (Index < 0x1000) {
213 if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
244 if (Index < 0x1000) {
248 if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
271 return mUnitTestHostBaseLibCr[0];
290 return mUnitTestHostBaseLibCr[2];
309 return mUnitTestHostBaseLibCr[3];
328 return mUnitTestHostBaseLibCr[4];
348 mUnitTestHostBaseLibCr[0] = Cr0;
369 mUnitTestHostBaseLibCr[2] = Cr2;
390 mUnitTestHostBaseLibCr[3] = Cr3;
411 mUnitTestHostBaseLibCr[4] = Cr4;
431 return mUnitTestHostBaseLibDr[0];
450 return mUnitTestHostBaseLibDr[1];
469 return mUnitTestHostBaseLibDr[2];
488 return mUnitTestHostBaseLibDr[3];
507 return mUnitTestHostBaseLibDr[4];
526 return mUnitTestHostBaseLibDr[5];
545 return mUnitTestHostBaseLibDr[6];
564 return mUnitTestHostBaseLibDr[7];
584 mUnitTestHostBaseLibDr[0] = Dr0;
605 mUnitTestHostBaseLibDr[1] = Dr1;
626 mUnitTestHostBaseLibDr[2] = Dr2;
647 mUnitTestHostBaseLibDr[3] = Dr3;
668 mUnitTestHostBaseLibDr[4] = Dr4;
689 mUnitTestHostBaseLibDr[5] = Dr5;
710 mUnitTestHostBaseLibDr[6] = Dr6;
731 mUnitTestHostBaseLibDr[7] = Dr7;
768 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS];
786 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES];
804 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS];
822 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS];
840 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS];
858 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR];
875 OUT IA32_DESCRIPTOR *Gdtr
878 Gdtr = &mUnitTestHostBaseLibGdtr;
898 CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr,
sizeof (IA32_DESCRIPTOR));
915 OUT IA32_DESCRIPTOR *Idtr
918 Idtr = &mUnitTestHostBaseLibIdtr;
938 CopyMem (&mUnitTestHostBaseLibIdtr, Idtr,
sizeof (IA32_DESCRIPTOR));
956 return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR];
974 mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;
1096 IN VOID *LinearAddress
1099 return LinearAddress;
1143 IN VOID *Context1 OPTIONAL,
1144 IN VOID *Context2 OPTIONAL,
1148 EntryPoint (Context1, Context2);
1189 IN VOID *Context1 OPTIONAL,
1190 IN VOID *Context2 OPTIONAL,
1194 EntryPoint (Context1, Context2);
1233 IN UINT64 EntryPoint,
1234 IN UINT64 Context1 OPTIONAL,
1235 IN UINT64 Context2 OPTIONAL,
1242 NewEntryPoint ((VOID *)(
UINTN)Context1, (VOID *)(
UINTN)Context2);
1279 IN UINT32 EntryPoint,
1280 IN UINT32 Context1 OPTIONAL,
1281 IN UINT32 Context2 OPTIONAL,
1288 NewEntryPoint ((VOID *)(
UINTN)Context1, (VOID *)(
UINTN)Context2);
1315 OUT UINT32 *RealModeBufferSize,
1316 OUT UINT32 *ExtraStackSize
1319 *RealModeBufferSize = 0;
1320 *ExtraStackSize = 0;
1340 IN OUT THUNK_CONTEXT *ThunkContext
1401 IN OUT THUNK_CONTEXT *ThunkContext
1429 IN OUT THUNK_CONTEXT *ThunkContext
1445 mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;
1500 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
1501 IN UINT64 PatchValue,
1536 OUT UINT32 *Eax OPTIONAL,
1537 OUT UINT32 *Ebx OPTIONAL,
1538 OUT UINT32 *Ecx OPTIONAL,
1539 OUT UINT32 *Edx OPTIONAL
1582 OUT UINT32 *Eax OPTIONAL,
1583 OUT UINT32 *Ebx OPTIONAL,
1584 OUT UINT32 *Ecx OPTIONAL,
1585 OUT UINT32 *Edx OPTIONAL
2281 OUT IA32_DESCRIPTOR *Gdtr
2301 IN CONST IA32_DESCRIPTOR *Gdtr
2321 OUT IA32_DESCRIPTOR *Idtr
2341 IN CONST IA32_DESCRIPTOR *Idtr
2504 IN VOID *LinearAddress
2551 IN VOID *Context1 OPTIONAL,
2552 IN VOID *Context2 OPTIONAL,
2597 IN VOID *Context1 OPTIONAL,
2598 IN VOID *Context2 OPTIONAL,
2641 IN UINT64 EntryPoint,
2642 IN UINT64 Context1 OPTIONAL,
2643 IN UINT64 Context2 OPTIONAL,
2684 IN UINT32 EntryPoint,
2685 IN UINT32 Context1 OPTIONAL,
2686 IN UINT32 Context2 OPTIONAL,
2717 OUT UINT32 *RealModeBufferSize,
2718 OUT UINT32 *ExtraStackSize
2741 IN OUT THUNK_CONTEXT *ThunkContext
2803 IN OUT THUNK_CONTEXT *ThunkContext
2832 IN OUT THUNK_CONTEXT *ThunkContext
2905 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
2906 IN UINT64 PatchValue,
VOID(EFIAPI * SWITCH_STACK_ENTRY_POINT)(IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL)
VOID *EFIAPI CopyMem(OUT VOID *DestinationBuffer, IN CONST VOID *SourceBuffer, IN UINTN Length)
VOID EFIAPI UnitTestHostBaseLibEnableDisableInterrupts(VOID)
VOID EFIAPI UnitTestHostBaseLibEnableInterrupts(VOID)
BOOLEAN EFIAPI UnitTestHostBaseLibGetInterruptState(VOID)
VOID EFIAPI UnitTestHostBaseLibDisableInterrupts(VOID)
UINTN EFIAPI AsmWriteDr1(UINTN Dr1)
VOID EFIAPI AsmDisablePaging64(IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuid(IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
UINT16 EFIAPI AsmReadTr(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmDisableCache(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr4(UINTN Cr4)
STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr7(UINTN Dr7)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmMonitor(IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr2(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmMwait(IN UINTN Eax, IN UINTN Ecx)
VOID EFIAPI AsmReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
VOID EFIAPI UnitTestHostBaseLibAsmPrepareAndThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT16 EFIAPI AsmReadLdtr(VOID)
VOID EFIAPI AsmReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr1(VOID)
UINTN EFIAPI AsmWriteDr4(UINTN Dr4)
UINTN EFIAPI AsmReadDr1(VOID)
VOID EFIAPI AsmEnableCache(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWriteTr(IN UINT16 Selector)
UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib
VOID EFIAPI UnitTestHostBaseLibAsmPrepareThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
VOID EFIAPI AsmInvd(VOID)
UINTN EFIAPI AsmReadDr0(VOID)
UINT16 EFIAPI AsmReadFs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr2(UINTN Dr2)
UINTN EFIAPI AsmWriteDr7(UINTN Dr7)
UINT64 EFIAPI UnitTestHostBaseLibAsmReadPmc(IN UINT32 Index)
VOID EFIAPI UnitTestHostBaseLibAsmInvd(VOID)
UINTN EFIAPI AsmWriteDr3(UINTN Dr3)
UINT16 EFIAPI AsmReadEs(VOID)
UINTN EFIAPI AsmReadCr3(VOID)
STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr3(UINTN Cr3)
VOID EFIAPI AsmGetThunk16Properties(OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
UINTN EFIAPI AsmReadDr2(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadGs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr0(VOID)
VOID EFIAPI AsmWriteTr(IN UINT16 Selector)
VOID EFIAPI AsmPrepareThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINTN EFIAPI AsmWriteCr2(UINTN Cr2)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr2(UINTN Cr2)
UINT64 EFIAPI UnitTestHostBaseLibAsmReadMsr64(IN UINT32 Index)
UINTN EFIAPI AsmMonitor(IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)
VOID EFIAPI UnitTestHostBaseLibAsmLfence(VOID)
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadFs(VOID)
UINTN EFIAPI AsmMwait(IN UINTN Eax, IN UINTN Ecx)
VOID EFIAPI UnitTestHostBaseLibAsmThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadDs(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWbinvd(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr3(UINTN Dr3)
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging64(IN UINT16 Cs, IN UINT32 EntryPoint, IN UINT32 Context1 OPTIONAL, IN UINT32 Context2 OPTIONAL, IN UINT32 NewStack)
UINTN EFIAPI AsmWriteCr3(UINTN Cr3)
VOID EFIAPI UnitTestHostBaseLibAsmGetThunk16Properties(OUT UINT32 *RealModeBufferSize, OUT UINT32 *ExtraStackSize)
UINT32 EFIAPI UnitTestHostBaseLibAsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
VOID EFIAPI AsmDisablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr1(UINTN Dr1)
UINTN EFIAPI AsmWriteCr4(UINTN Cr4)
VOID EFIAPI AsmPrepareAndThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
UINT32 EFIAPI AsmCpuid(IN UINT32 Index, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
VOID EFIAPI UnitTestHostBaseLibAsmReadIdtr(OUT IA32_DESCRIPTOR *Idtr)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteCr0(UINTN Cr0)
VOID EFIAPI UnitTestHostBaseLibAsmEnableCache(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr4(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmReadGdtr(OUT IA32_DESCRIPTOR *Gdtr)
VOID EFIAPI UnitTestHostBaseLibAsmWriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
VOID EFIAPI AsmThunk16(IN OUT THUNK_CONTEXT *ThunkContext)
VOID EFIAPI AsmWbinvd(VOID)
VOID EFIAPI UnitTestHostBaseLibPatchInstructionX86(OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
VOID EFIAPI UnitTestHostBaseLibAsmWriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr7(VOID)
UINTN EFIAPI AsmReadCr0(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmDisablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr0(UINTN Dr0)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadLdtr(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmWriteDr2(UINTN Dr2)
UINT64 EFIAPI UnitTestHostBaseLibAsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINTN EFIAPI AsmWriteDr0(UINTN Dr0)
VOID EFIAPI AsmDisableCache(VOID)
UINT32 EFIAPI AsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Edx OPTIONAL)
UINT16 EFIAPI AsmReadGs(VOID)
UINTN EFIAPI AsmWriteCr0(UINTN Cr0)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr5(UINTN Dr5)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr5(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr2(VOID)
VOID *EFIAPI AsmFlushCacheLine(IN VOID *LinearAddress)
UINTN EFIAPI AsmWriteDr5(UINTN Dr5)
VOID EFIAPI AsmEnablePaging64(IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr0(VOID)
VOID EFIAPI AsmWriteGdtr(IN CONST IA32_DESCRIPTOR *Gdtr)
UINTN EFIAPI AsmReadCr2(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr4(UINTN Dr4)
UINT16 EFIAPI AsmReadSs(VOID)
UINT16 EFIAPI AsmReadCs(VOID)
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadEs(VOID)
UINTN EFIAPI AsmReadDr3(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadCr4(VOID)
VOID EFIAPI AsmWriteIdtr(IN CONST IA32_DESCRIPTOR *Idtr)
VOID EFIAPI AsmWriteLdtr(IN UINT16 Ldtr)
UINTN EFIAPI AsmReadCr4(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadTr(VOID)
UINTN EFIAPI AsmReadDr6(VOID)
UINTN EFIAPI AsmWriteDr6(UINTN Dr6)
UINT64 EFIAPI AsmReadPmc(IN UINT32 Index)
VOID EFIAPI AsmEnablePaging32(IN SWITCH_STACK_ENTRY_POINT EntryPoint, IN VOID *Context1 OPTIONAL, IN VOID *Context2 OPTIONAL, IN VOID *NewStack)
UINT16 EFIAPI AsmReadDs(VOID)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadSs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmWriteDr6(UINTN Dr6)
UINT16 EFIAPI UnitTestHostBaseLibAsmReadCs(VOID)
UINTN EFIAPI UnitTestHostBaseLibAsmReadDr6(VOID)
UINTN EFIAPI AsmReadDr4(VOID)
UINTN EFIAPI AsmReadDr7(VOID)
VOID EFIAPI UnitTestHostBaseLibAsmEnablePaging64(IN UINT16 Cs, IN UINT64 EntryPoint, IN UINT64 Context1 OPTIONAL, IN UINT64 Context2 OPTIONAL, IN UINT64 NewStack)
VOID *EFIAPI UnitTestHostBaseLibAsmFlushCacheLine(IN VOID *LinearAddress)
STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000]
UINTN EFIAPI AsmReadDr5(VOID)
VOID EFIAPI AsmLfence(VOID)
VOID EFIAPI PatchInstructionX86(OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize)
#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS