XeonE7Msr.h

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#ifndef __XEON_E7_MSR_H__
#define __XEON_E7_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x2F    \
    )                       \
   )
 
#define MSR_XEON_E7_FEATURE_CONFIG  0x0000013C
 
typedef union {
  struct {
    UINT32    AESConfiguration : 2;
    UINT32    Reserved1        : 30;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
 
#define MSR_XEON_E7_OFFCORE_RSP_1  0x000001A7
 
#define MSR_XEON_E7_TURBO_RATIO_LIMIT  0x000001AD
 
#define MSR_XEON_E7_C8_PMON_BOX_CTRL  0x00000F40
 
#define MSR_XEON_E7_C8_PMON_BOX_STATUS  0x00000F41
 
#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL  0x00000F42
 
#define MSR_XEON_E7_C8_PMON_EVNT_SEL0  0x00000F50
#define MSR_XEON_E7_C8_PMON_EVNT_SEL1  0x00000F52
#define MSR_XEON_E7_C8_PMON_EVNT_SEL2  0x00000F54
#define MSR_XEON_E7_C8_PMON_EVNT_SEL3  0x00000F56
#define MSR_XEON_E7_C8_PMON_EVNT_SEL4  0x00000F58
#define MSR_XEON_E7_C8_PMON_EVNT_SEL5  0x00000F5A
 
#define MSR_XEON_E7_C8_PMON_CTR0  0x00000F51
#define MSR_XEON_E7_C8_PMON_CTR1  0x00000F53
#define MSR_XEON_E7_C8_PMON_CTR2  0x00000F55
#define MSR_XEON_E7_C8_PMON_CTR3  0x00000F57
#define MSR_XEON_E7_C8_PMON_CTR4  0x00000F59
#define MSR_XEON_E7_C8_PMON_CTR5  0x00000F5B
 
#define MSR_XEON_E7_C9_PMON_BOX_CTRL  0x00000FC0
 
#define MSR_XEON_E7_C9_PMON_BOX_STATUS  0x00000FC1
 
#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL  0x00000FC2
 
#define MSR_XEON_E7_C9_PMON_EVNT_SEL0  0x00000FD0
#define MSR_XEON_E7_C9_PMON_EVNT_SEL1  0x00000FD2
#define MSR_XEON_E7_C9_PMON_EVNT_SEL2  0x00000FD4
#define MSR_XEON_E7_C9_PMON_EVNT_SEL3  0x00000FD6
#define MSR_XEON_E7_C9_PMON_EVNT_SEL4  0x00000FD8
#define MSR_XEON_E7_C9_PMON_EVNT_SEL5  0x00000FDA
 
#define MSR_XEON_E7_C9_PMON_CTR0  0x00000FD1
#define MSR_XEON_E7_C9_PMON_CTR1  0x00000FD3
#define MSR_XEON_E7_C9_PMON_CTR2  0x00000FD5
#define MSR_XEON_E7_C9_PMON_CTR3  0x00000FD7
#define MSR_XEON_E7_C9_PMON_CTR4  0x00000FD9
#define MSR_XEON_E7_C9_PMON_CTR5  0x00000FDB
 
#endif