TianoCore EDK2 master
XeonE7Msr.h
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1
18#ifndef __XEON_E7_MSR_H__
19#define __XEON_E7_MSR_H__
20
22
32#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x2F \
36 ) \
37 )
38
58#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C
59
63typedef union {
67 struct {
77 UINT32 AESConfiguration : 2;
78 UINT32 Reserved1 : 30;
79 UINT32 Reserved2 : 32;
80 } Bits;
84 UINT32 Uint32;
88 UINT64 Uint64;
90
107#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7
108
125#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD
126
143#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40
144
161#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41
162
179#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42
180
203#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50
204#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52
205#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54
206#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56
207#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58
208#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A
210
233#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51
234#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53
235#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55
236#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57
237#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59
238#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B
240
257#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0
258
275#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1
276
293#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2
294
317#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0
318#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2
319#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4
320#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6
321#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8
322#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA
324
347#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1
348#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3
349#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5
350#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7
351#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9
352#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB
354
355#endif