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Data Structures | Macros
XeonE7Msr.h File Reference
#include <Register/Intel/ArchitecturalMsr.h>

Go to the source code of this file.

Data Structures

union  MSR_XEON_E7_FEATURE_CONFIG_REGISTER
 

Macros

#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_XEON_E7_FEATURE_CONFIG   0x0000013C
 
#define MSR_XEON_E7_OFFCORE_RSP_1   0x000001A7
 
#define MSR_XEON_E7_TURBO_RATIO_LIMIT   0x000001AD
 
#define MSR_XEON_E7_C8_PMON_BOX_CTRL   0x00000F40
 
#define MSR_XEON_E7_C8_PMON_BOX_STATUS   0x00000F41
 
#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL   0x00000F42
 
#define MSR_XEON_E7_C9_PMON_BOX_CTRL   0x00000FC0
 
#define MSR_XEON_E7_C9_PMON_BOX_STATUS   0x00000FC1
 
#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL   0x00000FC2
 
#define MSR_XEON_E7_C8_PMON_EVNT_SEL0   0x00000F50
 
#define MSR_XEON_E7_C8_PMON_EVNT_SEL1   0x00000F52
 
#define MSR_XEON_E7_C8_PMON_EVNT_SEL2   0x00000F54
 
#define MSR_XEON_E7_C8_PMON_EVNT_SEL3   0x00000F56
 
#define MSR_XEON_E7_C8_PMON_EVNT_SEL4   0x00000F58
 
#define MSR_XEON_E7_C8_PMON_EVNT_SEL5   0x00000F5A
 
#define MSR_XEON_E7_C8_PMON_CTR0   0x00000F51
 
#define MSR_XEON_E7_C8_PMON_CTR1   0x00000F53
 
#define MSR_XEON_E7_C8_PMON_CTR2   0x00000F55
 
#define MSR_XEON_E7_C8_PMON_CTR3   0x00000F57
 
#define MSR_XEON_E7_C8_PMON_CTR4   0x00000F59
 
#define MSR_XEON_E7_C8_PMON_CTR5   0x00000F5B
 
#define MSR_XEON_E7_C9_PMON_EVNT_SEL0   0x00000FD0
 
#define MSR_XEON_E7_C9_PMON_EVNT_SEL1   0x00000FD2
 
#define MSR_XEON_E7_C9_PMON_EVNT_SEL2   0x00000FD4
 
#define MSR_XEON_E7_C9_PMON_EVNT_SEL3   0x00000FD6
 
#define MSR_XEON_E7_C9_PMON_EVNT_SEL4   0x00000FD8
 
#define MSR_XEON_E7_C9_PMON_EVNT_SEL5   0x00000FDA
 
#define MSR_XEON_E7_C9_PMON_CTR0   0x00000FD1
 
#define MSR_XEON_E7_C9_PMON_CTR1   0x00000FD3
 
#define MSR_XEON_E7_C9_PMON_CTR2   0x00000FD5
 
#define MSR_XEON_E7_C9_PMON_CTR3   0x00000FD7
 
#define MSR_XEON_E7_C9_PMON_CTR4   0x00000FD9
 
#define MSR_XEON_E7_C9_PMON_CTR5   0x00000FDB
 

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file XeonE7Msr.h.

Macro Definition Documentation

◆ IS_XEON_E7_PROCESSOR

#define IS_XEON_E7_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x2F \
) \
)

Is Intel(R) Xeon(R) Processor E7 Family?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.

Definition at line 32 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_BOX_CTRL

#define MSR_XEON_E7_C8_PMON_BOX_CTRL   0x00000F40

Package. Uncore C-box 8 perfmon local box control MSR.

Parameters
ECXMSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
AsmReadMsr64
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
AsmWriteMsr64
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
Definition: GccInlinePriv.c:100
MSR_XEON_E7_C8_PMON_BOX_CTRL
#define MSR_XEON_E7_C8_PMON_BOX_CTRL
Definition: XeonE7Msr.h:143
Note
MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.

Definition at line 143 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL

#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL   0x00000F42

Package. Uncore C-box 8 perfmon local box overflow control MSR.

Parameters
ECXMSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL
#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL
Definition: XeonE7Msr.h:179
Note
MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.

Definition at line 179 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_BOX_STATUS

#define MSR_XEON_E7_C8_PMON_BOX_STATUS   0x00000F41

Package. Uncore C-box 8 perfmon local box status MSR.

Parameters
ECXMSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
MSR_XEON_E7_C8_PMON_BOX_STATUS
#define MSR_XEON_E7_C8_PMON_BOX_STATUS
Definition: XeonE7Msr.h:161
Note
MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.

Definition at line 161 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_CTR0

#define MSR_XEON_E7_C8_PMON_CTR0   0x00000F51

Package. Uncore C-box 8 perfmon counter MSR.

Parameters
ECXMSR_XEON_E7_C8_PMON_CTRn
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
MSR_XEON_E7_C8_PMON_CTR0
#define MSR_XEON_E7_C8_PMON_CTR0
Definition: XeonE7Msr.h:233
Note
MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM. MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.

Definition at line 233 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_CTR1

#define MSR_XEON_E7_C8_PMON_CTR1   0x00000F53

Definition at line 234 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_CTR2

#define MSR_XEON_E7_C8_PMON_CTR2   0x00000F55

Definition at line 235 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_CTR3

#define MSR_XEON_E7_C8_PMON_CTR3   0x00000F57

Definition at line 236 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_CTR4

#define MSR_XEON_E7_C8_PMON_CTR4   0x00000F59

Definition at line 237 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_CTR5

#define MSR_XEON_E7_C8_PMON_CTR5   0x00000F5B

Definition at line 238 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_EVNT_SEL0

#define MSR_XEON_E7_C8_PMON_EVNT_SEL0   0x00000F50

Package. Uncore C-box 8 perfmon event select MSR.

Parameters
ECXMSR_XEON_E7_C8_PMON_EVNT_SELn
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
MSR_XEON_E7_C8_PMON_EVNT_SEL0
#define MSR_XEON_E7_C8_PMON_EVNT_SEL0
Definition: XeonE7Msr.h:203
Note
MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM. MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM. MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM. MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM. MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM. MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.

Definition at line 203 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_EVNT_SEL1

#define MSR_XEON_E7_C8_PMON_EVNT_SEL1   0x00000F52

Definition at line 204 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_EVNT_SEL2

#define MSR_XEON_E7_C8_PMON_EVNT_SEL2   0x00000F54

Definition at line 205 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_EVNT_SEL3

#define MSR_XEON_E7_C8_PMON_EVNT_SEL3   0x00000F56

Definition at line 206 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_EVNT_SEL4

#define MSR_XEON_E7_C8_PMON_EVNT_SEL4   0x00000F58

Definition at line 207 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C8_PMON_EVNT_SEL5

#define MSR_XEON_E7_C8_PMON_EVNT_SEL5   0x00000F5A

Definition at line 208 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_BOX_CTRL

#define MSR_XEON_E7_C9_PMON_BOX_CTRL   0x00000FC0

Package. Uncore C-box 9 perfmon local box control MSR.

Parameters
ECXMSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
MSR_XEON_E7_C9_PMON_BOX_CTRL
#define MSR_XEON_E7_C9_PMON_BOX_CTRL
Definition: XeonE7Msr.h:257
Note
MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.

Definition at line 257 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL

#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL   0x00000FC2

Package. Uncore C-box 9 perfmon local box overflow control MSR.

Parameters
ECXMSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL
#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL
Definition: XeonE7Msr.h:293
Note
MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.

Definition at line 293 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_BOX_STATUS

#define MSR_XEON_E7_C9_PMON_BOX_STATUS   0x00000FC1

Package. Uncore C-box 9 perfmon local box status MSR.

Parameters
ECXMSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
MSR_XEON_E7_C9_PMON_BOX_STATUS
#define MSR_XEON_E7_C9_PMON_BOX_STATUS
Definition: XeonE7Msr.h:275
Note
MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.

Definition at line 275 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_CTR0

#define MSR_XEON_E7_C9_PMON_CTR0   0x00000FD1

Package. Uncore C-box 9 perfmon counter MSR.

Parameters
ECXMSR_XEON_E7_C9_PMON_CTRn
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
MSR_XEON_E7_C9_PMON_CTR0
#define MSR_XEON_E7_C9_PMON_CTR0
Definition: XeonE7Msr.h:347
Note
MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM. MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.

Definition at line 347 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_CTR1

#define MSR_XEON_E7_C9_PMON_CTR1   0x00000FD3

Definition at line 348 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_CTR2

#define MSR_XEON_E7_C9_PMON_CTR2   0x00000FD5

Definition at line 349 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_CTR3

#define MSR_XEON_E7_C9_PMON_CTR3   0x00000FD7

Definition at line 350 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_CTR4

#define MSR_XEON_E7_C9_PMON_CTR4   0x00000FD9

Definition at line 351 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_CTR5

#define MSR_XEON_E7_C9_PMON_CTR5   0x00000FDB

Definition at line 352 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_EVNT_SEL0

#define MSR_XEON_E7_C9_PMON_EVNT_SEL0   0x00000FD0

Package. Uncore C-box 9 perfmon event select MSR.

Parameters
ECXMSR_XEON_E7_C9_PMON_EVNT_SELn
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
MSR_XEON_E7_C9_PMON_EVNT_SEL0
#define MSR_XEON_E7_C9_PMON_EVNT_SEL0
Definition: XeonE7Msr.h:317
Note
MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM. MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM. MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM. MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM. MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM. MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.

Definition at line 317 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_EVNT_SEL1

#define MSR_XEON_E7_C9_PMON_EVNT_SEL1   0x00000FD2

Definition at line 318 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_EVNT_SEL2

#define MSR_XEON_E7_C9_PMON_EVNT_SEL2   0x00000FD4

Definition at line 319 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_EVNT_SEL3

#define MSR_XEON_E7_C9_PMON_EVNT_SEL3   0x00000FD6

Definition at line 320 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_EVNT_SEL4

#define MSR_XEON_E7_C9_PMON_EVNT_SEL4   0x00000FD8

Definition at line 321 of file XeonE7Msr.h.

◆ MSR_XEON_E7_C9_PMON_EVNT_SEL5

#define MSR_XEON_E7_C9_PMON_EVNT_SEL5   0x00000FDA

Definition at line 322 of file XeonE7Msr.h.

◆ MSR_XEON_E7_FEATURE_CONFIG

#define MSR_XEON_E7_FEATURE_CONFIG   0x0000013C

Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

Parameters
ECXMSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.

Example usage

MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
MSR_XEON_E7_FEATURE_CONFIG
#define MSR_XEON_E7_FEATURE_CONFIG
Definition: XeonE7Msr.h:58
MSR_XEON_E7_FEATURE_CONFIG_REGISTER
Definition: XeonE7Msr.h:63
Note
MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.

Definition at line 58 of file XeonE7Msr.h.

◆ MSR_XEON_E7_OFFCORE_RSP_1

#define MSR_XEON_E7_OFFCORE_RSP_1   0x000001A7

Thread. Offcore Response Event Select Register (R/W).

Parameters
ECXMSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
MSR_XEON_E7_OFFCORE_RSP_1
#define MSR_XEON_E7_OFFCORE_RSP_1
Definition: XeonE7Msr.h:107
Note
MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.

Definition at line 107 of file XeonE7Msr.h.

◆ MSR_XEON_E7_TURBO_RATIO_LIMIT

#define MSR_XEON_E7_TURBO_RATIO_LIMIT   0x000001AD

Package. Reserved Attempt to read/write will cause #UD.

Parameters
ECXMSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
MSR_XEON_E7_TURBO_RATIO_LIMIT
#define MSR_XEON_E7_TURBO_RATIO_LIMIT
Definition: XeonE7Msr.h:125
Note
MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

Definition at line 125 of file XeonE7Msr.h.