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XhciSched.h
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1
10#ifndef _EFI_XHCI_SCHED_H_
11#define _EFI_XHCI_SCHED_H_
12
13#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
14#define XHC_INIT_DEVICE_SLOT_RETRIES 1
15
16//
17// Transfer types, used in URB to identify the transfer type
18//
19#define XHC_CTRL_TRANSFER 0x01
20#define XHC_BULK_TRANSFER 0x02
21#define XHC_INT_TRANSFER_SYNC 0x04
22#define XHC_INT_TRANSFER_ASYNC 0x08
23#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
24
25//
26// 6.4.6 TRB Types
27//
28#define TRB_TYPE_NORMAL 1
29#define TRB_TYPE_SETUP_STAGE 2
30#define TRB_TYPE_DATA_STAGE 3
31#define TRB_TYPE_STATUS_STAGE 4
32#define TRB_TYPE_ISOCH 5
33#define TRB_TYPE_LINK 6
34#define TRB_TYPE_EVENT_DATA 7
35#define TRB_TYPE_NO_OP 8
36#define TRB_TYPE_EN_SLOT 9
37#define TRB_TYPE_DIS_SLOT 10
38#define TRB_TYPE_ADDRESS_DEV 11
39#define TRB_TYPE_CON_ENDPOINT 12
40#define TRB_TYPE_EVALU_CONTXT 13
41#define TRB_TYPE_RESET_ENDPOINT 14
42#define TRB_TYPE_STOP_ENDPOINT 15
43#define TRB_TYPE_SET_TR_DEQUE 16
44#define TRB_TYPE_RESET_DEV 17
45#define TRB_TYPE_GET_PORT_BANW 21
46#define TRB_TYPE_FORCE_HEADER 22
47#define TRB_TYPE_NO_OP_COMMAND 23
48#define TRB_TYPE_TRANS_EVENT 32
49#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
50#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
51#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
52#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
53#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
54
55//
56// Endpoint Type (EP Type).
57//
58#define ED_NOT_VALID 0
59#define ED_ISOCH_OUT 1
60#define ED_BULK_OUT 2
61#define ED_INTERRUPT_OUT 3
62#define ED_CONTROL_BIDIR 4
63#define ED_ISOCH_IN 5
64#define ED_BULK_IN 6
65#define ED_INTERRUPT_IN 7
66
67//
68// 6.4.5 TRB Completion Codes
69//
70#define TRB_COMPLETION_INVALID 0
71#define TRB_COMPLETION_SUCCESS 1
72#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
73#define TRB_COMPLETION_BABBLE_ERROR 3
74#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
75#define TRB_COMPLETION_TRB_ERROR 5
76#define TRB_COMPLETION_STALL_ERROR 6
77#define TRB_COMPLETION_SHORT_PACKET 13
78#define TRB_COMPLETION_STOPPED 26
79#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
80
81//
82// USB Transfer Results Internal Definition
83// Based on XHCI spec 4.8.3, software should do the reset endpoint while USB Transaction occur.
84// Add the error code for USB Transaction error since UEFI spec don't have the related definition.
85//
86#define EDKII_USB_ERR_TRANSACTION 0x200
87
88//
89// The topology string used to present usb device location
90//
91typedef struct _USB_DEV_TOPOLOGY {
92 //
93 // The tier concatenation of down stream port.
94 //
95 UINT32 RouteString : 20;
96 //
97 // The root port number of the chain.
98 //
99 UINT32 RootPortNum : 8;
100 //
101 // The Tier the device reside.
102 //
103 UINT32 TierNum : 4;
104} USB_DEV_TOPOLOGY;
105
106//
107// USB Device's RouteChart
108//
109typedef union _USB_DEV_ROUTE {
110 UINT32 Dword;
111 USB_DEV_TOPOLOGY Route;
112} USB_DEV_ROUTE;
113
114//
115// Endpoint address and its capabilities
116//
117typedef struct _USB_ENDPOINT {
118 //
119 // Store logical device address assigned by UsbBus
120 // It's because some XHCI host controllers may assign the same physcial device
121 // address for those devices inserted at different root port.
122 //
123 UINT8 BusAddr;
124 UINT8 DevAddr;
125 UINT8 EpAddr;
126 EFI_USB_DATA_DIRECTION Direction;
127 UINT8 DevSpeed;
128 UINTN MaxPacket;
129 UINTN Type;
130} USB_ENDPOINT;
131
132//
133// TRB Template
134//
135typedef struct _TRB_TEMPLATE {
136 UINT32 Parameter1;
137
138 UINT32 Parameter2;
139
140 UINT32 Status;
141
142 UINT32 CycleBit : 1;
143 UINT32 RsvdZ1 : 9;
144 UINT32 Type : 6;
145 UINT32 Control : 16;
146} TRB_TEMPLATE;
147
148typedef struct _TRANSFER_RING {
149 VOID *RingSeg0;
150 UINTN TrbNumber;
151 TRB_TEMPLATE *RingEnqueue;
152 TRB_TEMPLATE *RingDequeue;
153 UINT32 RingPCS;
154} TRANSFER_RING;
155
156typedef struct _EVENT_RING {
157 VOID *ERSTBase;
158 VOID *EventRingSeg0;
159 UINTN TrbNumber;
160 TRB_TEMPLATE *EventRingEnqueue;
161 TRB_TEMPLATE *EventRingDequeue;
162 UINT32 EventRingCCS;
163} EVENT_RING;
164
165//
166// URB (Usb Request Block) contains information for all kinds of
167// usb requests.
168//
169typedef struct _URB {
170 UINT32 Signature;
171 LIST_ENTRY UrbList;
172 //
173 // Usb Device URB related information
174 //
175 USB_ENDPOINT Ep;
176 EFI_USB_DEVICE_REQUEST *Request;
177 VOID *Data;
178 UINTN DataLen;
179 VOID *DataPhy;
180 VOID *DataMap;
181 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
182 VOID *Context;
183 //
184 // Execute result
185 //
186 UINT32 Result;
187 //
188 // completed data length
189 //
190 UINTN Completed;
191 //
192 // Command/Tranfer Ring info
193 //
194 TRANSFER_RING *Ring;
195 TRB_TEMPLATE *TrbStart;
196 TRB_TEMPLATE *TrbEnd;
197 UINTN TrbNum;
198 BOOLEAN StartDone;
199 BOOLEAN EndDone;
200 BOOLEAN Finished;
201
202 TRB_TEMPLATE *EvtTrb;
203} URB;
204
205//
206// 6.5 Event Ring Segment Table
207// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
208// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
209// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
210// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
211//
212typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
213 UINT32 PtrLo;
214 UINT32 PtrHi;
215 UINT32 RingTrbSize : 16;
216 UINT32 RsvdZ1 : 16;
217 UINT32 RsvdZ2;
218} EVENT_RING_SEG_TABLE_ENTRY;
219
220//
221// 6.4.1.1 Normal TRB
222// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
223// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
224// Rings, and to define the Data stage information for Control Transfer Rings.
225//
226typedef struct _TRANSFER_TRB_NORMAL {
227 UINT32 TRBPtrLo;
228
229 UINT32 TRBPtrHi;
230
231 UINT32 Length : 17;
232 UINT32 TDSize : 5;
233 UINT32 IntTarget : 10;
234
235 UINT32 CycleBit : 1;
236 UINT32 ENT : 1;
237 UINT32 ISP : 1;
238 UINT32 NS : 1;
239 UINT32 CH : 1;
240 UINT32 IOC : 1;
241 UINT32 IDT : 1;
242 UINT32 RsvdZ1 : 2;
243 UINT32 BEI : 1;
244 UINT32 Type : 6;
245 UINT32 RsvdZ2 : 16;
246} TRANSFER_TRB_NORMAL;
247
248//
249// 6.4.1.2.1 Setup Stage TRB
250// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
251//
252typedef struct _TRANSFER_TRB_CONTROL_SETUP {
253 UINT32 bmRequestType : 8;
254 UINT32 bRequest : 8;
255 UINT32 wValue : 16;
256
257 UINT32 wIndex : 16;
258 UINT32 wLength : 16;
259
260 UINT32 Length : 17;
261 UINT32 RsvdZ1 : 5;
262 UINT32 IntTarget : 10;
263
264 UINT32 CycleBit : 1;
265 UINT32 RsvdZ2 : 4;
266 UINT32 IOC : 1;
267 UINT32 IDT : 1;
268 UINT32 RsvdZ3 : 3;
269 UINT32 Type : 6;
270 UINT32 TRT : 2;
271 UINT32 RsvdZ4 : 14;
272} TRANSFER_TRB_CONTROL_SETUP;
273
274//
275// 6.4.1.2.2 Data Stage TRB
276// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
277//
278typedef struct _TRANSFER_TRB_CONTROL_DATA {
279 UINT32 TRBPtrLo;
280
281 UINT32 TRBPtrHi;
282
283 UINT32 Length : 17;
284 UINT32 TDSize : 5;
285 UINT32 IntTarget : 10;
286
287 UINT32 CycleBit : 1;
288 UINT32 ENT : 1;
289 UINT32 ISP : 1;
290 UINT32 NS : 1;
291 UINT32 CH : 1;
292 UINT32 IOC : 1;
293 UINT32 IDT : 1;
294 UINT32 RsvdZ1 : 3;
295 UINT32 Type : 6;
296 UINT32 DIR : 1;
297 UINT32 RsvdZ2 : 15;
298} TRANSFER_TRB_CONTROL_DATA;
299
300//
301// 6.4.1.2.2 Data Stage TRB
302// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
303//
304typedef struct _TRANSFER_TRB_CONTROL_STATUS {
305 UINT32 RsvdZ1;
306 UINT32 RsvdZ2;
307
308 UINT32 RsvdZ3 : 22;
309 UINT32 IntTarget : 10;
310
311 UINT32 CycleBit : 1;
312 UINT32 ENT : 1;
313 UINT32 RsvdZ4 : 2;
314 UINT32 CH : 1;
315 UINT32 IOC : 1;
316 UINT32 RsvdZ5 : 4;
317 UINT32 Type : 6;
318 UINT32 DIR : 1;
319 UINT32 RsvdZ6 : 15;
320} TRANSFER_TRB_CONTROL_STATUS;
321
322//
323// 6.4.2.1 Transfer Event TRB
324// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
325// for more information on the use and operation of Transfer Events.
326//
327typedef struct _EVT_TRB_TRANSFER {
328 UINT32 TRBPtrLo;
329
330 UINT32 TRBPtrHi;
331
332 UINT32 Length : 24;
333 UINT32 Completecode : 8;
334
335 UINT32 CycleBit : 1;
336 UINT32 RsvdZ1 : 1;
337 UINT32 ED : 1;
338 UINT32 RsvdZ2 : 7;
339 UINT32 Type : 6;
340 UINT32 EndpointId : 5;
341 UINT32 RsvdZ3 : 3;
342 UINT32 SlotId : 8;
343} EVT_TRB_TRANSFER;
344
345//
346// 6.4.2.2 Command Completion Event TRB
347// A Command Completion Event TRB shall be generated by the xHC when a command completes on the
348// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
349//
350typedef struct _EVT_TRB_COMMAND_COMPLETION {
351 UINT32 TRBPtrLo;
352
353 UINT32 TRBPtrHi;
354
355 UINT32 RsvdZ2 : 24;
356 UINT32 Completecode : 8;
357
358 UINT32 CycleBit : 1;
359 UINT32 RsvdZ3 : 9;
360 UINT32 Type : 6;
361 UINT32 VFID : 8;
362 UINT32 SlotId : 8;
363} EVT_TRB_COMMAND_COMPLETION;
364
365typedef union _TRB {
366 TRB_TEMPLATE TrbTemplate;
367 TRANSFER_TRB_NORMAL TrbNormal;
368 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
369 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
370 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
371} TRB;
372
373//
374// 6.4.3.1 No Op Command TRB
375// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
376// mechanisms offered by the xHCI.
377//
378typedef struct _CMD_TRB_NO_OP {
379 UINT32 RsvdZ0;
380 UINT32 RsvdZ1;
381 UINT32 RsvdZ2;
382
383 UINT32 CycleBit : 1;
384 UINT32 RsvdZ3 : 9;
385 UINT32 Type : 6;
386 UINT32 RsvdZ4 : 16;
387} CMD_TRB_NO_OP;
388
389//
390// 6.4.3.2 Enable Slot Command TRB
391// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
392// selected slot to the host in a Command Completion Event.
393//
394typedef struct _CMD_TRB_ENABLE_SLOT {
395 UINT32 RsvdZ0;
396 UINT32 RsvdZ1;
397 UINT32 RsvdZ2;
398
399 UINT32 CycleBit : 1;
400 UINT32 RsvdZ3 : 9;
401 UINT32 Type : 6;
402 UINT32 RsvdZ4 : 16;
403} CMD_TRB_ENABLE_SLOT;
404
405//
406// 6.4.3.3 Disable Slot Command TRB
407// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
408// internal xHC resources assigned to the slot.
409//
410typedef struct _CMD_TRB_DISABLE_SLOT {
411 UINT32 RsvdZ0;
412 UINT32 RsvdZ1;
413 UINT32 RsvdZ2;
414
415 UINT32 CycleBit : 1;
416 UINT32 RsvdZ3 : 9;
417 UINT32 Type : 6;
418 UINT32 RsvdZ4 : 8;
419 UINT32 SlotId : 8;
420} CMD_TRB_DISABLE_SLOT;
421
422//
423// 6.4.3.4 Address Device Command TRB
424// The Address Device Command TRB transitions the selected Device Context from the Default to the
425// Addressed state and causes the xHC to select an address for the USB device in the Default State and
426// issue a SET_ADDRESS request to the USB device.
427//
428typedef struct _CMD_TRB_ADDRESS_DEVICE {
429 UINT32 PtrLo;
430
431 UINT32 PtrHi;
432
433 UINT32 RsvdZ1;
434
435 UINT32 CycleBit : 1;
436 UINT32 RsvdZ2 : 8;
437 UINT32 BSR : 1;
438 UINT32 Type : 6;
439 UINT32 RsvdZ3 : 8;
440 UINT32 SlotId : 8;
441} CMD_TRB_ADDRESS_DEVICE;
442
443//
444// 6.4.3.5 Configure Endpoint Command TRB
445// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
446// endpoints selected by the command.
447//
448typedef struct _CMD_TRB_CONFIG_ENDPOINT {
449 UINT32 PtrLo;
450
451 UINT32 PtrHi;
452
453 UINT32 RsvdZ1;
454
455 UINT32 CycleBit : 1;
456 UINT32 RsvdZ2 : 8;
457 UINT32 DC : 1;
458 UINT32 Type : 6;
459 UINT32 RsvdZ3 : 8;
460 UINT32 SlotId : 8;
461} CMD_TRB_CONFIG_ENDPOINT;
462
463//
464// 6.4.3.6 Evaluate Context Command TRB
465// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
466// Context data structures in the Device Context have been modified by system software and that the xHC
467// shall evaluate any changes
468//
469typedef struct _CMD_TRB_EVALUATE_CONTEXT {
470 UINT32 PtrLo;
471
472 UINT32 PtrHi;
473
474 UINT32 RsvdZ1;
475
476 UINT32 CycleBit : 1;
477 UINT32 RsvdZ2 : 9;
478 UINT32 Type : 6;
479 UINT32 RsvdZ3 : 8;
480 UINT32 SlotId : 8;
481} CMD_TRB_EVALUATE_CONTEXT;
482
483//
484// 6.4.3.7 Reset Endpoint Command TRB
485// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
486//
487typedef struct _CMD_TRB_RESET_ENDPOINT {
488 UINT32 RsvdZ0;
489 UINT32 RsvdZ1;
490 UINT32 RsvdZ2;
491
492 UINT32 CycleBit : 1;
493 UINT32 RsvdZ3 : 8;
494 UINT32 TSP : 1;
495 UINT32 Type : 6;
496 UINT32 EDID : 5;
497 UINT32 RsvdZ4 : 3;
498 UINT32 SlotId : 8;
499} CMD_TRB_RESET_ENDPOINT;
500
501//
502// 6.4.3.8 Stop Endpoint Command TRB
503// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
504// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
505//
506typedef struct _CMD_TRB_STOP_ENDPOINT {
507 UINT32 RsvdZ0;
508 UINT32 RsvdZ1;
509 UINT32 RsvdZ2;
510
511 UINT32 CycleBit : 1;
512 UINT32 RsvdZ3 : 9;
513 UINT32 Type : 6;
514 UINT32 EDID : 5;
515 UINT32 RsvdZ4 : 2;
516 UINT32 SP : 1;
517 UINT32 SlotId : 8;
518} CMD_TRB_STOP_ENDPOINT;
519
520//
521// 6.4.3.9 Set TR Dequeue Pointer Command TRB
522// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
523// Pointer and DCS fields of an Endpoint or Stream Context.
524//
525typedef struct _CMD_SET_TR_DEQ_POINTER {
526 UINT32 PtrLo;
527
528 UINT32 PtrHi;
529
530 UINT32 RsvdZ1 : 16;
531 UINT32 StreamID : 16;
532
533 UINT32 CycleBit : 1;
534 UINT32 RsvdZ2 : 9;
535 UINT32 Type : 6;
536 UINT32 Endpoint : 5;
537 UINT32 RsvdZ3 : 3;
538 UINT32 SlotId : 8;
539} CMD_SET_TR_DEQ_POINTER;
540
541//
542// 6.4.4.1 Link TRB
543// A Link TRB provides support for non-contiguous TRB Rings.
544//
545typedef struct _LINK_TRB {
546 UINT32 PtrLo;
547
548 UINT32 PtrHi;
549
550 UINT32 RsvdZ1 : 22;
551 UINT32 InterTarget : 10;
552
553 UINT32 CycleBit : 1;
554 UINT32 TC : 1;
555 UINT32 RsvdZ2 : 2;
556 UINT32 CH : 1;
557 UINT32 IOC : 1;
558 UINT32 RsvdZ3 : 4;
559 UINT32 Type : 6;
560 UINT32 RsvdZ4 : 16;
561} LINK_TRB;
562
563//
564// 6.2.2 Slot Context
565//
566typedef struct _SLOT_CONTEXT {
567 UINT32 RouteString : 20;
568 UINT32 Speed : 4;
569 UINT32 RsvdZ1 : 1;
570 UINT32 MTT : 1;
571 UINT32 Hub : 1;
572 UINT32 ContextEntries : 5;
573
574 UINT32 MaxExitLatency : 16;
575 UINT32 RootHubPortNum : 8;
576 UINT32 PortNum : 8;
577
578 UINT32 TTHubSlotId : 8;
579 UINT32 TTPortNum : 8;
580 UINT32 TTT : 2;
581 UINT32 RsvdZ2 : 4;
582 UINT32 InterTarget : 10;
583
584 UINT32 DeviceAddress : 8;
585 UINT32 RsvdZ3 : 19;
586 UINT32 SlotState : 5;
587
588 UINT32 RsvdZ4;
589 UINT32 RsvdZ5;
590 UINT32 RsvdZ6;
591 UINT32 RsvdZ7;
592} SLOT_CONTEXT;
593
594typedef struct _SLOT_CONTEXT_64 {
595 UINT32 RouteString : 20;
596 UINT32 Speed : 4;
597 UINT32 RsvdZ1 : 1;
598 UINT32 MTT : 1;
599 UINT32 Hub : 1;
600 UINT32 ContextEntries : 5;
601
602 UINT32 MaxExitLatency : 16;
603 UINT32 RootHubPortNum : 8;
604 UINT32 PortNum : 8;
605
606 UINT32 TTHubSlotId : 8;
607 UINT32 TTPortNum : 8;
608 UINT32 TTT : 2;
609 UINT32 RsvdZ2 : 4;
610 UINT32 InterTarget : 10;
611
612 UINT32 DeviceAddress : 8;
613 UINT32 RsvdZ3 : 19;
614 UINT32 SlotState : 5;
615
616 UINT32 RsvdZ4;
617 UINT32 RsvdZ5;
618 UINT32 RsvdZ6;
619 UINT32 RsvdZ7;
620
621 UINT32 RsvdZ8;
622 UINT32 RsvdZ9;
623 UINT32 RsvdZ10;
624 UINT32 RsvdZ11;
625
626 UINT32 RsvdZ12;
627 UINT32 RsvdZ13;
628 UINT32 RsvdZ14;
629 UINT32 RsvdZ15;
630} SLOT_CONTEXT_64;
631
632//
633// 6.2.3 Endpoint Context
634//
635typedef struct _ENDPOINT_CONTEXT {
636 UINT32 EPState : 3;
637 UINT32 RsvdZ1 : 5;
638 UINT32 Mult : 2;
639 UINT32 MaxPStreams : 5;
640 UINT32 LSA : 1;
641 UINT32 Interval : 8;
642 UINT32 RsvdZ2 : 8;
643
644 UINT32 RsvdZ3 : 1;
645 UINT32 CErr : 2;
646 UINT32 EPType : 3;
647 UINT32 RsvdZ4 : 1;
648 UINT32 HID : 1;
649 UINT32 MaxBurstSize : 8;
650 UINT32 MaxPacketSize : 16;
651
652 UINT32 PtrLo;
653
654 UINT32 PtrHi;
655
656 UINT32 AverageTRBLength : 16;
657 UINT32 MaxESITPayload : 16;
658
659 UINT32 RsvdZ5;
660 UINT32 RsvdZ6;
661 UINT32 RsvdZ7;
662} ENDPOINT_CONTEXT;
663
664typedef struct _ENDPOINT_CONTEXT_64 {
665 UINT32 EPState : 3;
666 UINT32 RsvdZ1 : 5;
667 UINT32 Mult : 2;
668 UINT32 MaxPStreams : 5;
669 UINT32 LSA : 1;
670 UINT32 Interval : 8;
671 UINT32 RsvdZ2 : 8;
672
673 UINT32 RsvdZ3 : 1;
674 UINT32 CErr : 2;
675 UINT32 EPType : 3;
676 UINT32 RsvdZ4 : 1;
677 UINT32 HID : 1;
678 UINT32 MaxBurstSize : 8;
679 UINT32 MaxPacketSize : 16;
680
681 UINT32 PtrLo;
682
683 UINT32 PtrHi;
684
685 UINT32 AverageTRBLength : 16;
686 UINT32 MaxESITPayload : 16;
687
688 UINT32 RsvdZ5;
689 UINT32 RsvdZ6;
690 UINT32 RsvdZ7;
691
692 UINT32 RsvdZ8;
693 UINT32 RsvdZ9;
694 UINT32 RsvdZ10;
695 UINT32 RsvdZ11;
696
697 UINT32 RsvdZ12;
698 UINT32 RsvdZ13;
699 UINT32 RsvdZ14;
700 UINT32 RsvdZ15;
701} ENDPOINT_CONTEXT_64;
702
703//
704// 6.2.5.1 Input Control Context
705//
706typedef struct _INPUT_CONTRL_CONTEXT {
707 UINT32 Dword1;
708 UINT32 Dword2;
709 UINT32 RsvdZ1;
710 UINT32 RsvdZ2;
711 UINT32 RsvdZ3;
712 UINT32 RsvdZ4;
713 UINT32 RsvdZ5;
714 UINT32 RsvdZ6;
715} INPUT_CONTRL_CONTEXT;
716
717typedef struct _INPUT_CONTRL_CONTEXT_64 {
718 UINT32 Dword1;
719 UINT32 Dword2;
720 UINT32 RsvdZ1;
721 UINT32 RsvdZ2;
722 UINT32 RsvdZ3;
723 UINT32 RsvdZ4;
724 UINT32 RsvdZ5;
725 UINT32 RsvdZ6;
726 UINT32 RsvdZ7;
727 UINT32 RsvdZ8;
728 UINT32 RsvdZ9;
729 UINT32 RsvdZ10;
730 UINT32 RsvdZ11;
731 UINT32 RsvdZ12;
732 UINT32 RsvdZ13;
733 UINT32 RsvdZ14;
734} INPUT_CONTRL_CONTEXT_64;
735
736//
737// 6.2.1 Device Context
738//
739typedef struct _DEVICE_CONTEXT {
740 SLOT_CONTEXT Slot;
741 ENDPOINT_CONTEXT EP[31];
742} DEVICE_CONTEXT;
743
744typedef struct _DEVICE_CONTEXT_64 {
745 SLOT_CONTEXT_64 Slot;
746 ENDPOINT_CONTEXT_64 EP[31];
747} DEVICE_CONTEXT_64;
748
749//
750// 6.2.5 Input Context
751//
752typedef struct _INPUT_CONTEXT {
753 INPUT_CONTRL_CONTEXT InputControlContext;
754 SLOT_CONTEXT Slot;
755 ENDPOINT_CONTEXT EP[31];
756} INPUT_CONTEXT;
757
758typedef struct _INPUT_CONTEXT_64 {
759 INPUT_CONTRL_CONTEXT_64 InputControlContext;
760 SLOT_CONTEXT_64 Slot;
761 ENDPOINT_CONTEXT_64 EP[31];
762} INPUT_CONTEXT_64;
763
770VOID
771XhcInitSched (
772 IN USB_XHCI_INSTANCE *Xhc
773 );
774
781VOID
782XhcFreeSched (
783 IN USB_XHCI_INSTANCE *Xhc
784 );
785
795EFI_STATUS
796RingIntTransferDoorBell (
797 IN USB_XHCI_INSTANCE *Xhc,
798 IN URB *Urb
799 );
800
814EFI_STATUS
815XhcExecTransfer (
816 IN USB_XHCI_INSTANCE *Xhc,
817 IN BOOLEAN CmdTransfer,
818 IN URB *Urb,
819 IN UINTN Timeout
820 );
821
834EFI_STATUS
835XhciDelAsyncIntTransfer (
836 IN USB_XHCI_INSTANCE *Xhc,
837 IN UINT8 BusAddr,
838 IN UINT8 EpNum
839 );
840
847VOID
848XhciDelAllAsyncIntTransfers (
849 IN USB_XHCI_INSTANCE *Xhc
850 );
851
868URB *
869XhciInsertAsyncIntTransfer (
870 IN USB_XHCI_INSTANCE *Xhc,
871 IN UINT8 BusAddr,
872 IN UINT8 EpAddr,
873 IN UINT8 DevSpeed,
874 IN UINTN MaxPacket,
875 IN UINTN DataLen,
876 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
877 IN VOID *Context
878 );
879
886VOID
887XhcSetBiosOwnership (
888 IN USB_XHCI_INSTANCE *Xhc
889 );
890
897VOID
898XhcClearBiosOwnership (
899 IN USB_XHCI_INSTANCE *Xhc
900 );
901
911UINT8
912EFIAPI
913XhcRouteStringToSlotId (
914 IN USB_XHCI_INSTANCE *Xhc,
915 IN USB_DEV_ROUTE RouteString
916 );
917
927UINT8
928XhcEndpointToDci (
929 IN UINT8 EpAddr,
930 IN UINT8 Direction
931 );
932
943EFI_STATUS
944EFIAPI
945XhcRingDoorBell (
946 IN USB_XHCI_INSTANCE *Xhc,
947 IN UINT8 SlotId,
948 IN UINT8 Dci
949 );
950
958VOID
959EFIAPI
960XhcMonitorAsyncRequests (
961 IN EFI_EVENT Event,
962 IN VOID *Context
963 );
964
977EFI_STATUS
978EFIAPI
979XhcPollPortStatusChange (
980 IN USB_XHCI_INSTANCE *Xhc,
981 IN USB_DEV_ROUTE ParentRouteChart,
982 IN UINT8 Port,
983 IN EFI_USB_PORT_STATUS *PortState
984 );
985
998EFI_STATUS
999XhcConfigHubContext (
1000 IN USB_XHCI_INSTANCE *Xhc,
1001 IN UINT8 SlotId,
1002 IN UINT8 PortNum,
1003 IN UINT8 TTT,
1004 IN UINT8 MTT
1005 );
1006
1019EFI_STATUS
1020XhcConfigHubContext64 (
1021 IN USB_XHCI_INSTANCE *Xhc,
1022 IN UINT8 SlotId,
1023 IN UINT8 PortNum,
1024 IN UINT8 TTT,
1025 IN UINT8 MTT
1026 );
1027
1039EFI_STATUS
1040EFIAPI
1041XhcSetConfigCmd (
1042 IN USB_XHCI_INSTANCE *Xhc,
1043 IN UINT8 SlotId,
1044 IN UINT8 DeviceSpeed,
1045 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1046 );
1047
1059EFI_STATUS
1060EFIAPI
1061XhcSetConfigCmd64 (
1062 IN USB_XHCI_INSTANCE *Xhc,
1063 IN UINT8 SlotId,
1064 IN UINT8 DeviceSpeed,
1065 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1066 );
1067
1080EFI_STATUS
1081EFIAPI
1082XhcSetInterface (
1083 IN USB_XHCI_INSTANCE *Xhc,
1084 IN UINT8 SlotId,
1085 IN UINT8 DeviceSpeed,
1086 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
1087 IN EFI_USB_DEVICE_REQUEST *Request
1088 );
1089
1102EFI_STATUS
1103EFIAPI
1104XhcSetInterface64 (
1105 IN USB_XHCI_INSTANCE *Xhc,
1106 IN UINT8 SlotId,
1107 IN UINT8 DeviceSpeed,
1108 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
1109 IN EFI_USB_DEVICE_REQUEST *Request
1110 );
1111
1121UINT8
1122EFIAPI
1123XhcBusDevAddrToSlotId (
1124 IN USB_XHCI_INSTANCE *Xhc,
1125 IN UINT8 BusDevAddr
1126 );
1127
1140EFI_STATUS
1141EFIAPI
1142XhcInitializeDeviceSlot (
1143 IN USB_XHCI_INSTANCE *Xhc,
1144 IN USB_DEV_ROUTE ParentRouteChart,
1145 IN UINT16 ParentPort,
1146 IN USB_DEV_ROUTE RouteChart,
1147 IN UINT8 DeviceSpeed
1148 );
1149
1162EFI_STATUS
1163EFIAPI
1164XhcInitializeDeviceSlot64 (
1165 IN USB_XHCI_INSTANCE *Xhc,
1166 IN USB_DEV_ROUTE ParentRouteChart,
1167 IN UINT16 ParentPort,
1168 IN USB_DEV_ROUTE RouteChart,
1169 IN UINT8 DeviceSpeed
1170 );
1171
1182EFI_STATUS
1183EFIAPI
1184XhcEvaluateContext (
1185 IN USB_XHCI_INSTANCE *Xhc,
1186 IN UINT8 SlotId,
1187 IN UINT32 MaxPacketSize
1188 );
1189
1200EFI_STATUS
1201EFIAPI
1202XhcEvaluateContext64 (
1203 IN USB_XHCI_INSTANCE *Xhc,
1204 IN UINT8 SlotId,
1205 IN UINT32 MaxPacketSize
1206 );
1207
1217EFI_STATUS
1218EFIAPI
1219XhcDisableSlotCmd (
1220 IN USB_XHCI_INSTANCE *Xhc,
1221 IN UINT8 SlotId
1222 );
1223
1233EFI_STATUS
1234EFIAPI
1235XhcDisableSlotCmd64 (
1236 IN USB_XHCI_INSTANCE *Xhc,
1237 IN UINT8 SlotId
1238 );
1239
1249EFI_STATUS
1250EFIAPI
1251XhcSyncTrsRing (
1252 IN USB_XHCI_INSTANCE *Xhc,
1253 TRANSFER_RING *TrsRing
1254 );
1255
1265EFI_STATUS
1266EFIAPI
1267XhcSyncEventRing (
1268 IN USB_XHCI_INSTANCE *Xhc,
1269 EVENT_RING *EvtRing
1270 );
1271
1283EFI_STATUS
1284EFIAPI
1285XhcCheckNewEvent (
1286 IN USB_XHCI_INSTANCE *Xhc,
1287 IN EVENT_RING *EvtRing,
1288 OUT TRB_TEMPLATE **NewEvtTrb
1289 );
1290
1299VOID
1300CreateTransferRing (
1301 IN USB_XHCI_INSTANCE *Xhc,
1302 IN UINTN TrbNum,
1303 OUT TRANSFER_RING *TransferRing
1304 );
1305
1313VOID
1314CreateEventRing (
1315 IN USB_XHCI_INSTANCE *Xhc,
1316 OUT EVENT_RING *EventRing
1317 );
1318
1333EFI_STATUS
1334EFIAPI
1335XhcRecoverHaltedEndpoint (
1336 IN USB_XHCI_INSTANCE *Xhc,
1337 IN URB *Urb
1338 );
1339
1353EFI_STATUS
1354EFIAPI
1355XhcDequeueTrbFromEndpoint (
1356 IN USB_XHCI_INSTANCE *Xhc,
1357 IN URB *Urb
1358 );
1359
1372EFI_STATUS
1373EFIAPI
1374XhcStopEndpoint (
1375 IN USB_XHCI_INSTANCE *Xhc,
1376 IN UINT8 SlotId,
1377 IN UINT8 Dci,
1378 IN URB *PendingUrb OPTIONAL
1379 );
1380
1392EFI_STATUS
1393EFIAPI
1394XhcResetEndpoint (
1395 IN USB_XHCI_INSTANCE *Xhc,
1396 IN UINT8 SlotId,
1397 IN UINT8 Dci
1398 );
1399
1413EFI_STATUS
1414EFIAPI
1415XhcSetTrDequeuePointer (
1416 IN USB_XHCI_INSTANCE *Xhc,
1417 IN UINT8 SlotId,
1418 IN UINT8 Dci,
1419 IN URB *Urb
1420 );
1421
1440URB *
1441XhcCreateUrb (
1442 IN USB_XHCI_INSTANCE *Xhc,
1443 IN UINT8 DevAddr,
1444 IN UINT8 EpAddr,
1445 IN UINT8 DevSpeed,
1446 IN UINTN MaxPacket,
1447 IN UINTN Type,
1448 IN EFI_USB_DEVICE_REQUEST *Request,
1449 IN VOID *Data,
1450 IN UINTN DataLen,
1451 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1452 IN VOID *Context
1453 );
1454
1462VOID
1463XhcFreeUrb (
1464 IN USB_XHCI_INSTANCE *Xhc,
1465 IN URB *Urb
1466 );
1467
1477EFI_STATUS
1478XhcCreateTransferTrb (
1479 IN USB_XHCI_INSTANCE *Xhc,
1480 IN URB *Urb
1481 );
1482
1483#endif
UINTN
UINT64 UINTN
Definition: ProcessorBind.h:112
IN
#define IN
Definition: Base.h:279
OUT
#define OUT
Definition: Base.h:284
EFI_USB_DATA_DIRECTION
EFI_USB_DATA_DIRECTION
Definition: UsbIo.h:44
EFI_ASYNC_USB_TRANSFER_CALLBACK
EFI_STATUS(EFIAPI * EFI_ASYNC_USB_TRANSFER_CALLBACK)(IN VOID *Data, IN UINTN DataLength, IN VOID *Context, IN UINT32 Status)
Definition: UsbIo.h:80
EFI_STATUS
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
EFI_EVENT
VOID * EFI_EVENT
Definition: UefiBaseType.h:37
XhcSetConfigCmd64
EFI_STATUS EFIAPI XhcSetConfigCmd64(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 DeviceSpeed, IN USB_CONFIG_DESCRIPTOR *ConfigDesc)
Definition: XhciSched.c:3323
XhciInsertAsyncIntTransfer
URB * XhciInsertAsyncIntTransfer(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 BusAddr, IN UINT8 EpAddr, IN UINT8 DevSpeed, IN UINTN MaxPacket, IN UINTN DataLen, IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback, IN VOID *Context)
Definition: XhciSched.c:1474
XhcDisableSlotCmd
EFI_STATUS EFIAPI XhcDisableSlotCmd(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId)
Definition: XhciSched.c:2596
XhcInitializeDeviceSlot64
EFI_STATUS EFIAPI XhcInitializeDeviceSlot64(IN USB_XHCI_INSTANCE *Xhc, IN USB_DEV_ROUTE ParentRouteChart, IN UINT16 ParentPort, IN USB_DEV_ROUTE RouteChart, IN UINT8 DeviceSpeed)
Definition: XhciSched.c:2373
XhciDelAllAsyncIntTransfers
VOID XhciDelAllAsyncIntTransfers(IN USB_XHCI_INSTANCE *Xhc)
Definition: XhciSched.c:1430
XhcClearBiosOwnership
VOID XhcClearBiosOwnership(IN USB_XHCI_INSTANCE *Xhc)
Definition: XhciReg.c:503
CreateEventRing
VOID CreateEventRing(IN USB_XHCI_INSTANCE *Xhc, OUT EVENT_RING *EventRing)
Definition: XhciSched.c:789
XhcFreeUrb
VOID XhcFreeUrb(IN USB_XHCI_INSTANCE *Xhc, IN URB *Urb)
Definition: XhciSched.c:192
XhcSetTrDequeuePointer
EFI_STATUS EFIAPI XhcSetTrDequeuePointer(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 Dci, IN URB *Urb)
Definition: XhciSched.c:3541
XhcResetEndpoint
EFI_STATUS EFIAPI XhcResetEndpoint(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 Dci)
Definition: XhciSched.c:3491
XhciDelAsyncIntTransfer
EFI_STATUS XhciDelAsyncIntTransfer(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 BusAddr, IN UINT8 EpNum)
Definition: XhciSched.c:1381
XhcConfigHubContext64
EFI_STATUS XhcConfigHubContext64(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 PortNum, IN UINT8 TTT, IN UINT8 MTT)
Definition: XhciSched.c:4204
XhcSyncEventRing
EFI_STATUS EFIAPI XhcSyncEventRing(IN USB_XHCI_INSTANCE *Xhc, EVENT_RING *EvtRing)
XhcFreeSched
VOID XhcFreeSched(IN USB_XHCI_INSTANCE *Xhc)
Definition: XhciSched.c:967
XhcSetInterface64
EFI_STATUS EFIAPI XhcSetInterface64(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 DeviceSpeed, IN USB_CONFIG_DESCRIPTOR *ConfigDesc, IN EFI_USB_DEVICE_REQUEST *Request)
Definition: XhciSched.c:3802
XhcCheckNewEvent
EFI_STATUS EFIAPI XhcCheckNewEvent(IN USB_XHCI_INSTANCE *Xhc, IN EVENT_RING *EvtRing, OUT TRB_TEMPLATE **NewEvtTrb)
Definition: XhciSched.c:2037
XhcRecoverHaltedEndpoint
EFI_STATUS EFIAPI XhcRecoverHaltedEndpoint(IN USB_XHCI_INSTANCE *Xhc, IN URB *Urb)
Definition: XhciSched.c:661
XhcSyncTrsRing
EFI_STATUS EFIAPI XhcSyncTrsRing(IN USB_XHCI_INSTANCE *Xhc, TRANSFER_RING *TrsRing)
XhcMonitorAsyncRequests
VOID EFIAPI XhcMonitorAsyncRequests(IN EFI_EVENT Event, IN VOID *Context)
Definition: XhciSched.c:1614
CreateTransferRing
VOID CreateTransferRing(IN USB_XHCI_INSTANCE *Xhc, IN UINTN TrbNum, OUT TRANSFER_RING *TransferRing)
Definition: XhciSched.c:890
XhcSetBiosOwnership
VOID XhcSetBiosOwnership(IN USB_XHCI_INSTANCE *Xhc)
Definition: XhciReg.c:479
XhcCreateTransferTrb
EFI_STATUS XhcCreateTransferTrb(IN USB_XHCI_INSTANCE *Xhc, IN URB *Urb)
Definition: XhciSched.c:218
XhcDequeueTrbFromEndpoint
EFI_STATUS EFIAPI XhcDequeueTrbFromEndpoint(IN USB_XHCI_INSTANCE *Xhc, IN URB *Urb)
Definition: XhciSched.c:724
XhcEndpointToDci
UINT8 XhcEndpointToDci(IN UINT8 EpAddr, IN UINT8 Direction)
Definition: XhciSched.c:1823
XhcEvaluateContext64
EFI_STATUS EFIAPI XhcEvaluateContext64(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT32 MaxPacketSize)
Definition: XhciSched.c:4070
XhcInitSched
VOID XhcInitSched(IN USB_XHCI_INSTANCE *Xhc)
Definition: XhciSched.c:475
RingIntTransferDoorBell
EFI_STATUS RingIntTransferDoorBell(IN USB_XHCI_INSTANCE *Xhc, IN URB *Urb)
Definition: XhciSched.c:2099
XhcRingDoorBell
EFI_STATUS EFIAPI XhcRingDoorBell(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 Dci)
Definition: XhciSched.c:2074
XhcConfigHubContext
EFI_STATUS XhcConfigHubContext(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 PortNum, IN UINT8 TTT, IN UINT8 MTT)
Definition: XhciSched.c:4134
XhcEvaluateContext
EFI_STATUS EFIAPI XhcEvaluateContext(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT32 MaxPacketSize)
Definition: XhciSched.c:4007
XhcStopEndpoint
EFI_STATUS EFIAPI XhcStopEndpoint(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 Dci, IN URB *PendingUrb OPTIONAL)
Definition: XhciSched.c:3417
XhcExecTransfer
EFI_STATUS XhcExecTransfer(IN USB_XHCI_INSTANCE *Xhc, IN BOOLEAN CmdTransfer, IN URB *Urb, IN UINTN Timeout)
Definition: XhciSched.c:1294
XhcSetConfigCmd
EFI_STATUS EFIAPI XhcSetConfigCmd(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 DeviceSpeed, IN USB_CONFIG_DESCRIPTOR *ConfigDesc)
Definition: XhciSched.c:3230
XhcInitializeDeviceSlot
EFI_STATUS EFIAPI XhcInitializeDeviceSlot(IN USB_XHCI_INSTANCE *Xhc, IN USB_DEV_ROUTE ParentRouteChart, IN UINT16 ParentPort, IN USB_DEV_ROUTE RouteChart, IN UINT8 DeviceSpeed)
Definition: XhciSched.c:2147
XhcCreateUrb
URB * XhcCreateUrb(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 DevAddr, IN UINT8 EpAddr, IN UINT8 DevSpeed, IN UINTN MaxPacket, IN UINTN Type, IN EFI_USB_DEVICE_REQUEST *Request, IN VOID *Data, IN UINTN DataLen, IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback, IN VOID *Context)
Definition: XhciSched.c:134
XhcRouteStringToSlotId
UINT8 EFIAPI XhcRouteStringToSlotId(IN USB_XHCI_INSTANCE *Xhc, IN USB_DEV_ROUTE RouteString)
Definition: XhciSched.c:1887
XhcDisableSlotCmd64
EFI_STATUS EFIAPI XhcDisableSlotCmd64(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId)
Definition: XhciSched.c:2709
XhcBusDevAddrToSlotId
UINT8 EFIAPI XhcBusDevAddrToSlotId(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 BusDevAddr)
Definition: XhciSched.c:1853
XhcPollPortStatusChange
EFI_STATUS EFIAPI XhcPollPortStatusChange(IN USB_XHCI_INSTANCE *Xhc, IN USB_DEV_ROUTE ParentRouteChart, IN UINT8 Port, IN EFI_USB_PORT_STATUS *PortState)
Definition: XhciSched.c:1727
XhcSetInterface
EFI_STATUS EFIAPI XhcSetInterface(IN USB_XHCI_INSTANCE *Xhc, IN UINT8 SlotId, IN UINT8 DeviceSpeed, IN USB_CONFIG_DESCRIPTOR *ConfigDesc, IN EFI_USB_DEVICE_REQUEST *Request)
Definition: XhciSched.c:3595
_CMD_SET_TR_DEQ_POINTER
Definition: XhciSched.h:525
_CMD_TRB_ADDRESS_DEVICE
Definition: XhciSched.h:428
_CMD_TRB_CONFIG_ENDPOINT
Definition: XhciSched.h:448
_CMD_TRB_DISABLE_SLOT
Definition: XhciSched.h:410
_CMD_TRB_ENABLE_SLOT
Definition: XhciSched.h:394
_CMD_TRB_EVALUATE_CONTEXT
Definition: XhciSched.h:469
_CMD_TRB_NO_OP
Definition: XhciSched.h:378
_CMD_TRB_RESET_ENDPOINT
Definition: XhciSched.h:487
_CMD_TRB_STOP_ENDPOINT
Definition: XhciSched.h:506
_DEVICE_CONTEXT_64
Definition: XhciSched.h:744
_DEVICE_CONTEXT
Definition: XhciSched.h:739
_ENDPOINT_CONTEXT_64
Definition: XhciSched.h:664
_ENDPOINT_CONTEXT
Definition: XhciSched.h:635
_EVENT_RING_SEG_TABLE_ENTRY
Definition: XhciSched.h:212
_EVENT_RING
Definition: XhciSched.h:156
_EVT_TRB_COMMAND_COMPLETION
Definition: XhciSched.h:350
_EVT_TRB_TRANSFER
Definition: XhciSched.h:327
_INPUT_CONTEXT_64
Definition: XhciSched.h:758
_INPUT_CONTEXT
Definition: XhciSched.h:752
_INPUT_CONTRL_CONTEXT_64
Definition: XhciSched.h:717
_INPUT_CONTRL_CONTEXT
Definition: XhciSched.h:706
_LINK_TRB
Definition: XhciSched.h:545
_LIST_ENTRY
Definition: Base.h:247
_SLOT_CONTEXT_64
Definition: XhciSched.h:594
_SLOT_CONTEXT
Definition: XhciSched.h:566
_TRANSFER_RING
Definition: XhciSched.h:148
_TRANSFER_TRB_CONTROL_DATA
Definition: XhciSched.h:278
_TRANSFER_TRB_CONTROL_SETUP
Definition: XhciSched.h:252
_TRANSFER_TRB_CONTROL_STATUS
Definition: XhciSched.h:304
_TRANSFER_TRB_NORMAL
Definition: XhciSched.h:226
_TRB_TEMPLATE
Definition: XhciSched.h:135
_URB
Definition: EhciUrb.h:200
_USB_DEV_TOPOLOGY
Definition: XhciSched.h:91
_USB_ENDPOINT
Definition: EhciUrb.h:148
_USB_XHCI_INSTANCE
Definition: Xhci.h:204
EFI_USB_PORT_STATUS
Definition: Usb2HostController.h:27
USB_CONFIG_DESCRIPTOR
Definition: Usb.h:125
USB_DEVICE_REQUEST
Definition: Usb.h:92
_TRB
Definition: XhciSched.h:365
_USB_DEV_ROUTE
Definition: XhciSched.h:109