TianoCore EDK2 master
|
Data Fields | |
UINT32 | RsvdZ0 |
UINT32 | RsvdZ1 |
UINT32 | RsvdZ2 |
UINT32 | CycleBit: 1 |
UINT32 | RsvdZ3: 9 |
UINT32 | Type: 6 |
UINT32 | RsvdZ4: 16 |
Definition at line 378 of file XhciSched.h.
UINT32 _CMD_TRB_NO_OP::CycleBit |
Definition at line 383 of file XhciSched.h.
UINT32 _CMD_TRB_NO_OP::RsvdZ0 |
Definition at line 379 of file XhciSched.h.
UINT32 _CMD_TRB_NO_OP::RsvdZ1 |
Definition at line 380 of file XhciSched.h.
UINT32 _CMD_TRB_NO_OP::RsvdZ2 |
Definition at line 381 of file XhciSched.h.
UINT32 _CMD_TRB_NO_OP::RsvdZ3 |
Definition at line 384 of file XhciSched.h.
UINT32 _CMD_TRB_NO_OP::RsvdZ4 |
Definition at line 386 of file XhciSched.h.
UINT32 _CMD_TRB_NO_OP::Type |
Definition at line 385 of file XhciSched.h.