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XhciSched.h
Go to the documentation of this file.
1
10#ifndef _EFI_PEI_XHCI_SCHED_H_
11#define _EFI_PEI_XHCI_SCHED_H_
12
13//
14// Transfer types, used in URB to identify the transfer type
15//
16#define XHC_CTRL_TRANSFER 0x01
17#define XHC_BULK_TRANSFER 0x02
18
19//
20// 6.4.6 TRB Types
21//
22#define TRB_TYPE_NORMAL 1
23#define TRB_TYPE_SETUP_STAGE 2
24#define TRB_TYPE_DATA_STAGE 3
25#define TRB_TYPE_STATUS_STAGE 4
26#define TRB_TYPE_ISOCH 5
27#define TRB_TYPE_LINK 6
28#define TRB_TYPE_EVENT_DATA 7
29#define TRB_TYPE_NO_OP 8
30#define TRB_TYPE_EN_SLOT 9
31#define TRB_TYPE_DIS_SLOT 10
32#define TRB_TYPE_ADDRESS_DEV 11
33#define TRB_TYPE_CON_ENDPOINT 12
34#define TRB_TYPE_EVALU_CONTXT 13
35#define TRB_TYPE_RESET_ENDPOINT 14
36#define TRB_TYPE_STOP_ENDPOINT 15
37#define TRB_TYPE_SET_TR_DEQUE 16
38#define TRB_TYPE_RESET_DEV 17
39#define TRB_TYPE_GET_PORT_BANW 21
40#define TRB_TYPE_FORCE_HEADER 22
41#define TRB_TYPE_NO_OP_COMMAND 23
42#define TRB_TYPE_TRANS_EVENT 32
43#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
44#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
45#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
46#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
47#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
48
49//
50// Endpoint Type (EP Type).
51//
52#define ED_NOT_VALID 0
53#define ED_ISOCH_OUT 1
54#define ED_BULK_OUT 2
55#define ED_INTERRUPT_OUT 3
56#define ED_CONTROL_BIDIR 4
57#define ED_ISOCH_IN 5
58#define ED_BULK_IN 6
59#define ED_INTERRUPT_IN 7
60
61//
62// 6.4.5 TRB Completion Codes
63//
64#define TRB_COMPLETION_INVALID 0
65#define TRB_COMPLETION_SUCCESS 1
66#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
67#define TRB_COMPLETION_BABBLE_ERROR 3
68#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
69#define TRB_COMPLETION_TRB_ERROR 5
70#define TRB_COMPLETION_STALL_ERROR 6
71#define TRB_COMPLETION_SHORT_PACKET 13
72
73//
74// The topology string used to present usb device location
75//
76typedef struct _USB_DEV_TOPOLOGY {
77 //
78 // The tier concatenation of down stream port.
79 //
80 UINT32 RouteString : 20;
81 //
82 // The root port number of the chain.
83 //
84 UINT32 RootPortNum : 8;
85 //
86 // The Tier the device reside.
87 //
88 UINT32 TierNum : 4;
89} USB_DEV_TOPOLOGY;
90
91//
92// USB Device's RouteChart
93//
94typedef union _USB_DEV_ROUTE {
95 UINT32 Dword;
96 USB_DEV_TOPOLOGY Route;
97} USB_DEV_ROUTE;
98
99//
100// Endpoint address and its capabilities
101//
102typedef struct _USB_ENDPOINT {
103 //
104 // Store logical device address assigned by UsbBus
105 // It's because some XHCI host controllers may assign the same physcial device
106 // address for those devices inserted at different root port.
107 //
108 UINT8 BusAddr;
109 UINT8 DevAddr;
110 UINT8 EpAddr;
111 EFI_USB_DATA_DIRECTION Direction;
112 UINT8 DevSpeed;
113 UINTN MaxPacket;
114 UINTN Type;
115} USB_ENDPOINT;
116
117//
118// TRB Template
119//
120typedef struct _TRB_TEMPLATE {
121 UINT32 Parameter1;
122
123 UINT32 Parameter2;
124
125 UINT32 Status;
126
127 UINT32 CycleBit : 1;
128 UINT32 RsvdZ1 : 9;
129 UINT32 Type : 6;
130 UINT32 Control : 16;
131} TRB_TEMPLATE;
132
133typedef struct _TRANSFER_RING {
134 VOID *RingSeg0;
135 UINTN TrbNumber;
136 TRB_TEMPLATE *RingEnqueue;
137 TRB_TEMPLATE *RingDequeue;
138 UINT32 RingPCS;
139} TRANSFER_RING;
140
141typedef struct _EVENT_RING {
142 VOID *ERSTBase;
143 VOID *EventRingSeg0;
144 UINTN TrbNumber;
145 TRB_TEMPLATE *EventRingEnqueue;
146 TRB_TEMPLATE *EventRingDequeue;
147 UINT32 EventRingCCS;
148} EVENT_RING;
149
150#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
151
152//
153// URB (Usb Request Block) contains information for all kinds of
154// usb requests.
155//
156typedef struct _URB {
157 UINT32 Signature;
158 //
159 // Usb Device URB related information
160 //
161 USB_ENDPOINT Ep;
162 EFI_USB_DEVICE_REQUEST *Request;
163 VOID *Data;
164 UINTN DataLen;
165 VOID *DataPhy;
166 VOID *DataMap;
167 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
168 VOID *Context;
169 //
170 // Execute result
171 //
172 UINT32 Result;
173 //
174 // completed data length
175 //
176 UINTN Completed;
177 //
178 // Command/Tranfer Ring info
179 //
180 TRANSFER_RING *Ring;
181 TRB_TEMPLATE *TrbStart;
182 TRB_TEMPLATE *TrbEnd;
183 UINTN TrbNum;
184 BOOLEAN StartDone;
185 BOOLEAN EndDone;
186 BOOLEAN Finished;
187
188 TRB_TEMPLATE *EvtTrb;
189} URB;
190
191//
192// 6.5 Event Ring Segment Table
193// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
194// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
195// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
196// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
197//
198typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
199 UINT32 PtrLo;
200 UINT32 PtrHi;
201 UINT32 RingTrbSize : 16;
202 UINT32 RsvdZ1 : 16;
203 UINT32 RsvdZ2;
204} EVENT_RING_SEG_TABLE_ENTRY;
205
206//
207// 6.4.1.1 Normal TRB
208// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
209// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
210// Rings, and to define the Data stage information for Control Transfer Rings.
211//
212typedef struct _TRANSFER_TRB_NORMAL {
213 UINT32 TRBPtrLo;
214
215 UINT32 TRBPtrHi;
216
217 UINT32 Length : 17;
218 UINT32 TDSize : 5;
219 UINT32 IntTarget : 10;
220
221 UINT32 CycleBit : 1;
222 UINT32 ENT : 1;
223 UINT32 ISP : 1;
224 UINT32 NS : 1;
225 UINT32 CH : 1;
226 UINT32 IOC : 1;
227 UINT32 IDT : 1;
228 UINT32 RsvdZ1 : 2;
229 UINT32 BEI : 1;
230 UINT32 Type : 6;
231 UINT32 RsvdZ2 : 16;
232} TRANSFER_TRB_NORMAL;
233
234//
235// 6.4.1.2.1 Setup Stage TRB
236// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
237//
238typedef struct _TRANSFER_TRB_CONTROL_SETUP {
239 UINT32 bmRequestType : 8;
240 UINT32 bRequest : 8;
241 UINT32 wValue : 16;
242
243 UINT32 wIndex : 16;
244 UINT32 wLength : 16;
245
246 UINT32 Length : 17;
247 UINT32 RsvdZ1 : 5;
248 UINT32 IntTarget : 10;
249
250 UINT32 CycleBit : 1;
251 UINT32 RsvdZ2 : 4;
252 UINT32 IOC : 1;
253 UINT32 IDT : 1;
254 UINT32 RsvdZ3 : 3;
255 UINT32 Type : 6;
256 UINT32 TRT : 2;
257 UINT32 RsvdZ4 : 14;
258} TRANSFER_TRB_CONTROL_SETUP;
259
260//
261// 6.4.1.2.2 Data Stage TRB
262// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
263//
264typedef struct _TRANSFER_TRB_CONTROL_DATA {
265 UINT32 TRBPtrLo;
266
267 UINT32 TRBPtrHi;
268
269 UINT32 Length : 17;
270 UINT32 TDSize : 5;
271 UINT32 IntTarget : 10;
272
273 UINT32 CycleBit : 1;
274 UINT32 ENT : 1;
275 UINT32 ISP : 1;
276 UINT32 NS : 1;
277 UINT32 CH : 1;
278 UINT32 IOC : 1;
279 UINT32 IDT : 1;
280 UINT32 RsvdZ1 : 3;
281 UINT32 Type : 6;
282 UINT32 DIR : 1;
283 UINT32 RsvdZ2 : 15;
284} TRANSFER_TRB_CONTROL_DATA;
285
286//
287// 6.4.1.2.2 Data Stage TRB
288// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
289//
290typedef struct _TRANSFER_TRB_CONTROL_STATUS {
291 UINT32 RsvdZ1;
292 UINT32 RsvdZ2;
293
294 UINT32 RsvdZ3 : 22;
295 UINT32 IntTarget : 10;
296
297 UINT32 CycleBit : 1;
298 UINT32 ENT : 1;
299 UINT32 RsvdZ4 : 2;
300 UINT32 CH : 1;
301 UINT32 IOC : 1;
302 UINT32 RsvdZ5 : 4;
303 UINT32 Type : 6;
304 UINT32 DIR : 1;
305 UINT32 RsvdZ6 : 15;
306} TRANSFER_TRB_CONTROL_STATUS;
307
308//
309// 6.4.2.1 Transfer Event TRB
310// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
311// for more information on the use and operation of Transfer Events.
312//
313typedef struct _EVT_TRB_TRANSFER {
314 UINT32 TRBPtrLo;
315
316 UINT32 TRBPtrHi;
317
318 UINT32 Length : 24;
319 UINT32 Completecode : 8;
320
321 UINT32 CycleBit : 1;
322 UINT32 RsvdZ1 : 1;
323 UINT32 ED : 1;
324 UINT32 RsvdZ2 : 7;
325 UINT32 Type : 6;
326 UINT32 EndpointId : 5;
327 UINT32 RsvdZ3 : 3;
328 UINT32 SlotId : 8;
329} EVT_TRB_TRANSFER;
330
331//
332// 6.4.2.2 Command Completion Event TRB
333// A Command Completion Event TRB shall be generated by the xHC when a command completes on the
334// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
335//
336typedef struct _EVT_TRB_COMMAND_COMPLETION {
337 UINT32 TRBPtrLo;
338
339 UINT32 TRBPtrHi;
340
341 UINT32 RsvdZ2 : 24;
342 UINT32 Completecode : 8;
343
344 UINT32 CycleBit : 1;
345 UINT32 RsvdZ3 : 9;
346 UINT32 Type : 6;
347 UINT32 VFID : 8;
348 UINT32 SlotId : 8;
349} EVT_TRB_COMMAND_COMPLETION;
350
351typedef union _TRB {
352 TRB_TEMPLATE TrbTemplate;
353 TRANSFER_TRB_NORMAL TrbNormal;
354 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
355 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
356 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
357} TRB;
358
359//
360// 6.4.3.1 No Op Command TRB
361// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
362// mechanisms offered by the xHCI.
363//
364typedef struct _CMD_TRB_NO_OP {
365 UINT32 RsvdZ0;
366 UINT32 RsvdZ1;
367 UINT32 RsvdZ2;
368
369 UINT32 CycleBit : 1;
370 UINT32 RsvdZ3 : 9;
371 UINT32 Type : 6;
372 UINT32 RsvdZ4 : 16;
373} CMD_TRB_NO_OP;
374
375//
376// 6.4.3.2 Enable Slot Command TRB
377// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
378// selected slot to the host in a Command Completion Event.
379//
380typedef struct _CMD_TRB_ENABLE_SLOT {
381 UINT32 RsvdZ0;
382 UINT32 RsvdZ1;
383 UINT32 RsvdZ2;
384
385 UINT32 CycleBit : 1;
386 UINT32 RsvdZ3 : 9;
387 UINT32 Type : 6;
388 UINT32 RsvdZ4 : 16;
389} CMD_TRB_ENABLE_SLOT;
390
391//
392// 6.4.3.3 Disable Slot Command TRB
393// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
394// internal xHC resources assigned to the slot.
395//
396typedef struct _CMD_TRB_DISABLE_SLOT {
397 UINT32 RsvdZ0;
398 UINT32 RsvdZ1;
399 UINT32 RsvdZ2;
400
401 UINT32 CycleBit : 1;
402 UINT32 RsvdZ3 : 9;
403 UINT32 Type : 6;
404 UINT32 RsvdZ4 : 8;
405 UINT32 SlotId : 8;
406} CMD_TRB_DISABLE_SLOT;
407
408//
409// 6.4.3.4 Address Device Command TRB
410// The Address Device Command TRB transitions the selected Device Context from the Default to the
411// Addressed state and causes the xHC to select an address for the USB device in the Default State and
412// issue a SET_ADDRESS request to the USB device.
413//
414typedef struct _CMD_TRB_ADDRESS_DEVICE {
415 UINT32 PtrLo;
416
417 UINT32 PtrHi;
418
419 UINT32 RsvdZ1;
420
421 UINT32 CycleBit : 1;
422 UINT32 RsvdZ2 : 8;
423 UINT32 BSR : 1;
424 UINT32 Type : 6;
425 UINT32 RsvdZ3 : 8;
426 UINT32 SlotId : 8;
427} CMD_TRB_ADDRESS_DEVICE;
428
429//
430// 6.4.3.5 Configure Endpoint Command TRB
431// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
432// endpoints selected by the command.
433//
434typedef struct _CMD_TRB_CONFIG_ENDPOINT {
435 UINT32 PtrLo;
436
437 UINT32 PtrHi;
438
439 UINT32 RsvdZ1;
440
441 UINT32 CycleBit : 1;
442 UINT32 RsvdZ2 : 8;
443 UINT32 DC : 1;
444 UINT32 Type : 6;
445 UINT32 RsvdZ3 : 8;
446 UINT32 SlotId : 8;
447} CMD_TRB_CONFIG_ENDPOINT;
448
449//
450// 6.4.3.6 Evaluate Context Command TRB
451// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
452// Context data structures in the Device Context have been modified by system software and that the xHC
453// shall evaluate any changes
454//
455typedef struct _CMD_TRB_EVALUATE_CONTEXT {
456 UINT32 PtrLo;
457
458 UINT32 PtrHi;
459
460 UINT32 RsvdZ1;
461
462 UINT32 CycleBit : 1;
463 UINT32 RsvdZ2 : 9;
464 UINT32 Type : 6;
465 UINT32 RsvdZ3 : 8;
466 UINT32 SlotId : 8;
467} CMD_TRB_EVALUATE_CONTEXT;
468
469//
470// 6.4.3.7 Reset Endpoint Command TRB
471// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
472//
473typedef struct _CMD_TRB_RESET_ENDPOINT {
474 UINT32 RsvdZ0;
475 UINT32 RsvdZ1;
476 UINT32 RsvdZ2;
477
478 UINT32 CycleBit : 1;
479 UINT32 RsvdZ3 : 8;
480 UINT32 TSP : 1;
481 UINT32 Type : 6;
482 UINT32 EDID : 5;
483 UINT32 RsvdZ4 : 3;
484 UINT32 SlotId : 8;
485} CMD_TRB_RESET_ENDPOINT;
486
487//
488// 6.4.3.8 Stop Endpoint Command TRB
489// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
490// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
491//
492typedef struct _CMD_TRB_STOP_ENDPOINT {
493 UINT32 RsvdZ0;
494 UINT32 RsvdZ1;
495 UINT32 RsvdZ2;
496
497 UINT32 CycleBit : 1;
498 UINT32 RsvdZ3 : 9;
499 UINT32 Type : 6;
500 UINT32 EDID : 5;
501 UINT32 RsvdZ4 : 2;
502 UINT32 SP : 1;
503 UINT32 SlotId : 8;
504} CMD_TRB_STOP_ENDPOINT;
505
506//
507// 6.4.3.9 Set TR Dequeue Pointer Command TRB
508// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
509// Pointer and DCS fields of an Endpoint or Stream Context.
510//
511typedef struct _CMD_SET_TR_DEQ_POINTER {
512 UINT32 PtrLo;
513
514 UINT32 PtrHi;
515
516 UINT32 RsvdZ1 : 16;
517 UINT32 StreamID : 16;
518
519 UINT32 CycleBit : 1;
520 UINT32 RsvdZ2 : 9;
521 UINT32 Type : 6;
522 UINT32 Endpoint : 5;
523 UINT32 RsvdZ3 : 3;
524 UINT32 SlotId : 8;
525} CMD_SET_TR_DEQ_POINTER;
526
527//
528// 6.4.4.1 Link TRB
529// A Link TRB provides support for non-contiguous TRB Rings.
530//
531typedef struct _LINK_TRB {
532 UINT32 PtrLo;
533
534 UINT32 PtrHi;
535
536 UINT32 RsvdZ1 : 22;
537 UINT32 InterTarget : 10;
538
539 UINT32 CycleBit : 1;
540 UINT32 TC : 1;
541 UINT32 RsvdZ2 : 2;
542 UINT32 CH : 1;
543 UINT32 IOC : 1;
544 UINT32 RsvdZ3 : 4;
545 UINT32 Type : 6;
546 UINT32 RsvdZ4 : 16;
547} LINK_TRB;
548
549//
550// 6.2.2 Slot Context
551//
552typedef struct _SLOT_CONTEXT {
553 UINT32 RouteString : 20;
554 UINT32 Speed : 4;
555 UINT32 RsvdZ1 : 1;
556 UINT32 MTT : 1;
557 UINT32 Hub : 1;
558 UINT32 ContextEntries : 5;
559
560 UINT32 MaxExitLatency : 16;
561 UINT32 RootHubPortNum : 8;
562 UINT32 PortNum : 8;
563
564 UINT32 TTHubSlotId : 8;
565 UINT32 TTPortNum : 8;
566 UINT32 TTT : 2;
567 UINT32 RsvdZ2 : 4;
568 UINT32 InterTarget : 10;
569
570 UINT32 DeviceAddress : 8;
571 UINT32 RsvdZ3 : 19;
572 UINT32 SlotState : 5;
573
574 UINT32 RsvdZ4;
575 UINT32 RsvdZ5;
576 UINT32 RsvdZ6;
577 UINT32 RsvdZ7;
578} SLOT_CONTEXT;
579
580typedef struct _SLOT_CONTEXT_64 {
581 UINT32 RouteString : 20;
582 UINT32 Speed : 4;
583 UINT32 RsvdZ1 : 1;
584 UINT32 MTT : 1;
585 UINT32 Hub : 1;
586 UINT32 ContextEntries : 5;
587
588 UINT32 MaxExitLatency : 16;
589 UINT32 RootHubPortNum : 8;
590 UINT32 PortNum : 8;
591
592 UINT32 TTHubSlotId : 8;
593 UINT32 TTPortNum : 8;
594 UINT32 TTT : 2;
595 UINT32 RsvdZ2 : 4;
596 UINT32 InterTarget : 10;
597
598 UINT32 DeviceAddress : 8;
599 UINT32 RsvdZ3 : 19;
600 UINT32 SlotState : 5;
601
602 UINT32 RsvdZ4;
603 UINT32 RsvdZ5;
604 UINT32 RsvdZ6;
605 UINT32 RsvdZ7;
606
607 UINT32 RsvdZ8;
608 UINT32 RsvdZ9;
609 UINT32 RsvdZ10;
610 UINT32 RsvdZ11;
611
612 UINT32 RsvdZ12;
613 UINT32 RsvdZ13;
614 UINT32 RsvdZ14;
615 UINT32 RsvdZ15;
616} SLOT_CONTEXT_64;
617
618//
619// 6.2.3 Endpoint Context
620//
621typedef struct _ENDPOINT_CONTEXT {
622 UINT32 EPState : 3;
623 UINT32 RsvdZ1 : 5;
624 UINT32 Mult : 2;
625 UINT32 MaxPStreams : 5;
626 UINT32 LSA : 1;
627 UINT32 Interval : 8;
628 UINT32 RsvdZ2 : 8;
629
630 UINT32 RsvdZ3 : 1;
631 UINT32 CErr : 2;
632 UINT32 EPType : 3;
633 UINT32 RsvdZ4 : 1;
634 UINT32 HID : 1;
635 UINT32 MaxBurstSize : 8;
636 UINT32 MaxPacketSize : 16;
637
638 UINT32 PtrLo;
639
640 UINT32 PtrHi;
641
642 UINT32 AverageTRBLength : 16;
643 UINT32 MaxESITPayload : 16;
644
645 UINT32 RsvdZ5;
646 UINT32 RsvdZ6;
647 UINT32 RsvdZ7;
648} ENDPOINT_CONTEXT;
649
650typedef struct _ENDPOINT_CONTEXT_64 {
651 UINT32 EPState : 3;
652 UINT32 RsvdZ1 : 5;
653 UINT32 Mult : 2;
654 UINT32 MaxPStreams : 5;
655 UINT32 LSA : 1;
656 UINT32 Interval : 8;
657 UINT32 RsvdZ2 : 8;
658
659 UINT32 RsvdZ3 : 1;
660 UINT32 CErr : 2;
661 UINT32 EPType : 3;
662 UINT32 RsvdZ4 : 1;
663 UINT32 HID : 1;
664 UINT32 MaxBurstSize : 8;
665 UINT32 MaxPacketSize : 16;
666
667 UINT32 PtrLo;
668
669 UINT32 PtrHi;
670
671 UINT32 AverageTRBLength : 16;
672 UINT32 MaxESITPayload : 16;
673
674 UINT32 RsvdZ5;
675 UINT32 RsvdZ6;
676 UINT32 RsvdZ7;
677
678 UINT32 RsvdZ8;
679 UINT32 RsvdZ9;
680 UINT32 RsvdZ10;
681 UINT32 RsvdZ11;
682
683 UINT32 RsvdZ12;
684 UINT32 RsvdZ13;
685 UINT32 RsvdZ14;
686 UINT32 RsvdZ15;
687} ENDPOINT_CONTEXT_64;
688
689//
690// 6.2.5.1 Input Control Context
691//
692typedef struct _INPUT_CONTRL_CONTEXT {
693 UINT32 Dword1;
694 UINT32 Dword2;
695 UINT32 RsvdZ1;
696 UINT32 RsvdZ2;
697 UINT32 RsvdZ3;
698 UINT32 RsvdZ4;
699 UINT32 RsvdZ5;
700 UINT32 RsvdZ6;
701} INPUT_CONTRL_CONTEXT;
702
703typedef struct _INPUT_CONTRL_CONTEXT_64 {
704 UINT32 Dword1;
705 UINT32 Dword2;
706 UINT32 RsvdZ1;
707 UINT32 RsvdZ2;
708 UINT32 RsvdZ3;
709 UINT32 RsvdZ4;
710 UINT32 RsvdZ5;
711 UINT32 RsvdZ6;
712 UINT32 RsvdZ7;
713 UINT32 RsvdZ8;
714 UINT32 RsvdZ9;
715 UINT32 RsvdZ10;
716 UINT32 RsvdZ11;
717 UINT32 RsvdZ12;
718 UINT32 RsvdZ13;
719 UINT32 RsvdZ14;
720} INPUT_CONTRL_CONTEXT_64;
721
722//
723// 6.2.1 Device Context
724//
725typedef struct _DEVICE_CONTEXT {
726 SLOT_CONTEXT Slot;
727 ENDPOINT_CONTEXT EP[31];
728} DEVICE_CONTEXT;
729
730typedef struct _DEVICE_CONTEXT_64 {
731 SLOT_CONTEXT_64 Slot;
732 ENDPOINT_CONTEXT_64 EP[31];
733} DEVICE_CONTEXT_64;
734
735//
736// 6.2.5 Input Context
737//
738typedef struct _INPUT_CONTEXT {
739 INPUT_CONTRL_CONTEXT InputControlContext;
740 SLOT_CONTEXT Slot;
741 ENDPOINT_CONTEXT EP[31];
742} INPUT_CONTEXT;
743
744typedef struct _INPUT_CONTEXT_64 {
745 INPUT_CONTRL_CONTEXT_64 InputControlContext;
746 SLOT_CONTEXT_64 Slot;
747 ENDPOINT_CONTEXT_64 EP[31];
748} INPUT_CONTEXT_64;
749
763EFI_STATUS
764XhcPeiExecTransfer (
765 IN PEI_XHC_DEV *Xhc,
766 IN BOOLEAN CmdTransfer,
767 IN URB *Urb,
768 IN UINTN Timeout
769 );
770
780UINT8
781XhcPeiBusDevAddrToSlotId (
782 IN PEI_XHC_DEV *Xhc,
783 IN UINT8 BusDevAddr
784 );
785
795UINT8
796XhcPeiRouteStringToSlotId (
797 IN PEI_XHC_DEV *Xhc,
798 IN USB_DEV_ROUTE RouteString
799 );
800
810UINT8
811XhcPeiEndpointToDci (
812 IN UINT8 EpAddr,
813 IN EFI_USB_DATA_DIRECTION Direction
814 );
815
824VOID
825XhcPeiRingDoorBell (
826 IN PEI_XHC_DEV *Xhc,
827 IN UINT8 SlotId,
828 IN UINT8 Dci
829 );
830
843EFI_STATUS
844XhcPeiPollPortStatusChange (
845 IN PEI_XHC_DEV *Xhc,
846 IN USB_DEV_ROUTE ParentRouteChart,
847 IN UINT8 Port,
848 IN EFI_USB_PORT_STATUS *PortState
849 );
850
863EFI_STATUS
864XhcPeiConfigHubContext (
865 IN PEI_XHC_DEV *Xhc,
866 IN UINT8 SlotId,
867 IN UINT8 PortNum,
868 IN UINT8 TTT,
869 IN UINT8 MTT
870 );
871
884EFI_STATUS
885XhcPeiConfigHubContext64 (
886 IN PEI_XHC_DEV *Xhc,
887 IN UINT8 SlotId,
888 IN UINT8 PortNum,
889 IN UINT8 TTT,
890 IN UINT8 MTT
891 );
892
904EFI_STATUS
905XhcPeiSetConfigCmd (
906 IN PEI_XHC_DEV *Xhc,
907 IN UINT8 SlotId,
908 IN UINT8 DeviceSpeed,
909 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
910 );
911
923EFI_STATUS
924XhcPeiSetConfigCmd64 (
925 IN PEI_XHC_DEV *Xhc,
926 IN UINT8 SlotId,
927 IN UINT8 DeviceSpeed,
928 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
929 );
930
942EFI_STATUS
943EFIAPI
944XhcPeiStopEndpoint (
945 IN PEI_XHC_DEV *Xhc,
946 IN UINT8 SlotId,
947 IN UINT8 Dci
948 );
949
961EFI_STATUS
962EFIAPI
963XhcPeiResetEndpoint (
964 IN PEI_XHC_DEV *Xhc,
965 IN UINT8 SlotId,
966 IN UINT8 Dci
967 );
968
982EFI_STATUS
983EFIAPI
984XhcPeiSetTrDequeuePointer (
985 IN PEI_XHC_DEV *Xhc,
986 IN UINT8 SlotId,
987 IN UINT8 Dci,
988 IN URB *Urb
989 );
990
1004EFI_STATUS
1005XhcPeiInitializeDeviceSlot (
1006 IN PEI_XHC_DEV *Xhc,
1007 IN USB_DEV_ROUTE ParentRouteChart,
1008 IN UINT16 ParentPort,
1009 IN USB_DEV_ROUTE RouteChart,
1010 IN UINT8 DeviceSpeed
1011 );
1012
1026EFI_STATUS
1027XhcPeiInitializeDeviceSlot64 (
1028 IN PEI_XHC_DEV *Xhc,
1029 IN USB_DEV_ROUTE ParentRouteChart,
1030 IN UINT16 ParentPort,
1031 IN USB_DEV_ROUTE RouteChart,
1032 IN UINT8 DeviceSpeed
1033 );
1034
1045EFI_STATUS
1046XhcPeiEvaluateContext (
1047 IN PEI_XHC_DEV *Xhc,
1048 IN UINT8 SlotId,
1049 IN UINT32 MaxPacketSize
1050 );
1051
1062EFI_STATUS
1063XhcPeiEvaluateContext64 (
1064 IN PEI_XHC_DEV *Xhc,
1065 IN UINT8 SlotId,
1066 IN UINT32 MaxPacketSize
1067 );
1068
1078EFI_STATUS
1079XhcPeiDisableSlotCmd (
1080 IN PEI_XHC_DEV *Xhc,
1081 IN UINT8 SlotId
1082 );
1083
1093EFI_STATUS
1094XhcPeiDisableSlotCmd64 (
1095 IN PEI_XHC_DEV *Xhc,
1096 IN UINT8 SlotId
1097 );
1098
1113EFI_STATUS
1114XhcPeiRecoverHaltedEndpoint (
1115 IN PEI_XHC_DEV *Xhc,
1116 IN URB *Urb
1117 );
1118
1132EFI_STATUS
1133XhcPeiDequeueTrbFromEndpoint (
1134 IN PEI_XHC_DEV *Xhc,
1135 IN URB *Urb
1136 );
1137
1156URB *
1157XhcPeiCreateUrb (
1158 IN PEI_XHC_DEV *Xhc,
1159 IN UINT8 DevAddr,
1160 IN UINT8 EpAddr,
1161 IN UINT8 DevSpeed,
1162 IN UINTN MaxPacket,
1163 IN UINTN Type,
1164 IN EFI_USB_DEVICE_REQUEST *Request,
1165 IN VOID *Data,
1166 IN UINTN DataLen,
1167 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1168 IN VOID *Context
1169 );
1170
1178VOID
1179XhcPeiFreeUrb (
1180 IN PEI_XHC_DEV *Xhc,
1181 IN URB *Urb
1182 );
1183
1193EFI_STATUS
1194XhcPeiCreateTransferTrb (
1195 IN PEI_XHC_DEV *Xhc,
1196 IN URB *Urb
1197 );
1198
1208EFI_STATUS
1209XhcPeiSyncTrsRing (
1210 IN PEI_XHC_DEV *Xhc,
1211 IN TRANSFER_RING *TrsRing
1212 );
1213
1222VOID
1223XhcPeiCreateTransferRing (
1224 IN PEI_XHC_DEV *Xhc,
1225 IN UINTN TrbNum,
1226 OUT TRANSFER_RING *TransferRing
1227 );
1228
1240EFI_STATUS
1241XhcPeiCheckNewEvent (
1242 IN PEI_XHC_DEV *Xhc,
1243 IN EVENT_RING *EvtRing,
1244 OUT TRB_TEMPLATE **NewEvtTrb
1245 );
1246
1256EFI_STATUS
1257XhcPeiSyncEventRing (
1258 IN PEI_XHC_DEV *Xhc,
1259 IN EVENT_RING *EvtRing
1260 );
1261
1269VOID
1270XhcPeiCreateEventRing (
1271 IN PEI_XHC_DEV *Xhc,
1272 OUT EVENT_RING *EventRing
1273 );
1274
1281VOID
1282XhcPeiInitSched (
1283 IN PEI_XHC_DEV *Xhc
1284 );
1285
1292VOID
1293XhcPeiFreeSched (
1294 IN PEI_XHC_DEV *Xhc
1295 );
1296
1297#endif
UINTN
UINT64 UINTN
Definition: ProcessorBind.h:112
IN
#define IN
Definition: Base.h:279
OUT
#define OUT
Definition: Base.h:284
EFI_USB_DATA_DIRECTION
EFI_USB_DATA_DIRECTION
Definition: UsbIo.h:44
EFI_ASYNC_USB_TRANSFER_CALLBACK
EFI_STATUS(EFIAPI * EFI_ASYNC_USB_TRANSFER_CALLBACK)(IN VOID *Data, IN UINTN DataLength, IN VOID *Context, IN UINT32 Status)
Definition: UsbIo.h:80
EFI_STATUS
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
XhcPeiDisableSlotCmd64
EFI_STATUS XhcPeiDisableSlotCmd64(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId)
Definition: XhciSched.c:1604
XhcPeiRouteStringToSlotId
UINT8 XhcPeiRouteStringToSlotId(IN PEI_XHC_DEV *Xhc, IN USB_DEV_ROUTE RouteString)
Definition: XhciSched.c:1012
XhcPeiInitSched
VOID XhcPeiInitSched(IN PEI_XHC_DEV *Xhc)
Definition: XhciSched.c:2882
XhcPeiEvaluateContext
EFI_STATUS XhcPeiEvaluateContext(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT32 MaxPacketSize)
Definition: XhciSched.c:2167
XhcPeiSetConfigCmd
EFI_STATUS XhcPeiSetConfigCmd(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT8 DeviceSpeed, IN USB_CONFIG_DESCRIPTOR *ConfigDesc)
Definition: XhciSched.c:1713
XhcPeiSetConfigCmd64
EFI_STATUS XhcPeiSetConfigCmd64(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT8 DeviceSpeed, IN USB_CONFIG_DESCRIPTOR *ConfigDesc)
Definition: XhciSched.c:1939
XhcPeiCheckNewEvent
EFI_STATUS XhcPeiCheckNewEvent(IN PEI_XHC_DEV *Xhc, IN EVENT_RING *EvtRing, OUT TRB_TEMPLATE **NewEvtTrb)
Definition: XhciSched.c:2561
XhcPeiRecoverHaltedEndpoint
EFI_STATUS XhcPeiRecoverHaltedEndpoint(IN PEI_XHC_DEV *Xhc, IN URB *Urb)
Definition: XhciSched.c:472
XhcPeiRingDoorBell
VOID XhcPeiRingDoorBell(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT8 Dci)
Definition: XhciSched.c:1044
XhcPeiFreeSched
VOID XhcPeiFreeSched(IN PEI_XHC_DEV *Xhc)
Definition: XhciSched.c:3049
XhcPeiConfigHubContext
EFI_STATUS XhcPeiConfigHubContext(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT8 PortNum, IN UINT8 TTT, IN UINT8 MTT)
Definition: XhciSched.c:2279
XhcPeiEvaluateContext64
EFI_STATUS XhcPeiEvaluateContext64(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT32 MaxPacketSize)
Definition: XhciSched.c:2222
XhcPeiSyncTrsRing
EFI_STATUS XhcPeiSyncTrsRing(IN PEI_XHC_DEV *Xhc, IN TRANSFER_RING *TrsRing)
Definition: XhciSched.c:2772
XhcPeiDisableSlotCmd
EFI_STATUS XhcPeiDisableSlotCmd(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId)
Definition: XhciSched.c:1497
XhcPeiFreeUrb
VOID XhcPeiFreeUrb(IN PEI_XHC_DEV *Xhc, IN URB *Urb)
Definition: XhciSched.c:188
XhcPeiInitializeDeviceSlot64
EFI_STATUS XhcPeiInitializeDeviceSlot64(IN PEI_XHC_DEV *Xhc, IN USB_DEV_ROUTE ParentRouteChart, IN UINT16 ParentPort, IN USB_DEV_ROUTE RouteChart, IN UINT8 DeviceSpeed)
Definition: XhciSched.c:1286
XhcPeiConfigHubContext64
EFI_STATUS XhcPeiConfigHubContext64(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT8 PortNum, IN UINT8 TTT, IN UINT8 MTT)
Definition: XhciSched.c:2348
XhcPeiResetEndpoint
EFI_STATUS EFIAPI XhcPeiResetEndpoint(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT8 Dci)
Definition: XhciSched.c:2463
XhcPeiCreateUrb
URB * XhcPeiCreateUrb(IN PEI_XHC_DEV *Xhc, IN UINT8 DevAddr, IN UINT8 EpAddr, IN UINT8 DevSpeed, IN UINTN MaxPacket, IN UINTN Type, IN EFI_USB_DEVICE_REQUEST *Request, IN VOID *Data, IN UINTN DataLen, IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback, IN VOID *Context)
Definition: XhciSched.c:131
XhcPeiStopEndpoint
EFI_STATUS EFIAPI XhcPeiStopEndpoint(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT8 Dci)
Definition: XhciSched.c:2417
XhcPeiBusDevAddrToSlotId
UINT8 XhcPeiBusDevAddrToSlotId(IN PEI_XHC_DEV *Xhc, IN UINT8 BusDevAddr)
Definition: XhciSched.c:979
XhcPeiCreateTransferTrb
EFI_STATUS XhcPeiCreateTransferTrb(IN PEI_XHC_DEV *Xhc, IN URB *Urb)
Definition: XhciSched.c:212
XhcPeiSyncEventRing
EFI_STATUS XhcPeiSyncEventRing(IN PEI_XHC_DEV *Xhc, IN EVENT_RING *EvtRing)
Definition: XhciSched.c:2596
XhcPeiInitializeDeviceSlot
EFI_STATUS XhcPeiInitializeDeviceSlot(IN PEI_XHC_DEV *Xhc, IN USB_DEV_ROUTE ParentRouteChart, IN UINT16 ParentPort, IN USB_DEV_ROUTE RouteChart, IN UINT8 DeviceSpeed)
Definition: XhciSched.c:1071
XhcPeiExecTransfer
EFI_STATUS XhcPeiExecTransfer(IN PEI_XHC_DEV *Xhc, IN BOOLEAN CmdTransfer, IN URB *Urb, IN UINTN Timeout)
Definition: XhciSched.c:797
XhcPeiCreateTransferRing
VOID XhcPeiCreateTransferRing(IN PEI_XHC_DEV *Xhc, IN UINTN TrbNum, OUT TRANSFER_RING *TransferRing)
Definition: XhciSched.c:2835
XhcPeiDequeueTrbFromEndpoint
EFI_STATUS XhcPeiDequeueTrbFromEndpoint(IN PEI_XHC_DEV *Xhc, IN URB *Urb)
Definition: XhciSched.c:532
XhcPeiCreateEventRing
VOID XhcPeiCreateEventRing(IN PEI_XHC_DEV *Xhc, OUT EVENT_RING *EventRing)
Definition: XhciSched.c:2670
XhcPeiEndpointToDci
UINT8 XhcPeiEndpointToDci(IN UINT8 EpAddr, IN EFI_USB_DATA_DIRECTION Direction)
Definition: XhciSched.c:948
XhcPeiPollPortStatusChange
EFI_STATUS XhcPeiPollPortStatusChange(IN PEI_XHC_DEV *Xhc, IN USB_DEV_ROUTE ParentRouteChart, IN UINT8 Port, IN EFI_USB_PORT_STATUS *PortState)
Definition: XhciSched.c:863
XhcPeiSetTrDequeuePointer
EFI_STATUS EFIAPI XhcPeiSetTrDequeuePointer(IN PEI_XHC_DEV *Xhc, IN UINT8 SlotId, IN UINT8 Dci, IN URB *Urb)
Definition: XhciSched.c:2511
_CMD_SET_TR_DEQ_POINTER
Definition: XhciSched.h:525
_CMD_TRB_ADDRESS_DEVICE
Definition: XhciSched.h:428
_CMD_TRB_CONFIG_ENDPOINT
Definition: XhciSched.h:448
_CMD_TRB_DISABLE_SLOT
Definition: XhciSched.h:410
_CMD_TRB_ENABLE_SLOT
Definition: XhciSched.h:394
_CMD_TRB_EVALUATE_CONTEXT
Definition: XhciSched.h:469
_CMD_TRB_NO_OP
Definition: XhciSched.h:378
_CMD_TRB_RESET_ENDPOINT
Definition: XhciSched.h:487
_CMD_TRB_STOP_ENDPOINT
Definition: XhciSched.h:506
_DEVICE_CONTEXT_64
Definition: XhciSched.h:744
_DEVICE_CONTEXT
Definition: XhciSched.h:739
_ENDPOINT_CONTEXT_64
Definition: XhciSched.h:664
_ENDPOINT_CONTEXT
Definition: XhciSched.h:635
_EVENT_RING_SEG_TABLE_ENTRY
Definition: XhciSched.h:212
_EVENT_RING
Definition: XhciSched.h:156
_EVT_TRB_COMMAND_COMPLETION
Definition: XhciSched.h:350
_EVT_TRB_TRANSFER
Definition: XhciSched.h:327
_INPUT_CONTEXT_64
Definition: XhciSched.h:758
_INPUT_CONTEXT
Definition: XhciSched.h:752
_INPUT_CONTRL_CONTEXT_64
Definition: XhciSched.h:717
_INPUT_CONTRL_CONTEXT
Definition: XhciSched.h:706
_LINK_TRB
Definition: XhciSched.h:545
_PEI_XHC_DEV
Definition: XhcPeim.h:143
_SLOT_CONTEXT_64
Definition: XhciSched.h:594
_SLOT_CONTEXT
Definition: XhciSched.h:566
_TRANSFER_RING
Definition: XhciSched.h:148
_TRANSFER_TRB_CONTROL_DATA
Definition: XhciSched.h:278
_TRANSFER_TRB_CONTROL_SETUP
Definition: XhciSched.h:252
_TRANSFER_TRB_CONTROL_STATUS
Definition: XhciSched.h:304
_TRANSFER_TRB_NORMAL
Definition: XhciSched.h:226
_TRB_TEMPLATE
Definition: XhciSched.h:135
_URB
Definition: EhciUrb.h:200
_USB_DEV_TOPOLOGY
Definition: XhciSched.h:91
_USB_ENDPOINT
Definition: EhciUrb.h:148
EFI_USB_PORT_STATUS
Definition: Usb2HostController.h:27
USB_CONFIG_DESCRIPTOR
Definition: Usb.h:125
USB_DEVICE_REQUEST
Definition: Usb.h:92
_TRB
Definition: XhciSched.h:365
_USB_DEV_ROUTE
Definition: XhciSched.h:109