TianoCore EDK2 master
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Defines the structure of the CSSELR (Cache Size Selection) register. More...
#include <ArmPkg/Include/IndustryStandard/ArmCache.h>
Data Fields | |
struct { | |
UINT32 InD: 1 | |
Instruction not Data bit. More... | |
UINT32 Level: 3 | |
Cache level (zero based) More... | |
UINT32 TnD: 1 | |
Allocation not Data bit. More... | |
UINT32 Reserved: 27 | |
Reserved, RES0. More... | |
} | Bits |
Bitfield definition of the register. | |
UINT32 | Data |
The entire 32-bit value. | |
Defines the structure of the CSSELR (Cache Size Selection) register.
Definition at line 19 of file ArmCache.h.
UINT32 CSSELR_DATA::Data |
The entire 32-bit value.
Definition at line 26 of file ArmCache.h.
UINT32 CSSELR_DATA::InD |
Instruction not Data bit.
Definition at line 21 of file ArmCache.h.
UINT32 CSSELR_DATA::Level |
Cache level (zero based)
Definition at line 22 of file ArmCache.h.
UINT32 CSSELR_DATA::Reserved |
Reserved, RES0.
Definition at line 24 of file ArmCache.h.
UINT32 CSSELR_DATA::TnD |
Allocation not Data bit.
Definition at line 23 of file ArmCache.h.