ArmCache.h

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#ifndef ARM_CACHE_H_
#define ARM_CACHE_H_
 
#include <Uefi/UefiBaseType.h>
 
// The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7.
#define MAX_ARM_CACHE_LEVEL  7
 
typedef union {
  struct {
    UINT32    InD      : 1;  
    UINT32    Level    : 3;  
    UINT32    TnD      : 1;  
    UINT32    Reserved : 27; 
  } Bits;         
  UINT32    Data; 
} CSSELR_DATA;
 
typedef enum {
  CsselrCacheTypeDataOrUnified = 0,
  CsselrCacheTypeInstruction,
  CsselrCacheTypeMax
} CSSELR_CACHE_TYPE;
 
typedef union {
  struct {
    UINT64    LineSize      : 3;      
    UINT64    Associativity : 10;     
    UINT64    NumSets       : 15;     
    UINT64    Unknown       : 4;      
    UINT64    Reserved      : 32;     
  } BitsNonCcidx; 
  struct {
    UINT64    LineSize      : 3;      
    UINT64    Associativity : 21;     
    UINT64    Reserved1     : 8;      
    UINT64    NumSets       : 24;     
    UINT64    Reserved2     : 8;      
  } BitsCcidxAA64; 
  struct {
    UINT64    LineSize      : 3;
    UINT64    Associativity : 21;
    UINT64    Reserved      : 8;
    UINT64    Unallocated   : 32;
  } BitsCcidxAA32;
  UINT64    Data; 
} CCSIDR_DATA;
 
typedef union {
  struct {
    UINT32    NumSets  : 24;          
    UINT32    Reserved : 8;           
  } Bits;         
  UINT32    Data; 
} CCSIDR2_DATA;
 
typedef union {
  struct {
    UINT32    Ctype1 : 3;   
    UINT32    Ctype2 : 3;   
    UINT32    Ctype3 : 3;   
    UINT32    Ctype4 : 3;   
    UINT32    Ctype5 : 3;   
    UINT32    Ctype6 : 3;   
    UINT32    Ctype7 : 3;   
    UINT32    LoUIS  : 3;   
    UINT32    LoC    : 3;   
    UINT32    LoUU   : 3;   
    UINT32    Icb    : 3;   
  } Bits;         
  UINT32    Data; 
} CLIDR_DATA;
 
typedef enum {
  ClidrCacheTypeNone = 0,
  ClidrCacheTypeInstructionOnly,
  ClidrCacheTypeDataOnly,
  ClidrCacheTypeSeparate,
  ClidrCacheTypeUnified,
  ClidrCacheTypeMax
} CLIDR_CACHE_TYPE;
 
#define CLIDR_GET_CACHE_TYPE(x, level)  ((x >> (3 * (level))) & 0b111)
 
#endif /* ARM_CACHE_H_ */