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EhcPeim.h
Go to the documentation of this file.
1
11#ifndef _RECOVERY_EHC_H_
12#define _RECOVERY_EHC_H_
13
14#include <PiPei.h>
15
16#include <Ppi/UsbController.h>
18#include <Ppi/IoMmu.h>
19#include <Ppi/EndOfPeiPhase.h>
20
21#include <Library/BaseLib.h>
22#include <Library/DebugLib.h>
26#include <Library/TimerLib.h>
27#include <Library/IoLib.h>
28
30
31#define EFI_LIST_ENTRY LIST_ENTRY
32
33#include "UsbHcMem.h"
34#include "EhciReg.h"
35#include "EhciUrb.h"
36#include "EhciSched.h"
37
38#define EFI_USB_SPEED_FULL 0x0000
39#define EFI_USB_SPEED_LOW 0x0001
40#define EFI_USB_SPEED_HIGH 0x0002
41
42#define PAGESIZE 4096
43
44#define EHC_1_MICROSECOND 1
45#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
46#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
47
48//
49// EHCI register operation timeout, set by experience
50//
51#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
52#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
53
54//
55// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
56//
57#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
58
59//
60// Sync transfer polling interval, set by experience.
61//
62#define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)
63
64#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
65
66#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
67#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
68#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
69
70#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
71 (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
72
73#define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')
74
76 UINTN Signature;
77 PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
78 EDKII_IOMMU_PPI *IoMmu;
79 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
80 //
81 // EndOfPei callback is used to stop the EHC DMA operation
82 // after exit PEI phase.
83 //
84 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
85 UINT32 UsbHostControllerBaseAddress;
86 PEI_URB *Urb;
87 USBHC_MEM_POOL *MemPool;
88
89 //
90 // Schedule data shared between asynchronous and periodic
91 // transfers:
92 // ShortReadStop, as its name indicates, is used to terminate
93 // the short read except the control transfer. EHCI follows
94 // the alternative next QTD point when a short read happens.
95 // For control transfer, even the short read happens, try the
96 // status stage.
97 //
98 PEI_EHC_QTD *ShortReadStop;
99 EFI_EVENT PollTimer;
100
101 //
102 // Asynchronous(bulk and control) transfer schedule data:
103 // ReclaimHead is used as the head of the asynchronous transfer
104 // list. It acts as the reclamation header.
105 //
106 PEI_EHC_QH *ReclaimHead;
107
108 //
109 // Periodic (interrupt) transfer schedule data:
110 //
111 VOID *PeriodFrame; // Mapped as common buffer
112 VOID *PeriodFrameMap;
113
114 PEI_EHC_QH *PeriodOne;
115 EFI_LIST_ENTRY AsyncIntTransfers;
116
117 //
118 // EHCI configuration data
119 //
120 UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
121 UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
122 UINT32 CapLen; // Capability length
123 UINT32 High32bitAddr;
124};
125
126#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
127#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
128
138 IN PEI_USB2_HC_DEV *EhcDev
139 );
140
155 IN PEI_USB2_HC_DEV *Ehc,
156 IN BOOLEAN Check4G,
157 IN UINT32 Which4G
158 )
159;
160
173 IN PEI_USB2_HC_DEV *Ehc,
174 IN USBHC_MEM_POOL *Pool
175 )
176;
177
189VOID *
191 IN PEI_USB2_HC_DEV *Ehc,
192 IN USBHC_MEM_POOL *Pool,
193 IN UINTN Size
194 )
195;
196
206VOID
208 IN PEI_USB2_HC_DEV *Ehc,
209 IN USBHC_MEM_POOL *Pool,
210 IN VOID *Mem,
211 IN UINTN Size
212 )
213;
214
236IoMmuMap (
237 IN EDKII_IOMMU_PPI *IoMmu,
238 IN EDKII_IOMMU_OPERATION Operation,
239 IN VOID *HostAddress,
240 IN OUT UINTN *NumberOfBytes,
241 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
242 OUT VOID **Mapping
243 );
244
252VOID
254 IN EDKII_IOMMU_PPI *IoMmu,
255 IN VOID *Mapping
256 );
257
279 IN EDKII_IOMMU_PPI *IoMmu,
280 IN UINTN Pages,
281 OUT VOID **HostAddress,
282 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
283 OUT VOID **Mapping
284 );
285
295VOID
297 IN EDKII_IOMMU_PPI *IoMmu,
298 IN UINTN Pages,
299 IN VOID *HostAddress,
300 IN VOID *Mapping
301 );
302
309VOID
310IoMmuInit (
311 OUT EDKII_IOMMU_PPI **IoMmu
312 );
313
314#endif
UINT64 UINTN
EFI_STATUS InitializeUsbHC(IN PEI_USB2_HC_DEV *EhcDev)
Definition: EhcPeim.c:1301
VOID IoMmuFreeBuffer(IN EDKII_IOMMU_PPI *IoMmu, IN UINTN Pages, IN VOID *HostAddress, IN VOID *Mapping)
Definition: DmaMem.c:217
VOID IoMmuUnmap(IN EDKII_IOMMU_PPI *IoMmu, IN VOID *Mapping)
Definition: DmaMem.c:103
EFI_STATUS UsbHcFreeMemPool(IN PEI_USB2_HC_DEV *Ehc, IN USBHC_MEM_POOL *Pool)
Definition: UsbHcMem.c:350
VOID UsbHcFreeMem(IN PEI_USB2_HC_DEV *Ehc, IN USBHC_MEM_POOL *Pool, IN VOID *Mem, IN UINTN Size)
Definition: UsbHcMem.c:458
VOID * UsbHcAllocateMem(IN PEI_USB2_HC_DEV *Ehc, IN USBHC_MEM_POOL *Pool, IN UINTN Size)
Definition: UsbHcMem.c:383
EFI_STATUS IoMmuMap(IN EDKII_IOMMU_PPI *IoMmu, IN EDKII_IOMMU_OPERATION Operation, IN VOID *HostAddress, IN OUT UINTN *NumberOfBytes, OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, OUT VOID **Mapping)
Definition: DmaMem.c:33
VOID IoMmuInit(OUT EDKII_IOMMU_PPI **IoMmu)
Definition: DmaMem.c:238
EFI_STATUS IoMmuAllocateBuffer(IN EDKII_IOMMU_PPI *IoMmu, IN UINTN Pages, OUT VOID **HostAddress, OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, OUT VOID **Mapping)
Definition: DmaMem.c:134
USBHC_MEM_POOL * UsbHcInitMemPool(IN PEI_USB2_HC_DEV *Ehc, IN BOOLEAN Check4G, IN UINT32 Which4G)
Definition: UsbHcMem.c:302
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
EDKII_IOMMU_OPERATION
Definition: IoMmu.h:44
UINT64 EFI_PHYSICAL_ADDRESS
Definition: UefiBaseType.h:50
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
VOID * EFI_EVENT
Definition: UefiBaseType.h:37