PciEnumerator.c

Go to the documentation of this file.

 
#include "PciBus.h"
 
EFI_STATUS
PciEnumerator (
  IN EFI_HANDLE  Controller,
  IN EFI_HANDLE  HostBridgeHandle
  )
{
  EFI_STATUS                                        Status;
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc;
 
  //
  // Get the pci host bridge resource allocation protocol
  //
  Status = gBS->OpenProtocol (
                  HostBridgeHandle,
                  &gEfiPciHostBridgeResourceAllocationProtocolGuid,
                  (VOID **)&PciResAlloc,
                  gPciBusDriverBinding.DriverBindingHandle,
                  Controller,
                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
                  );
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Notify the pci bus enumeration is about to begin
  //
  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Start the bus allocation phase
  //
  Status = PciHostBridgeEnumerator (PciResAlloc);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Submit the resource request
  //
  Status = PciHostBridgeResourceAllocator (PciResAlloc);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Notify the pci bus enumeration is about to complete
  //
  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Process P2C
  //
  Status = PciHostBridgeP2CProcess (PciResAlloc);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Process attributes for devices on this host bridge
  //
  Status = PciHostBridgeDeviceAttribute (PciResAlloc);
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  return EFI_SUCCESS;
}
 
EFI_STATUS
PciRootBridgeEnumerator (
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc,
  IN PCI_IO_DEVICE                                     *RootBridgeDev
  )
{
  EFI_STATUS                         Status;
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Configuration;
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Configuration1;
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Configuration2;
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Configuration3;
  UINT8                              SubBusNumber;
  UINT8                              StartBusNumber;
  UINT8                              PaddedBusRange;
  EFI_HANDLE                         RootBridgeHandle;
  UINT8                              Desc;
  UINT64                             AddrLen;
  UINT64                             AddrRangeMin;
 
  SubBusNumber   = 0;
  StartBusNumber = 0;
  PaddedBusRange = 0;
 
  //
  // Get the root bridge handle
  //
  RootBridgeHandle = RootBridgeDev->Handle;
 
  REPORT_STATUS_CODE_WITH_DEVICE_PATH (
    EFI_PROGRESS_CODE,
    EFI_IO_BUS_PCI | EFI_IOB_PCI_BUS_ENUM,
    RootBridgeDev->DevicePath
    );
 
  //
  // Get the Bus information
  //
  Status = PciResAlloc->StartBusEnumeration (
                          PciResAlloc,
                          RootBridgeHandle,
                          (VOID **)&Configuration
                          );
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  if ((Configuration == NULL) || (Configuration->Desc == ACPI_END_TAG_DESCRIPTOR)) {
    return EFI_INVALID_PARAMETER;
  }
 
  RootBridgeDev->BusNumberRanges = Configuration;
 
  //
  // Sort the descriptors in ascending order
  //
  for (Configuration1 = Configuration; Configuration1->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration1++) {
    Configuration2 = Configuration1;
    for (Configuration3 = Configuration1 + 1; Configuration3->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration3++) {
      if (Configuration2->AddrRangeMin > Configuration3->AddrRangeMin) {
        Configuration2 = Configuration3;
      }
    }
 
    //
    // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,
    // so only need to swap these two fields.
    //
    if (Configuration2 != Configuration1) {
      AddrRangeMin                 = Configuration1->AddrRangeMin;
      Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;
      Configuration2->AddrRangeMin = AddrRangeMin;
 
      AddrLen                 = Configuration1->AddrLen;
      Configuration1->AddrLen = Configuration2->AddrLen;
      Configuration2->AddrLen = AddrLen;
    }
  }
 
  //
  // Get the bus number to start with
  //
  StartBusNumber = (UINT8)(Configuration->AddrRangeMin);
 
  //
  // Initialize the subordinate bus number
  //
  SubBusNumber = StartBusNumber;
 
  //
  // Reset all assigned PCI bus number
  //
  ResetAllPpbBusNumber (
    RootBridgeDev,
    StartBusNumber
    );
 
  //
  // Assign bus number
  //
  Status = PciScanBus (
             RootBridgeDev,
             StartBusNumber,
             &SubBusNumber,
             &PaddedBusRange
             );
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Assign max bus number scanned
  //
 
  Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Find the bus range which contains the higest bus number, then returns the number of buses
  // that should be decoded.
  //
  while (Configuration->AddrRangeMin + Configuration->AddrLen - 1 < SubBusNumber) {
    Configuration++;
  }
 
  AddrLen                = Configuration->AddrLen;
  Configuration->AddrLen = SubBusNumber - Configuration->AddrRangeMin + 1;
 
  //
  // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.
  //
  Configuration++;
  Desc                = Configuration->Desc;
  Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;
 
  //
  // Set bus number
  //
  Status = PciResAlloc->SetBusNumbers (
                          PciResAlloc,
                          RootBridgeHandle,
                          RootBridgeDev->BusNumberRanges
                          );
 
  //
  // Restore changed fields
  //
  Configuration->Desc          = Desc;
  (Configuration - 1)->AddrLen = AddrLen;
 
  return Status;
}
 
VOID
ProcessOptionRom (
  IN PCI_IO_DEVICE  *Bridge,
  IN UINT64         RomBase,
  IN UINT64         MaxLength
  )
{
  LIST_ENTRY     *CurrentLink;
  PCI_IO_DEVICE  *Temp;
 
  //
  // Go through bridges to reach all devices
  //
  CurrentLink = Bridge->ChildList.ForwardLink;
  while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
    Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
    if (!IsListEmpty (&Temp->ChildList)) {
      //
      // Go further to process the option rom under this bridge
      //
      ProcessOptionRom (Temp, RomBase, MaxLength);
    }
 
    if ((Temp->RomSize != 0) && (Temp->RomSize <= MaxLength)) {
      //
      // Load and process the option rom
      //
      LoadOpRomImage (Temp, RomBase);
    }
 
    CurrentLink = CurrentLink->ForwardLink;
  }
}
 
EFI_STATUS
PciAssignBusNumber (
  IN PCI_IO_DEVICE  *Bridge,
  IN UINT8          StartBusNumber,
  OUT UINT8         *SubBusNumber
  )
{
  EFI_STATUS                       Status;
  PCI_TYPE00                       Pci;
  UINT8                            Device;
  UINT8                            Func;
  UINT64                           Address;
  UINTN                            SecondBus;
  UINT16                           Register;
  UINT8                            Register8;
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo;
 
  PciRootBridgeIo = Bridge->PciRootBridgeIo;
 
  SecondBus = 0;
  Register  = 0;
 
  *SubBusNumber = StartBusNumber;
 
  //
  // First check to see whether the parent is ppb
  //
  for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
    for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
      //
      // Check to see whether a pci device is present
      //
      Status = PciDevicePresent (
                 PciRootBridgeIo,
                 &Pci,
                 StartBusNumber,
                 Device,
                 Func
                 );
 
      if (EFI_ERROR (Status) && (Func == 0)) {
        //
        // go to next device if there is no Function 0
        //
        break;
      }
 
      if (!EFI_ERROR (Status)   &&
          (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)))
      {
        //
        // Reserved one bus for cardbus bridge
        //
        Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);
        if (EFI_ERROR (Status)) {
          return Status;
        }
 
        SecondBus = *SubBusNumber;
 
        Register = (UINT16)((SecondBus << 8) | (UINT16)StartBusNumber);
 
        Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
 
        Status = PciRootBridgeIo->Pci.Write (
                                        PciRootBridgeIo,
                                        EfiPciWidthUint16,
                                        Address,
                                        1,
                                        &Register
                                        );
 
        //
        // Initialize SubBusNumber to SecondBus
        //
        Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
        Status  = PciRootBridgeIo->Pci.Write (
                                         PciRootBridgeIo,
                                         EfiPciWidthUint8,
                                         Address,
                                         1,
                                         SubBusNumber
                                         );
        //
        // If it is PPB, resursively search down this bridge
        //
        if (IS_PCI_BRIDGE (&Pci)) {
          Register8 = 0xFF;
          Status    = PciRootBridgeIo->Pci.Write (
                                             PciRootBridgeIo,
                                             EfiPciWidthUint8,
                                             Address,
                                             1,
                                             &Register8
                                             );
 
          Status = PciAssignBusNumber (
                     Bridge,
                     (UINT8)(SecondBus),
                     SubBusNumber
                     );
 
          if (EFI_ERROR (Status)) {
            return EFI_DEVICE_ERROR;
          }
        }
 
        //
        // Set the current maximum bus number under the PPB
        //
        Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
 
        Status = PciRootBridgeIo->Pci.Write (
                                        PciRootBridgeIo,
                                        EfiPciWidthUint8,
                                        Address,
                                        1,
                                        SubBusNumber
                                        );
      }
 
      if ((Func == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {
        //
        // Skip sub functions, this is not a multi function device
        //
        Func = PCI_MAX_FUNC;
      }
    }
  }
 
  return EFI_SUCCESS;
}
 
EFI_STATUS
DetermineRootBridgeAttributes (
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc,
  IN PCI_IO_DEVICE                                     *RootBridgeDev
  )
{
  UINT64      Attributes;
  EFI_STATUS  Status;
  EFI_HANDLE  RootBridgeHandle;
 
  Attributes       = 0;
  RootBridgeHandle = RootBridgeDev->Handle;
 
  //
  // Get root bridge attribute by calling into pci host bridge resource allocation protocol
  //
  Status = PciResAlloc->GetAllocAttributes (
                          PciResAlloc,
                          RootBridgeHandle,
                          &Attributes
                          );
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Here is the point where PCI bus driver calls HOST bridge allocation protocol
  // Currently we hardcoded for ea815
  //
  if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {
    RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;
  }
 
  if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {
    RootBridgeDev->Decodes |= EFI_BRIDGE_MEM64_DECODE_SUPPORTED;
    RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;
  }
 
  RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;
  RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
  RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;
 
  return EFI_SUCCESS;
}
 
UINT32
GetMaxOptionRomSize (
  IN PCI_IO_DEVICE  *Bridge
  )
{
  LIST_ENTRY     *CurrentLink;
  PCI_IO_DEVICE  *Temp;
  UINT32         MaxOptionRomSize;
  UINT32         TempOptionRomSize;
 
  MaxOptionRomSize = 0;
 
  //
  // Go through bridges to reach all devices
  //
  CurrentLink = Bridge->ChildList.ForwardLink;
  while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
    Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
    if (!IsListEmpty (&Temp->ChildList)) {
      //
      // Get max option rom size under this bridge
      //
      TempOptionRomSize = GetMaxOptionRomSize (Temp);
 
      //
      // Compare with the option rom size of the bridge
      // Get the larger one
      //
      if (Temp->RomSize > TempOptionRomSize) {
        TempOptionRomSize = Temp->RomSize;
      }
    } else {
      //
      // For devices get the rom size directly
      //
      TempOptionRomSize = Temp->RomSize;
    }
 
    //
    // Get the largest rom size on this bridge
    //
    if (TempOptionRomSize > MaxOptionRomSize) {
      MaxOptionRomSize = TempOptionRomSize;
    }
 
    CurrentLink = CurrentLink->ForwardLink;
  }
 
  return MaxOptionRomSize;
}
 
EFI_STATUS
PciHostBridgeDeviceAttribute (
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc
  )
{
  EFI_HANDLE     RootBridgeHandle;
  PCI_IO_DEVICE  *RootBridgeDev;
  EFI_STATUS     Status;
 
  RootBridgeHandle = NULL;
 
  while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
    //
    // Get RootBridg Device by handle
    //
    RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
 
    if (RootBridgeDev == NULL) {
      return EFI_NOT_FOUND;
    }
 
    //
    // Set the attributes for devcies behind the Root Bridge
    //
    Status = DetermineDeviceAttribute (RootBridgeDev);
    if (EFI_ERROR (Status)) {
      return Status;
    }
  }
 
  return EFI_SUCCESS;
}
 
VOID
GetResourceAllocationStatus (
  VOID        *AcpiConfig,
  OUT UINT64  *IoResStatus,
  OUT UINT64  *Mem32ResStatus,
  OUT UINT64  *PMem32ResStatus,
  OUT UINT64  *Mem64ResStatus,
  OUT UINT64  *PMem64ResStatus
  )
{
  UINT8                              *Temp;
  UINT64                             ResStatus;
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *ACPIAddressDesc;
 
  Temp = (UINT8 *)AcpiConfig;
 
  while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
    ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp;
    ResStatus       = ACPIAddressDesc->AddrTranslationOffset;
 
    switch (ACPIAddressDesc->ResType) {
      case 0:
        if (ACPIAddressDesc->AddrSpaceGranularity == 32) {
          if (ACPIAddressDesc->SpecificFlag == 0x06) {
            //
            // Pmem32
            //
            *PMem32ResStatus = ResStatus;
          } else {
            //
            // Mem32
            //
            *Mem32ResStatus = ResStatus;
          }
        }
 
        if (ACPIAddressDesc->AddrSpaceGranularity == 64) {
          if (ACPIAddressDesc->SpecificFlag == 0x06) {
            //
            // PMem64
            //
            *PMem64ResStatus = ResStatus;
          } else {
            //
            // Mem64
            //
            *Mem64ResStatus = ResStatus;
          }
        }
 
        break;
 
      case 1:
        //
        // Io
        //
        *IoResStatus = ResStatus;
        break;
 
      default:
        break;
    }
 
    Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
  }
}
 
EFI_STATUS
RejectPciDevice (
  IN PCI_IO_DEVICE  *PciDevice
  )
{
  PCI_IO_DEVICE  *Bridge;
  PCI_IO_DEVICE  *Temp;
  LIST_ENTRY     *CurrentLink;
 
  //
  // Remove the padding resource from a bridge
  //
  if ( IS_PCI_BRIDGE (&PciDevice->Pci) &&
       (PciDevice->ResourcePaddingDescriptors != NULL))
  {
    FreePool (PciDevice->ResourcePaddingDescriptors);
    PciDevice->ResourcePaddingDescriptors = NULL;
    return EFI_SUCCESS;
  }
 
  //
  // Skip RB and PPB
  //
  if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {
    return EFI_ABORTED;
  }
 
  if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {
    //
    // Get the root bridge device
    //
    Bridge = PciDevice;
    while (Bridge->Parent != NULL) {
      Bridge = Bridge->Parent;
    }
 
    RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);
 
    //
    // Mark its bar
    //
    InitializeP2C (PciDevice);
  }
 
  //
  // Remove the device
  //
  Bridge      = PciDevice->Parent;
  CurrentLink = Bridge->ChildList.ForwardLink;
  while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
    Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
    if (Temp == PciDevice) {
      InitializePciDevice (Temp);
      RemoveEntryList (CurrentLink);
      return EFI_SUCCESS;
    }
 
    CurrentLink = CurrentLink->ForwardLink;
  }
 
  return EFI_ABORTED;
}
 
BOOLEAN
IsRejectiveDevice (
  IN  PCI_RESOURCE_NODE  *PciResNode
  )
{
  PCI_IO_DEVICE  *Temp;
 
  Temp = PciResNode->PciDev;
 
  //
  // Ensure the device is present
  //
  if (Temp == NULL) {
    return FALSE;
  }
 
  //
  // PPB and RB should go ahead
  //
  if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {
    return TRUE;
  }
 
  //
  // Skip device on Bus0
  //
  if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {
    return FALSE;
  }
 
  //
  // Skip VGA
  //
  if (IS_PCI_VGA (&Temp->Pci)) {
    return FALSE;
  }
 
  return TRUE;
}
 
PCI_RESOURCE_NODE *
GetLargerConsumerDevice (
  IN  PCI_RESOURCE_NODE  *PciResNode1,
  IN  PCI_RESOURCE_NODE  *PciResNode2
  )
{
  if (PciResNode2 == NULL) {
    return PciResNode1;
  }
 
  if (  (IS_PCI_BRIDGE (&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \
     && (PciResNode2->ResourceUsage != PciResUsagePadding))
  {
    return PciResNode1;
  }
 
  if (PciResNode1 == NULL) {
    return PciResNode2;
  }
 
  if ((PciResNode1->Length) > (PciResNode2->Length)) {
    return PciResNode1;
  }
 
  return PciResNode2;
}
 
PCI_RESOURCE_NODE *
GetMaxResourceConsumerDevice (
  IN  PCI_RESOURCE_NODE  *ResPool
  )
{
  PCI_RESOURCE_NODE  *Temp;
  LIST_ENTRY         *CurrentLink;
  PCI_RESOURCE_NODE  *PciResNode;
  PCI_RESOURCE_NODE  *PPBResNode;
 
  PciResNode = NULL;
 
  CurrentLink = ResPool->ChildList.ForwardLink;
  while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {
    Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
 
    if (!IsRejectiveDevice (Temp)) {
      CurrentLink = CurrentLink->ForwardLink;
      continue;
    }
 
    if (  (IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \
       && (Temp->ResourceUsage != PciResUsagePadding))
    {
      PPBResNode = GetMaxResourceConsumerDevice (Temp);
      PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);
    } else {
      PciResNode = GetLargerConsumerDevice (PciResNode, Temp);
    }
 
    CurrentLink = CurrentLink->ForwardLink;
  }
 
  return PciResNode;
}
 
EFI_STATUS
PciHostBridgeAdjustAllocation (
  IN  PCI_RESOURCE_NODE  *IoPool,
  IN  PCI_RESOURCE_NODE  *Mem32Pool,
  IN  PCI_RESOURCE_NODE  *PMem32Pool,
  IN  PCI_RESOURCE_NODE  *Mem64Pool,
  IN  PCI_RESOURCE_NODE  *PMem64Pool,
  IN  UINT64             IoResStatus,
  IN  UINT64             Mem32ResStatus,
  IN  UINT64             PMem32ResStatus,
  IN  UINT64             Mem64ResStatus,
  IN  UINT64             PMem64ResStatus
  )
{
  BOOLEAN                                        AllocationAjusted;
  PCI_RESOURCE_NODE                              *PciResNode;
  PCI_RESOURCE_NODE                              *ResPool[5];
  PCI_IO_DEVICE                                  *RemovedPciDev[5];
  UINT64                                         ResStatus[5];
  UINTN                                          RemovedPciDevNum;
  UINTN                                          DevIndex;
  UINTN                                          ResType;
  EFI_STATUS                                     Status;
  EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD  AllocFailExtendedData;
 
  PciResNode = NULL;
  ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));
  RemovedPciDevNum = 0;
 
  ResPool[0] = IoPool;
  ResPool[1] = Mem32Pool;
  ResPool[2] = PMem32Pool;
  ResPool[3] = Mem64Pool;
  ResPool[4] = PMem64Pool;
 
  ResStatus[0] = IoResStatus;
  ResStatus[1] = Mem32ResStatus;
  ResStatus[2] = PMem32ResStatus;
  ResStatus[3] = Mem64ResStatus;
  ResStatus[4] = PMem64ResStatus;
 
  AllocationAjusted = FALSE;
 
  for (ResType = 0; ResType < 5; ResType++) {
    if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {
      continue;
    }
 
    if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {
      //
      // Host bridge hasn't this resource type
      //
      return EFI_ABORTED;
    }
 
    //
    // Hostbridge hasn't enough resource
    //
    PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);
    if (PciResNode == NULL) {
      continue;
    }
 
    //
    // Check if the device has been removed before
    //
    for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {
      if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {
        break;
      }
    }
 
    if (DevIndex != RemovedPciDevNum) {
      continue;
    }
 
    //
    // Remove the device if it isn't in the array
    //
    Status = RejectPciDevice (PciResNode->PciDev);
    if (Status == EFI_SUCCESS) {
      DEBUG ((
        DEBUG_ERROR,
        "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
        PciResNode->PciDev->BusNumber,
        PciResNode->PciDev->DeviceNumber,
        PciResNode->PciDev->FunctionNumber
        ));
 
      //
      // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
      //
      //
      // Have no way to get ReqRes, AllocRes & Bar here
      //
      ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));
      AllocFailExtendedData.DevicePathSize = (UINT16)sizeof (EFI_DEVICE_PATH_PROTOCOL);
      AllocFailExtendedData.DevicePath     = (UINT8 *)PciResNode->PciDev->DevicePath;
      AllocFailExtendedData.Bar            = PciResNode->Bar;
 
      REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
        EFI_PROGRESS_CODE,
        EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
        (VOID *)&AllocFailExtendedData,
        sizeof (AllocFailExtendedData)
        );
 
      //
      // Add it to the array and indicate at least a device has been rejected
      //
      RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;
      AllocationAjusted                 = TRUE;
    }
  }
 
  //
  // End for
  //
 
  if (AllocationAjusted) {
    return EFI_SUCCESS;
  } else {
    return EFI_ABORTED;
  }
}
 
EFI_STATUS
ConstructAcpiResourceRequestor (
  IN PCI_IO_DEVICE      *Bridge,
  IN PCI_RESOURCE_NODE  *IoNode,
  IN PCI_RESOURCE_NODE  *Mem32Node,
  IN PCI_RESOURCE_NODE  *PMem32Node,
  IN PCI_RESOURCE_NODE  *Mem64Node,
  IN PCI_RESOURCE_NODE  *PMem64Node,
  OUT VOID              **Config
  )
{
  UINT8                              NumConfig;
  UINT8                              Aperture;
  UINT8                              *Configuration;
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Ptr;
  EFI_ACPI_END_TAG_DESCRIPTOR        *PtrEnd;
 
  NumConfig = 0;
  Aperture  = 0;
 
  *Config = NULL;
 
  //
  // if there is io request, add to the io aperture
  //
  if (ResourceRequestExisted (IoNode)) {
    NumConfig++;
    Aperture |= 0x01;
  }
 
  //
  // if there is mem32 request, add to the mem32 aperture
  //
  if (ResourceRequestExisted (Mem32Node)) {
    NumConfig++;
    Aperture |= 0x02;
  }
 
  //
  // if there is pmem32 request, add to the pmem32 aperture
  //
  if (ResourceRequestExisted (PMem32Node)) {
    NumConfig++;
    Aperture |= 0x04;
  }
 
  //
  // if there is mem64 request, add to the mem64 aperture
  //
  if (ResourceRequestExisted (Mem64Node)) {
    NumConfig++;
    Aperture |= 0x08;
  }
 
  //
  // if there is pmem64 request, add to the pmem64 aperture
  //
  if (ResourceRequestExisted (PMem64Node)) {
    NumConfig++;
    Aperture |= 0x10;
  }
 
  if (NumConfig != 0) {
    //
    // If there is at least one type of resource request,
    // allocate a acpi resource node
    //
    Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
    if (Configuration == NULL) {
      return EFI_OUT_OF_RESOURCES;
    }
 
    Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
 
    //
    // Deal with io aperture
    //
    if ((Aperture & 0x01) != 0) {
      Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
      Ptr->Len  = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
      //
      // Io
      //
      Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
      //
      // non ISA range
      //
      Ptr->SpecificFlag = 1;
      Ptr->AddrLen      = IoNode->Length;
      Ptr->AddrRangeMax = IoNode->Alignment;
 
      Ptr++;
    }
 
    //
    // Deal with mem32 aperture
    //
    if ((Aperture & 0x02) != 0) {
      Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
      Ptr->Len  = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
      //
      // Mem
      //
      Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
      //
      // Nonprefechable
      //
      Ptr->SpecificFlag = 0;
      //
      // 32 bit
      //
      Ptr->AddrSpaceGranularity = 32;
      Ptr->AddrLen              = Mem32Node->Length;
      Ptr->AddrRangeMax         = Mem32Node->Alignment;
 
      Ptr++;
    }
 
    //
    // Deal with Pmem32 aperture
    //
    if ((Aperture & 0x04) != 0) {
      Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
      Ptr->Len  = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
      //
      // Mem
      //
      Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
      //
      // prefechable
      //
      Ptr->SpecificFlag = 0x6;
      //
      // 32 bit
      //
      Ptr->AddrSpaceGranularity = 32;
      Ptr->AddrLen              = PMem32Node->Length;
      Ptr->AddrRangeMax         = PMem32Node->Alignment;
 
      Ptr++;
    }
 
    //
    // Deal with mem64 aperture
    //
    if ((Aperture & 0x08) != 0) {
      Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
      Ptr->Len  = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
      //
      // Mem
      //
      Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
      //
      // nonprefechable
      //
      Ptr->SpecificFlag = 0;
      //
      // 64 bit
      //
      Ptr->AddrSpaceGranularity = 64;
      Ptr->AddrLen              = Mem64Node->Length;
      Ptr->AddrRangeMax         = Mem64Node->Alignment;
 
      Ptr++;
    }
 
    //
    // Deal with Pmem64 aperture
    //
    if ((Aperture & 0x10) != 0) {
      Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
      Ptr->Len  = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
      //
      // Mem
      //
      Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
      //
      // prefechable
      //
      Ptr->SpecificFlag = 0x06;
      //
      // 64 bit
      //
      Ptr->AddrSpaceGranularity = 64;
      Ptr->AddrLen              = PMem64Node->Length;
      Ptr->AddrRangeMax         = PMem64Node->Alignment;
 
      Ptr++;
    }
 
    //
    // put the checksum
    //
    PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr;
 
    PtrEnd->Desc     = ACPI_END_TAG_DESCRIPTOR;
    PtrEnd->Checksum = 0;
  } else {
    //
    // If there is no resource request
    //
    Configuration = AllocateZeroPool (sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
    if (Configuration == NULL) {
      return EFI_OUT_OF_RESOURCES;
    }
 
    PtrEnd           = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Configuration);
    PtrEnd->Desc     = ACPI_END_TAG_DESCRIPTOR;
    PtrEnd->Checksum = 0;
  }
 
  *Config = Configuration;
 
  return EFI_SUCCESS;
}
 
VOID
GetResourceBase (
  IN VOID     *Config,
  OUT UINT64  *IoBase,
  OUT UINT64  *Mem32Base,
  OUT UINT64  *PMem32Base,
  OUT UINT64  *Mem64Base,
  OUT UINT64  *PMem64Base
  )
{
  UINT8                              *Temp;
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Ptr;
  UINT64                             ResStatus;
 
  ASSERT (Config != NULL);
 
  *IoBase     = 0xFFFFFFFFFFFFFFFFULL;
  *Mem32Base  = 0xFFFFFFFFFFFFFFFFULL;
  *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;
  *Mem64Base  = 0xFFFFFFFFFFFFFFFFULL;
  *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;
 
  Temp = (UINT8 *)Config;
 
  while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
    Ptr       = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp;
    ResStatus = Ptr->AddrTranslationOffset;
 
    if (ResStatus == EFI_RESOURCE_SATISFIED) {
      switch (Ptr->ResType) {
        //
        // Memory type aperture
        //
        case 0:
 
          //
          // Check to see the granularity
          //
          if (Ptr->AddrSpaceGranularity == 32) {
            if ((Ptr->SpecificFlag & 0x06) != 0) {
              *PMem32Base = Ptr->AddrRangeMin;
            } else {
              *Mem32Base = Ptr->AddrRangeMin;
            }
          }
 
          if (Ptr->AddrSpaceGranularity == 64) {
            if ((Ptr->SpecificFlag & 0x06) != 0) {
              *PMem64Base = Ptr->AddrRangeMin;
            } else {
              *Mem64Base = Ptr->AddrRangeMin;
            }
          }
 
          break;
 
        case 1:
 
          //
          // Io type aperture
          //
          *IoBase = Ptr->AddrRangeMin;
          break;
 
        default:
          break;
      }
 
      //
      // End switch
      //
    }
 
    //
    // End for
    //
    Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
  }
}
 
EFI_STATUS
PciBridgeEnumerator (
  IN PCI_IO_DEVICE  *BridgeDev
  )
{
  UINT8                SubBusNumber;
  UINT8                StartBusNumber;
  EFI_PCI_IO_PROTOCOL  *PciIo;
  EFI_STATUS           Status;
 
  SubBusNumber   = 0;
  StartBusNumber = 0;
  PciIo          = &(BridgeDev->PciIo);
  Status         = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  Status = PciAssignBusNumber (
             BridgeDev,
             StartBusNumber,
             &SubBusNumber
             );
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  Status = PciBridgeResourceAllocator (BridgeDev);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  Status = DetermineDeviceAttribute (BridgeDev);
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  return EFI_SUCCESS;
}
 
EFI_STATUS
PciBridgeResourceAllocator (
  IN PCI_IO_DEVICE  *Bridge
  )
{
  PCI_RESOURCE_NODE  *IoBridge;
  PCI_RESOURCE_NODE  *Mem32Bridge;
  PCI_RESOURCE_NODE  *PMem32Bridge;
  PCI_RESOURCE_NODE  *Mem64Bridge;
  PCI_RESOURCE_NODE  *PMem64Bridge;
  UINT64             IoBase;
  UINT64             Mem32Base;
  UINT64             PMem32Base;
  UINT64             Mem64Base;
  UINT64             PMem64Base;
  EFI_STATUS         Status;
 
  IoBridge = CreateResourceNode (
               Bridge,
               0,
               Bridge->BridgeIoAlignment,
               0,
               PciBarTypeIo16,
               PciResUsageTypical
               );
 
  Mem32Bridge = CreateResourceNode (
                  Bridge,
                  0,
                  0xFFFFF,
                  0,
                  PciBarTypeMem32,
                  PciResUsageTypical
                  );
 
  PMem32Bridge = CreateResourceNode (
                   Bridge,
                   0,
                   0xFFFFF,
                   0,
                   PciBarTypePMem32,
                   PciResUsageTypical
                   );
 
  Mem64Bridge = CreateResourceNode (
                  Bridge,
                  0,
                  0xFFFFF,
                  0,
                  PciBarTypeMem64,
                  PciResUsageTypical
                  );
 
  PMem64Bridge = CreateResourceNode (
                   Bridge,
                   0,
                   0xFFFFF,
                   0,
                   PciBarTypePMem64,
                   PciResUsageTypical
                   );
 
  //
  // Create resourcemap by going through all the devices subject to this root bridge
  //
  CreateResourceMap (
    Bridge,
    IoBridge,
    Mem32Bridge,
    PMem32Bridge,
    Mem64Bridge,
    PMem64Bridge
    );
 
  Status = GetResourceBaseFromBridge (
             Bridge,
             &IoBase,
             &Mem32Base,
             &PMem32Base,
             &Mem64Base,
             &PMem64Base
             );
 
  if (EFI_ERROR (Status)) {
    return Status;
  }
 
  //
  // Program IO resources
  //
  ProgramResource (
    IoBase,
    IoBridge
    );
 
  //
  // Program Mem32 resources
  //
  ProgramResource (
    Mem32Base,
    Mem32Bridge
    );
 
  //
  // Program PMem32 resources
  //
  ProgramResource (
    PMem32Base,
    PMem32Bridge
    );
 
  //
  // Program Mem64 resources
  //
  ProgramResource (
    Mem64Base,
    Mem64Bridge
    );
 
  //
  // Program PMem64 resources
  //
  ProgramResource (
    PMem64Base,
    PMem64Bridge
    );
 
  DestroyResourceTree (IoBridge);
  DestroyResourceTree (Mem32Bridge);
  DestroyResourceTree (PMem32Bridge);
  DestroyResourceTree (PMem64Bridge);
  DestroyResourceTree (Mem64Bridge);
 
  gBS->FreePool (IoBridge);
  gBS->FreePool (Mem32Bridge);
  gBS->FreePool (PMem32Bridge);
  gBS->FreePool (PMem64Bridge);
  gBS->FreePool (Mem64Bridge);
 
  return EFI_SUCCESS;
}
 
EFI_STATUS
GetResourceBaseFromBridge (
  IN  PCI_IO_DEVICE  *Bridge,
  OUT UINT64         *IoBase,
  OUT UINT64         *Mem32Base,
  OUT UINT64         *PMem32Base,
  OUT UINT64         *Mem64Base,
  OUT UINT64         *PMem64Base
  )
{
  if (!Bridge->Allocated) {
    return EFI_OUT_OF_RESOURCES;
  }
 
  *IoBase     = gAllOne;
  *Mem32Base  = gAllOne;
  *PMem32Base = gAllOne;
  *Mem64Base  = gAllOne;
  *PMem64Base = gAllOne;
 
  if (IS_PCI_BRIDGE (&Bridge->Pci)) {
    if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {
      *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;
    }
 
    if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {
      *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;
    }
 
    if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {
      *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;
    }
 
    if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {
      *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;
    } else {
      *PMem64Base = gAllOne;
    }
  }
 
  if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {
    if (Bridge->PciBar[P2C_IO_1].Length > 0) {
      *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;
    } else {
      if (Bridge->PciBar[P2C_IO_2].Length > 0) {
        *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;
      }
    }
 
    if (Bridge->PciBar[P2C_MEM_1].Length > 0) {
      if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {
        *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;
      }
 
      if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {
        *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;
      }
    }
 
    if (Bridge->PciBar[P2C_MEM_2].Length > 0) {
      if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {
        *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;
      }
 
      if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {
        *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;
      }
    }
  }
 
  return EFI_SUCCESS;
}
 
EFI_STATUS
NotifyPhase (
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc,
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE        Phase
  )
{
  EFI_HANDLE                       HostBridgeHandle;
  EFI_HANDLE                       RootBridgeHandle;
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo;
  EFI_STATUS                       Status;
 
  HostBridgeHandle = NULL;
  RootBridgeHandle = NULL;
  if (gPciPlatformProtocol != NULL) {
    //
    // Get Host Bridge Handle.
    //
    PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);
 
    //
    // Get the rootbridge Io protocol to find the host bridge handle
    //
    Status = gBS->HandleProtocol (
                    RootBridgeHandle,
                    &gEfiPciRootBridgeIoProtocolGuid,
                    (VOID **)&PciRootBridgeIo
                    );
 
    if (EFI_ERROR (Status)) {
      return EFI_NOT_FOUND;
    }
 
    HostBridgeHandle = PciRootBridgeIo->ParentHandle;
 
    //
    // Call PlatformPci::PlatformNotify() if the protocol is present.
    //
    gPciPlatformProtocol->PlatformNotify (
                            gPciPlatformProtocol,
                            HostBridgeHandle,
                            Phase,
                            ChipsetEntry
                            );
  } else if (gPciOverrideProtocol != NULL) {
    //
    // Get Host Bridge Handle.
    //
    PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);
 
    //
    // Get the rootbridge Io protocol to find the host bridge handle
    //
    Status = gBS->HandleProtocol (
                    RootBridgeHandle,
                    &gEfiPciRootBridgeIoProtocolGuid,
                    (VOID **)&PciRootBridgeIo
                    );
 
    if (EFI_ERROR (Status)) {
      return EFI_NOT_FOUND;
    }
 
    HostBridgeHandle = PciRootBridgeIo->ParentHandle;
 
    //
    // Call PlatformPci::PhaseNotify() if the protocol is present.
    //
    gPciOverrideProtocol->PlatformNotify (
                            gPciOverrideProtocol,
                            HostBridgeHandle,
                            Phase,
                            ChipsetEntry
                            );
  }
 
  Status = PciResAlloc->NotifyPhase (
                          PciResAlloc,
                          Phase
                          );
 
  if (gPciPlatformProtocol != NULL) {
    //
    // Call PlatformPci::PlatformNotify() if the protocol is present.
    //
    gPciPlatformProtocol->PlatformNotify (
                            gPciPlatformProtocol,
                            HostBridgeHandle,
                            Phase,
                            ChipsetExit
                            );
  } else if (gPciOverrideProtocol != NULL) {
    //
    // Call PlatformPci::PhaseNotify() if the protocol is present.
    //
    gPciOverrideProtocol->PlatformNotify (
                            gPciOverrideProtocol,
                            HostBridgeHandle,
                            Phase,
                            ChipsetExit
                            );
  }
 
  return Status;
}
 
EFI_STATUS
PreprocessController (
  IN PCI_IO_DEVICE                                 *Bridge,
  IN UINT8                                         Bus,
  IN UINT8                                         Device,
  IN UINT8                                         Func,
  IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE  Phase
  )
{
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS       RootBridgePciAddress;
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc;
  EFI_HANDLE                                        RootBridgeHandle;
  EFI_HANDLE                                        HostBridgeHandle;
  EFI_STATUS                                        Status;
 
  //
  // Get the host bridge handle
  //
  HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;
 
  //
  // Get the pci host bridge resource allocation protocol
  //
  Status = gBS->OpenProtocol (
                  HostBridgeHandle,
                  &gEfiPciHostBridgeResourceAllocationProtocolGuid,
                  (VOID **)&PciResAlloc,
                  NULL,
                  NULL,
                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
                  );
 
  if (EFI_ERROR (Status)) {
    return EFI_UNSUPPORTED;
  }
 
  //
  // Get Root Brige Handle
  //
  while (Bridge->Parent != NULL) {
    Bridge = Bridge->Parent;
  }
 
  RootBridgeHandle = Bridge->Handle;
 
  RootBridgePciAddress.Register         = 0;
  RootBridgePciAddress.Function         = Func;
  RootBridgePciAddress.Device           = Device;
  RootBridgePciAddress.Bus              = Bus;
  RootBridgePciAddress.ExtendedRegister = 0;
 
  if (gPciPlatformProtocol != NULL) {
    //
    // Call PlatformPci::PrepController() if the protocol is present.
    //
    gPciPlatformProtocol->PlatformPrepController (
                            gPciPlatformProtocol,
                            HostBridgeHandle,
                            RootBridgeHandle,
                            RootBridgePciAddress,
                            Phase,
                            ChipsetEntry
                            );
  } else if (gPciOverrideProtocol != NULL) {
    //
    // Call PlatformPci::PrepController() if the protocol is present.
    //
    gPciOverrideProtocol->PlatformPrepController (
                            gPciOverrideProtocol,
                            HostBridgeHandle,
                            RootBridgeHandle,
                            RootBridgePciAddress,
                            Phase,
                            ChipsetEntry
                            );
  }
 
  Status = PciResAlloc->PreprocessController (
                          PciResAlloc,
                          RootBridgeHandle,
                          RootBridgePciAddress,
                          Phase
                          );
 
  if (gPciPlatformProtocol != NULL) {
    //
    // Call PlatformPci::PrepController() if the protocol is present.
    //
    gPciPlatformProtocol->PlatformPrepController (
                            gPciPlatformProtocol,
                            HostBridgeHandle,
                            RootBridgeHandle,
                            RootBridgePciAddress,
                            Phase,
                            ChipsetExit
                            );
  } else if (gPciOverrideProtocol != NULL) {
    //
    // Call PlatformPci::PrepController() if the protocol is present.
    //
    gPciOverrideProtocol->PlatformPrepController (
                            gPciOverrideProtocol,
                            HostBridgeHandle,
                            RootBridgeHandle,
                            RootBridgePciAddress,
                            Phase,
                            ChipsetExit
                            );
  }
 
  return EFI_SUCCESS;
}
 
EFI_STATUS
EFIAPI
PciHotPlugRequestNotify (
  IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL  *This,
  IN EFI_PCI_HOTPLUG_OPERATION         Operation,
  IN EFI_HANDLE                        Controller,
  IN EFI_DEVICE_PATH_PROTOCOL          *RemainingDevicePath OPTIONAL,
  IN OUT UINT8                         *NumberOfChildren,
  IN OUT EFI_HANDLE                    *ChildHandleBuffer
  )
{
  PCI_IO_DEVICE        *Bridge;
  PCI_IO_DEVICE        *Temp;
  EFI_PCI_IO_PROTOCOL  *PciIo;
  UINTN                Index;
  EFI_HANDLE           RootBridgeHandle;
  EFI_STATUS           Status;
 
  //
  // Check input parameter validity
  //
  if ((Controller == NULL) || (NumberOfChildren == NULL)) {
    return EFI_INVALID_PARAMETER;
  }
 
  if ((Operation != EfiPciHotPlugRequestAdd) && (Operation != EfiPciHotplugRequestRemove)) {
    return EFI_INVALID_PARAMETER;
  }
 
  if (Operation == EfiPciHotPlugRequestAdd) {
    if (ChildHandleBuffer == NULL) {
      return EFI_INVALID_PARAMETER;
    }
  } else if ((Operation == EfiPciHotplugRequestRemove) && (*NumberOfChildren != 0)) {
    if (ChildHandleBuffer == NULL) {
      return EFI_INVALID_PARAMETER;
    }
  }
 
  Status = gBS->OpenProtocol (
                  Controller,
                  &gEfiPciIoProtocolGuid,
                  (VOID **)&PciIo,
                  gPciBusDriverBinding.DriverBindingHandle,
                  Controller,
                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
                  );
 
  if (EFI_ERROR (Status)) {
    return EFI_NOT_FOUND;
  }
 
  Bridge = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
 
  //
  // Get root bridge handle
  //
  Temp = Bridge;
  while (Temp->Parent != NULL) {
    Temp = Temp->Parent;
  }
 
  RootBridgeHandle = Temp->Handle;
 
  if (Operation == EfiPciHotPlugRequestAdd) {
    //
    // Report Status Code to indicate hot plug happens
    //
    REPORT_STATUS_CODE_WITH_DEVICE_PATH (
      EFI_PROGRESS_CODE,
      (EFI_IO_BUS_PCI | EFI_IOB_PC_HOTPLUG),
      Temp->DevicePath
      );
 
    if (NumberOfChildren != NULL) {
      *NumberOfChildren = 0;
    }
 
    if (IsListEmpty (&Bridge->ChildList)) {
      Status = PciBridgeEnumerator (Bridge);
 
      if (EFI_ERROR (Status)) {
        return Status;
      }
    }
 
    Status = StartPciDevicesOnBridge (
               RootBridgeHandle,
               Bridge,
               RemainingDevicePath,
               NumberOfChildren,
               ChildHandleBuffer
               );
 
    return Status;
  }
 
  if (Operation == EfiPciHotplugRequestRemove) {
    if (*NumberOfChildren == 0) {
      //
      // Remove all devices on the bridge
      //
      RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);
      return EFI_SUCCESS;
    }
 
    for (Index = 0; Index < *NumberOfChildren; Index++) {
      //
      // De register all the pci device
      //
      Status = DeRegisterPciDevice (RootBridgeHandle, ChildHandleBuffer[Index]);
 
      if (EFI_ERROR (Status)) {
        return Status;
      }
    }
 
    //
    // End for
    //
    return EFI_SUCCESS;
  }
 
  return EFI_SUCCESS;
}
 
BOOLEAN
SearchHostBridgeHandle (
  IN EFI_HANDLE  RootBridgeHandle
  )
{
  EFI_HANDLE                       HostBridgeHandle;
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo;
  UINTN                            Index;
  EFI_STATUS                       Status;
 
  //
  // Get the rootbridge Io protocol to find the host bridge handle
  //
  Status = gBS->OpenProtocol (
                  RootBridgeHandle,
                  &gEfiPciRootBridgeIoProtocolGuid,
                  (VOID **)&PciRootBridgeIo,
                  gPciBusDriverBinding.DriverBindingHandle,
                  RootBridgeHandle,
                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
                  );
 
  if (EFI_ERROR (Status)) {
    return FALSE;
  }
 
  HostBridgeHandle = PciRootBridgeIo->ParentHandle;
  for (Index = 0; Index < gPciHostBridgeNumber; Index++) {
    if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {
      return TRUE;
    }
  }
 
  return FALSE;
}
 
EFI_STATUS
AddHostBridgeEnumerator (
  IN EFI_HANDLE  HostBridgeHandle
  )
{
  UINTN  Index;
 
  if (HostBridgeHandle == NULL) {
    return EFI_ABORTED;
  }
 
  for (Index = 0; Index < gPciHostBridgeNumber; Index++) {
    if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {
      return EFI_ABORTED;
    }
  }
 
  if (Index < PCI_MAX_HOST_BRIDGE_NUM) {
    gPciHostBrigeHandles[Index] = HostBridgeHandle;
    gPciHostBridgeNumber++;
  }
 
  return EFI_SUCCESS;
}