20#include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>
43Q35TsegMbytesInitialization (
47 UINT16 ExtendedTsegMbytes;
48 RETURN_STATUS PcdStatus;
50 ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
68 PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);
69 ExtendedTsegMbytes =
PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));
70 if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {
71 PlatformInfoHob->Q35TsegMbytes =
PcdGet16 (PcdQ35TsegMbytes);
77 "%a: QEMU offers an extended TSEG (%d MB)\n",
81 PcdStatus =
PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
83 PlatformInfoHob->Q35TsegMbytes = ExtendedTsegMbytes;
87Q35SmramAtDefaultSmbaseInitialization (
91 RETURN_STATUS PcdStatus;
95 ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
97 CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);
98 PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);
100 PlatformInfoHob->Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==
101 MCH_DEFAULT_SMBASE_IN_RAM);
104 "%a: SMRAM at default SMBASE %a\n",
106 PlatformInfoHob->Q35SmramAtDefaultSmbase ?
"found" :
"not found"
110 PcdQ35SmramAtDefaultSmbase,
111 PlatformInfoHob->Q35SmramAtDefaultSmbase
124 RETURN_STATUS PcdStatus;
140 if (PlatformInfoHob->PcdPciMmio64Size == 0) {
141 if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
144 "%a: disabling 64-bit PCI host aperture\n",
147 PcdStatus =
PcdSet64S (PcdPciMmio64Size, 0);
154 if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
160 PcdStatus =
PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);
162 PcdStatus =
PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);
167 "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
169 PlatformInfoHob->PcdPciMmio64Base,
170 PlatformInfoHob->PcdPciMmio64Size
184 BOOLEAN Page1GSupport;
211 Page1GSupport =
FALSE;
214 if (RegEax >= 0x80000001) {
216 if ((RegEdx & BIT26) != 0) {
217 Page1GSupport =
TRUE;
236 MaxAddr =
LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth);
237 Level2Pages = (UINT32)
RShiftU64 (MaxAddr, 30);
238 Level3Pages =
MAX (Level2Pages >> 9, 1u);
239 Level4Pages =
MAX (Level3Pages >> 9, 1u);
244 TotalPages = Level5Pages + Level4Pages + Level3Pages;
245 ASSERT (TotalPages <= 0x40201);
247 TotalPages = Level5Pages + Level4Pages + Level3Pages + Level2Pages;
249 ASSERT (PlatformInfoHob->PhysMemAddressWidth <= 40);
250 ASSERT (TotalPages <= 0x404);
257 ApStacks = PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber *
PcdGet32 (PcdCpuApStackSize);
268 "%a: page tables: %6lu KB (%u/%u/%u/%u pages for levels 5/4/3/2)\n",
278 "%a: ap stacks: %6lu KB (%u cpus)\n",
281 PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber
285 "%a: memory cap: %6lu KB\n",
290 ASSERT (MemoryCap <= MAX_UINT32);
291 return (UINT32)MemoryCap;
308 UINT32 LowerMemorySize;
310 UINT32 S3AcpiReservedMemoryBase;
311 UINT32 S3AcpiReservedMemorySize;
313 PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
314 LowerMemorySize = PlatformInfoHob->LowMemory;
315 if (PlatformInfoHob->SmmSmramRequire) {
319 LowerMemorySize -= PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;
322 S3AcpiReservedMemoryBase = 0;
323 S3AcpiReservedMemorySize = 0;
330 if (PlatformInfoHob->S3Supported) {
331 S3AcpiReservedMemorySize = SIZE_512KB +
332 PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber *
334 S3AcpiReservedMemoryBase = LowerMemorySize - S3AcpiReservedMemorySize;
335 LowerMemorySize = S3AcpiReservedMemoryBase;
338 PlatformInfoHob->S3AcpiReservedMemoryBase = S3AcpiReservedMemoryBase;
339 PlatformInfoHob->S3AcpiReservedMemorySize = S3AcpiReservedMemorySize;
341 if (PlatformInfoHob->BootMode == BOOT_ON_S3_RESUME) {
342 MemoryBase = S3AcpiReservedMemoryBase;
343 MemorySize = S3AcpiReservedMemorySize;
348 "%a: PhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
350 PlatformInfoHob->PhysMemAddressWidth,
364 MemoryBase = PlatformInfoHob->S3Supported && PlatformInfoHob->SmmSmramRequire ?
365 PcdGet32 (PcdOvmfDecompressionScratchEnd) :
367 MemorySize = LowerMemorySize - MemoryBase;
368 if (MemorySize > PeiMemoryCap) {
369 MemoryBase = LowerMemorySize - PeiMemoryCap;
370 MemorySize = PeiMemoryCap;
374 "%a: Not enough memory for PEI (have %lu KB, estimated need %u KB)\n",
387 if (PlatformInfoHob->SmmSmramRequire && PlatformInfoHob->Q35SmramAtDefaultSmbase) {
418 PlatformQemuInitializeRamForS3 (PlatformInfoHob);
UINT64 EFIAPI RShiftU64(IN UINT64 Operand, IN UINTN Count)
UINT64 EFIAPI LShiftU64(IN UINT64 Operand, IN UINTN Count)
#define ASSERT_EFI_ERROR(StatusParameter)
#define ASSERT_RETURN_ERROR(StatusParameter)
#define DEBUG(Expression)
UINT8 EFIAPI PciRead8(IN UINTN Address)
UINT8 EFIAPI PciWrite8(IN UINTN Address, IN UINT8 Value)
UINT16 EFIAPI PciWrite16(IN UINTN Address, IN UINT16 Value)
UINT16 EFIAPI PciRead16(IN UINTN Address)
#define SMM_DEFAULT_SMBASE
UINT32 EFIAPI AsmCpuid(IN UINT32 Index, OUT UINT32 *RegisterEax OPTIONAL, OUT UINT32 *RegisterEbx OPTIONAL, OUT UINT32 *RegisterEcx OPTIONAL, OUT UINT32 *RegisterEdx OPTIONAL)
BOOLEAN EFIAPI TdIsEnabled()
#define PcdGet16(TokenName)
#define PcdSetBoolS(TokenName, Value)
#define PcdGet32(TokenName)
#define PcdGetBool(TokenName)
#define PcdSet64S(TokenName, Value)
#define PcdSet16S(TokenName, Value)
#define FeaturePcdGet(TokenName)
RETURN_STATUS EFIAPI PublishSystemMemory(IN PHYSICAL_ADDRESS MemoryBegin, IN UINT64 MemoryLength)
UINT64 EFI_PHYSICAL_ADDRESS
#define EFI_PAGES_TO_SIZE(Pages)