40#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"
41#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"
42#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)
47#define TIMEOUT_STALL_INTERVAL 10
75#define SERIAL_MAX_FIFO_SIZE 17
114 BOOLEAN SoftwareLoopbackEnable;
115 BOOLEAN HardwareFlowControl;
122#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')
123#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
128#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
129#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \
130 EFI_SERIAL_DATA_SET_READY | \
131 EFI_SERIAL_RING_INDICATE | \
132 EFI_SERIAL_CARRIER_DETECT | \
133 EFI_SERIAL_REQUEST_TO_SEND | \
134 EFI_SERIAL_DATA_TERMINAL_READY | \
135 EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE | \
136 EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
137 EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE | \
138 EFI_SERIAL_OUTPUT_BUFFER_EMPTY | \
139 EFI_SERIAL_INPUT_BUFFER_EMPTY)
141#define SERIAL_PORT_MIN_TIMEOUT 1
142#define SERIAL_PORT_MAX_TIMEOUT 100000000
146#define SERIAL_REGISTER_THR 0
147#define SERIAL_REGISTER_RBR 0
148#define SERIAL_REGISTER_DLL 0
149#define SERIAL_REGISTER_DLM 1
150#define SERIAL_REGISTER_IER 1
151#define SERIAL_REGISTER_IIR 2
152#define SERIAL_REGISTER_FCR 2
153#define SERIAL_REGISTER_LCR 3
154#define SERIAL_REGISTER_MCR 4
155#define SERIAL_REGISTER_LSR 5
156#define SERIAL_REGISTER_MSR 6
157#define SERIAL_REGISTER_SCR 7
259#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)
260#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)
261#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)
262#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)
263#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)
264#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)
265#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)
266#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)
267#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)
268#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)
270#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)
271#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)
272#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)
273#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)
274#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)
275#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)
276#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)
277#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)
278#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)
279#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)
383 IN UINT32 ReceiveFifoDepth,
630 OUT CHAR16 **DriverName
708 OUT CHAR16 **ControllerName
751 OUT UINT64 *ActualBaudRate
767 BOOLEAN *ContainsControllerNode,
768 UINT32 *ControllerNumber
BOOLEAN SerialFifoFull(IN SERIAL_DEV_FIFO *Fifo)
BOOLEAN SerialFifoEmpty(IN SERIAL_DEV_FIFO *Fifo)
EFI_STATUS EFIAPI SerialSetAttributes(IN EFI_SERIAL_IO_PROTOCOL *This, IN UINT64 BaudRate, IN UINT32 ReceiveFifoDepth, IN UINT32 Timeout, IN EFI_PARITY_TYPE Parity, IN UINT8 DataBits, IN EFI_STOP_BITS_TYPE StopBits)
EFI_STATUS EFIAPI SerialSetControl(IN EFI_SERIAL_IO_PROTOCOL *This, IN UINT32 Control)
EFI_STATUS EFIAPI SerialReset(IN EFI_SERIAL_IO_PROTOCOL *This)
BOOLEAN SerialPresent(IN SERIAL_DEV *SerialDevice)
BOOLEAN VerifyUartParameters(IN UINT32 ClockRate, IN UINT64 BaudRate, IN UINT8 DataBits, IN EFI_PARITY_TYPE Parity, IN EFI_STOP_BITS_TYPE StopBits, OUT UINT64 *Divisor, OUT UINT64 *ActualBaudRate)
BOOLEAN IsUartFlowControlDevicePathNode(IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl)
EFI_STATUS EFIAPI SerialControllerDriverStart(IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_HANDLE Controller, IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath)
VOID AddName(IN SERIAL_DEV *SerialDevice, IN UINT32 Uid)
#define SERIAL_MAX_FIFO_SIZE
Actual FIFO size is 16. FIFO based on circular wastes one unit.
EFI_STATUS EFIAPI SerialWrite(IN EFI_SERIAL_IO_PROTOCOL *This, IN OUT UINTN *BufferSize, IN VOID *Buffer)
EFI_STATUS SerialFifoAdd(IN SERIAL_DEV_FIFO *Fifo, IN UINT8 Data)
EFI_STATUS SerialFifoRemove(IN SERIAL_DEV_FIFO *Fifo, OUT UINT8 *Data)
EFI_STATUS EFIAPI SerialGetControl(IN EFI_SERIAL_IO_PROTOCOL *This, OUT UINT32 *Control)
EFI_STATUS EFIAPI SerialControllerDriverStop(IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_HANDLE Controller, IN UINTN NumberOfChildren, IN EFI_HANDLE *ChildHandleBuffer)
EFI_STATUS EFIAPI SerialControllerDriverSupported(IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_HANDLE Controller, IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath)
VOID SerialWriteRegister(IN SERIAL_DEV *SerialDev, IN UINT32 Offset, IN UINT8 Data)
EFI_STATUS EFIAPI SerialRead(IN EFI_SERIAL_IO_PROTOCOL *This, IN OUT UINTN *BufferSize, OUT VOID *Buffer)
EFI_STATUS EFIAPI SerialComponentNameGetControllerName(IN EFI_COMPONENT_NAME_PROTOCOL *This, IN EFI_HANDLE ControllerHandle, IN EFI_HANDLE ChildHandle OPTIONAL, IN CHAR8 *Language, OUT CHAR16 **ControllerName)
EFI_STATUS SerialReceiveTransmit(IN SERIAL_DEV *SerialDevice)
EFI_STATUS EFIAPI SerialComponentNameGetDriverName(IN EFI_COMPONENT_NAME_PROTOCOL *This, IN CHAR8 *Language, OUT CHAR16 **DriverName)
UART_DEVICE_PATH * SkipControllerDevicePathNode(EFI_DEVICE_PATH_PROTOCOL *DevicePath, BOOLEAN *ContainsControllerNode, UINT32 *ControllerNumber)
UINT8 SerialReadRegister(IN SERIAL_DEV *SerialDev, IN UINT32 Offset)
UINT64 EFI_PHYSICAL_ADDRESS
UINT16 VendorId
Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
UINT16 ReceiveFifoDepth
UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT8 RegisterStride
UART register stride in bytes. Set to 0 for default register stride of 1 byte.
UINT16 DeviceId
Device ID to match the PCI device.
UINT16 TransmitFifoDepth
UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT8 BarIndex
Which BAR to get the UART base address.
UINT64 Offset
The byte offset into to the BAR.
UINT32 ClockRate
UART clock rate. Set to 0 for default clock rate of 1843200 Hz.
UINT16 Tail
Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).
UINT16 Head
Head pointer of the FIFO. Empty when (Head == Tail).
UINT16 ReceiveFifoDepth
UART receive FIFO depth in bytes.
BOOLEAN MmioAccess
TRUE for MMIO, FALSE for IO.
UINT16 TransmitFifoDepth
UART transmit FIFO depth in bytes.
BOOLEAN ContainsControllerNode
TRUE if the device produced contains Controller node.
SERIAL_DEV_FIFO Receive
The FIFO used to store received data.
SERIAL_DEV_FIFO Transmit
The FIFO used to store to-transmit data.
UINT8 RegisterStride
UART Register Stride.
EFI_PHYSICAL_ADDRESS BaseAddress
UART base address.
UINT32 ClockRate
UART clock rate.
UINT8 ResetRF
Reset Reciever FIFO.
UINT8 ResetTF
Reset Transmistter FIFO.
UINT8 Dms
DMA Mode Select.
UINT8 Rtb
Receive Trigger Bits.
UINT8 TrFIFOE
Transmit and Receive FIFO Enable.
UINT8 TrFIFO64
Enable 64 byte FIFO.
UINT8 Theie
Transmistter Holding Register Empty Interrupt Enable.
UINT8 Rie
Receiver Interrupt Enable.
UINT8 Mie
Modem Interrupt Enable.
UINT8 Ravie
Receiver Data Available Interrupt Enable.
UINT8 BrCon
Break Control.
UINT8 SerialDB
Number of Serial Data Bits.
UINT8 DLab
Divisor Latch Access Bit.
UINT8 StopB
Number of Stop Bits.
UINT8 EvenPar
Even Parity Select.
UINT8 SticPar
Sticky Parity.
UINT8 ParEn
Parity Enable.
UINT8 Dr
Receiver Data Ready Status.
UINT8 Oe
Overrun Error Status.
UINT8 Temt
Transmitter Empty Status.
UINT8 FIFOe
FIFO Error Status.
UINT8 Bi
Break Interrupt Status.
UINT8 Pe
Parity Error Status.
UINT8 Thre
Transmistter Holding Register Status.
UINT8 Fe
Framing Error Status.
UINT8 DtrC
Data Terminal Ready Control.
UINT8 Rts
Request To Send Control.
UINT8 Out2
Output2, used to disable interrupt.
UINT8 Lme
Loopback Mode Enable.
UINT8 Dcd
Data Carrier Detect Status.
UINT8 Dsr
Data Set Ready Status.
UINT8 DeltaCTS
Delta Clear To Send Status.
UINT8 TrailingEdgeRI
Trailing Edge of Ring Indicator Status.
UINT8 DeltaDCD
Delta Data Carrier Detect Status.
UINT8 Ri
Ring Indicator Status.
UINT8 DeltaDSR
Delta Data Set Ready Status.
UINT8 Cts
Clear To Send Status.