TianoCore EDK2 master
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PchSpi.c
Go to the documentation of this file.
1
7#include "SpiCommon.h"
8
17UINT32
19 IN UINTN PchSpiBase
20 )
21{
22 return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);
23}
24
31VOID
33 IN UINTN PchSpiBase
34 )
35{
36}
37
44VOID
46 IN BOOLEAN EnableSmmSts
47 )
48{
49 UINT32 Data32;
50
51 if (EnableSmmSts) {
52 //
53 // Disable BIOS Write Protect in SMM phase.
54 //
55 Data32 = MmioRead32 ((UINTN)(0xFED30880)) | (UINT32)(BIT0);
56 AsmWriteMsr32 (0x000001FE, Data32);
57 } else {
58 //
59 // Enable BIOS Write Protect in SMM phase
60 //
61 Data32 = MmioRead32 ((UINTN)(0xFED30880)) & (UINT32)(~BIT0);
62 AsmWriteMsr32 (0x000001FE, Data32);
63 }
64
65 //
66 // Read FED30880h back to ensure the setting went through.
67 //
68 Data32 = MmioRead32 (0xFED30880);
69}
70
82EFIAPI
84 IN UINTN PchSpiBase,
85 IN UINT8 CpuSmmBwp
86 )
87{
88 //
89 // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
90 //
91 MmioOr8 (PchSpiBase + R_SPI_BCR + 1, (B_SPI_BCR_SYNC_SS >> 8));
92
93 //
94 // Enable the access to the BIOS space for both read and write cycles
95 //
96 MmioOr8 (PchSpiBase + R_SPI_BCR, B_SPI_BCR_BIOSWE);
97
98 if (CpuSmmBwp != 0) {
100 }
101
102 return EFI_SUCCESS;
103}
104
112VOID
113EFIAPI
115 IN UINTN PchSpiBase,
116 IN UINT8 CpuSmmBwp
117 )
118{
119 //
120 // Disable the access to the BIOS space for write cycles
121 //
122 MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8)(~B_SPI_BCR_BIOSWE));
123
124 if (CpuSmmBwp != 0) {
126 }
127}
128
138UINT8
140 IN UINTN PchSpiBase
141 )
142{
143 UINT8 BiosCtlSave;
144
145 BiosCtlSave = MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;
146
148 PchSpiBase + R_SPI_BCR, \
149 (UINT32)(~B_SPI_BCR_SRC), \
151 );
152
153 return BiosCtlSave;
154}
155
163VOID
165 IN UINTN PchSpiBase,
166 IN UINT8 BiosCtlValue
167 )
168{
169 MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlValue);
170}
UINT64 UINTN
UINT8 EFIAPI MmioAnd8(IN UINTN Address, IN UINT8 AndData)
Definition: IoHighLevel.c:1231
UINT8 EFIAPI MmioAndThenOr8(IN UINTN Address, IN UINT8 AndData, IN UINT8 OrData)
Definition: IoHighLevel.c:1262
UINT8 EFIAPI MmioRead8(IN UINTN Address)
Definition: IoLib.c:82
UINT8 EFIAPI MmioOr8(IN UINTN Address, IN UINT8 OrData)
Definition: IoHighLevel.c:1203
UINT32 EFIAPI MmioRead32(IN UINTN Address)
Definition: IoLib.c:262
UINT32 EFIAPI MmioAndThenOr32(IN UINTN Address, IN UINT32 AndData, IN UINT32 OrData)
Definition: IoHighLevel.c:1845
#define TRUE
Definition: Base.h:301
#define FALSE
Definition: Base.h:307
#define IN
Definition: Base.h:279
UINT8 SaveAndDisableSpiPrefetchCache(IN UINTN PchSpiBase)
Definition: PchSpi.c:139
VOID EFIAPI EnableBiosWriteProtect(IN UINTN PchSpiBase, IN UINT8 CpuSmmBwp)
Definition: PchSpi.c:114
EFI_STATUS EFIAPI DisableBiosWriteProtect(IN UINTN PchSpiBase, IN UINT8 CpuSmmBwp)
Definition: PchSpi.c:83
VOID SetSpiBiosControlRegister(IN UINTN PchSpiBase, IN UINT8 BiosCtlValue)
Definition: PchSpi.c:164
VOID CpuSmmDisableBiosWriteProtect(IN BOOLEAN EnableSmmSts)
Definition: PchSpi.c:45
UINT32 AcquireSpiBar0(IN UINTN PchSpiBase)
Definition: PchSpi.c:18
VOID ReleaseSpiBar0(IN UINTN PchSpiBase)
Definition: PchSpi.c:32
#define R_SPI_BCR
BIOS Control Register.
Definition: RegsSpi.h:14
#define B_SPI_BCR_SRC
SPI Read Configuration (SRC)
Definition: RegsSpi.h:15
#define R_SPI_BASE
32-bit Memory Base Address Register
Definition: RegsSpi.h:12
#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS
Prefetch Disable, Cache Disable.
Definition: RegsSpi.h:16
#define B_SPI_BCR_BIOSWE
Write Protect Disable (WPD)
Definition: RegsSpi.h:18
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
#define EFI_SUCCESS
Definition: UefiBaseType.h:112
UINT32 EFIAPI AsmWriteMsr32(IN UINT32 Index, IN UINT32 Value)
Definition: X86Msr.c:53