TianoCore EDK2 master
UefiPxe.h
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1
15#ifndef __EFI_PXE_H__
16#define __EFI_PXE_H__
17
18#pragma pack(1)
19
20#define PXE_BUSTYPE(a, b, c, d) \
21 ( \
22 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \
23 ((PXE_UINT32) (a) & 0xFF) \
24 )
25
29#define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
30
34#define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
35#define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
36#define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
37#define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
38
39#define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))
40
41#define PXE_SWAP_UINT32(n) \
42 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
43 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \
44 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \
45 (((PXE_UINT32)(n) & 0xFF000000) >> 24))
46
47#define PXE_SWAP_UINT64(n) \
48 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \
49 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \
50 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \
51 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \
52 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \
53 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \
54 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \
55 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))
56
57#define PXE_CPBSIZE_NOT_USED 0
58#define PXE_DBSIZE_NOT_USED 0
59#define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0
60#define PXE_DBADDR_NOT_USED (PXE_UINT64) 0
61#define PXE_CONST CONST
62
63#define PXE_VOLATILE volatile
64
65typedef VOID PXE_VOID;
66typedef UINT8 PXE_UINT8;
67typedef UINT16 PXE_UINT16;
68typedef UINT32 PXE_UINT32;
69typedef UINTN PXE_UINTN;
70
74typedef UINT64 PXE_UINT64;
75
76typedef PXE_UINT8 PXE_BOOL;
77#define PXE_FALSE 0
78#define PXE_TRUE (!PXE_FALSE)
79
80typedef PXE_UINT16 PXE_OPCODE;
81
85#define PXE_OPCODE_GET_STATE 0x0000
86
90#define PXE_OPCODE_START 0x0001
91
95#define PXE_OPCODE_STOP 0x0002
96
100#define PXE_OPCODE_GET_INIT_INFO 0x0003
101
105#define PXE_OPCODE_GET_CONFIG_INFO 0x0004
106
110#define PXE_OPCODE_INITIALIZE 0x0005
111
115#define PXE_OPCODE_RESET 0x0006
116
120#define PXE_OPCODE_SHUTDOWN 0x0007
121
125#define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
126
130#define PXE_OPCODE_RECEIVE_FILTERS 0x0009
131
135#define PXE_OPCODE_STATION_ADDRESS 0x000A
136
140#define PXE_OPCODE_STATISTICS 0x000B
141
145#define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
146
150#define PXE_OPCODE_NVDATA 0x000D
151
155#define PXE_OPCODE_GET_STATUS 0x000E
156
160#define PXE_OPCODE_FILL_HEADER 0x000F
161
165#define PXE_OPCODE_TRANSMIT 0x0010
166
170#define PXE_OPCODE_RECEIVE 0x0011
171
175#define PXE_OPCODE_LAST_VALID 0x0011
176
177typedef PXE_UINT16 PXE_OPFLAGS;
178
179#define PXE_OPFLAGS_NOT_USED 0x0000
180
181//
182// //////////////////////////////////////
183// UNDI Get State
184//
185// No OpFlags
186
188// UNDI Start
189//
190// No OpFlags
191
193// UNDI Stop
194//
195// No OpFlags
196
198// UNDI Get Init Info
199//
200// No Opflags
201
203// UNDI Get Config Info
204//
205// No Opflags
206
210#define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
211#define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
212#define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
213
218#define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
219#define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
220
225
233#define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
234#define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
235#define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
236#define PXE_OPFLAGS_INTERRUPT_READ 0x0000
237
242#define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
243
248#define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
249
254#define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
255
260#define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
261
269#define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
270#define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
271#define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
272#define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
273
278#define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
279
284#define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
285
290#define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
291
297#define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
298
302#define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
303
308#define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
309
313#define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
314#define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
315#define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
316
320#define PXE_OPFLAGS_STATISTICS_READ 0x0000
321#define PXE_OPFLAGS_STATISTICS_RESET 0x0001
322
329#define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
330#define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
331#define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
332
339#define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
340#define PXE_OPFLAGS_NVDATA_READ 0x0000
341#define PXE_OPFLAGS_NVDATA_WRITE 0x0001
342
352#define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
353
362#define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
363
367#define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004
368
372#define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
373#define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
374#define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
375
384#define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
385#define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
386#define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
387
388#define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
389#define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
390#define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
391
397
401typedef PXE_UINT16 PXE_STATFLAGS;
402
403#define PXE_STATFLAGS_INITIALIZE 0x0000
404
413#define PXE_STATFLAGS_STATUS_MASK 0xC000
414#define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
415#define PXE_STATFLAGS_COMMAND_FAILED 0x8000
416#define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
417
421#define PXE_STATFLAGS_GET_STATE_MASK 0x0003
422#define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
423#define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
424#define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
425
431
435#define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
436#define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
437#define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
438
439#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK 0x0002
440#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED 0x0000
441#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED 0x0002
442
446#define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
447
451#define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
452
457
464#define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
465
469#define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
470
474#define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
475
479
483#define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
484
488#define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
489
494#define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
495
499#define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
500
504#define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
505
511
517
522
528
532
536#define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
537#define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
538
542#define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
543
547#define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
548
552#define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
553
557#define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
558
563#define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
564
569#define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
570
574#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA 0x0040
575
581
586
590
594typedef PXE_UINT16 PXE_STATCODE;
595
596#define PXE_STATCODE_INITIALIZE 0x0000
597
602#define PXE_STATCODE_SUCCESS 0x0000
603
604#define PXE_STATCODE_INVALID_CDB 0x0001
605#define PXE_STATCODE_INVALID_CPB 0x0002
606#define PXE_STATCODE_BUSY 0x0003
607#define PXE_STATCODE_QUEUE_FULL 0x0004
608#define PXE_STATCODE_ALREADY_STARTED 0x0005
609#define PXE_STATCODE_NOT_STARTED 0x0006
610#define PXE_STATCODE_NOT_SHUTDOWN 0x0007
611#define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
612#define PXE_STATCODE_NOT_INITIALIZED 0x0009
613#define PXE_STATCODE_DEVICE_FAILURE 0x000A
614#define PXE_STATCODE_NVDATA_FAILURE 0x000B
615#define PXE_STATCODE_UNSUPPORTED 0x000C
616#define PXE_STATCODE_BUFFER_FULL 0x000D
617#define PXE_STATCODE_INVALID_PARAMETER 0x000E
618#define PXE_STATCODE_INVALID_UNDI 0x000F
619#define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
620#define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
621#define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
622#define PXE_STATCODE_NO_DATA 0x0013
623
624typedef PXE_UINT16 PXE_IFNUM;
625
629#define PXE_IFNUM_START 0x0000
630
635#define PXE_IFNUM_INVALID 0x0000
636
637typedef PXE_UINT16 PXE_CONTROL;
638
646#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
647
655#define PXE_CONTROL_LINK 0x0001
656#define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
657
658typedef PXE_UINT8 PXE_FRAME_TYPE;
659
660#define PXE_FRAME_TYPE_NONE 0x00
661#define PXE_FRAME_TYPE_UNICAST 0x01
662#define PXE_FRAME_TYPE_BROADCAST 0x02
663#define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03
664#define PXE_FRAME_TYPE_PROMISCUOUS 0x04
665#define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05
666
667#define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST
668
669typedef PXE_UINT32 PXE_IPV4;
670
671typedef PXE_UINT32 PXE_IPV6[4];
672#define PXE_MAC_LENGTH 32
673
674typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
675
676typedef PXE_UINT8 PXE_IFTYPE;
677typedef UINT16 PXE_MEDIA_PROTOCOL;
678
706#define PXE_IFTYPE_ETHERNET 0x01
707#define PXE_IFTYPE_TOKENRING 0x04
708#define PXE_IFTYPE_FIBRE_CHANNEL 0x12
709
710typedef struct s_pxe_hw_undi {
711 PXE_UINT32 Signature;
712 PXE_UINT8 Len;
713 PXE_UINT8 Fudge;
714 PXE_UINT8 Rev;
715 PXE_UINT8 IFcnt;
716 PXE_UINT8 MajorVer;
717 PXE_UINT8 MinorVer;
718 PXE_UINT8 IFcntExt;
719 PXE_UINT8 reserved;
720 PXE_UINT32 Implementation;
727
731
735#define PXE_HWSTAT_STATE_MASK 0xC0000000
736#define PXE_HWSTAT_BUSY 0xC0000000
737#define PXE_HWSTAT_INITIALIZED 0x80000000
738#define PXE_HWSTAT_STARTED 0x40000000
739#define PXE_HWSTAT_STOPPED 0x00000000
740
744#define PXE_HWSTAT_COMMAND_FAILED 0x20000000
745
749#define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
750#define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
751#define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
752#define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
753#define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
754
758#define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
759#define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
760#define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
761#define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
762
766#define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
767#define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
768#define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
769#define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
770
774
779#define PXE_HWCMD_ISSUE_COMMAND 0x80000000
780#define PXE_HWCMD_INTS_AND_FILTS 0x00000000
781
785#define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
786#define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
787#define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
788#define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
789#define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
790
794#define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
795#define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
796#define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
797#define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
798
802#define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
803#define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
804#define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
805#define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
806
807typedef struct s_pxe_sw_undi {
808 PXE_UINT32 Signature;
809 PXE_UINT8 Len;
810 PXE_UINT8 Fudge;
811 PXE_UINT8 Rev;
812 PXE_UINT8 IFcnt;
813 PXE_UINT8 MajorVer;
814 PXE_UINT8 MinorVer;
815 PXE_UINT8 IFcntExt;
816 PXE_UINT8 reserved1;
817 PXE_UINT32 Implementation;
819 PXE_UINT8 reserved2[3];
820 PXE_UINT8 BusCnt;
821 PXE_UINT32 BusType[1];
823
824typedef union u_pxe_undi {
825 PXE_HW_UNDI hw;
826 PXE_SW_UNDI sw;
827} PXE_UNDI;
828
832#define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
833
837#define PXE_ROMID_REV 0x02
838
844#define PXE_ROMID_MAJORVER 0x03
845#define PXE_ROMID_MINORVER 0x01
846
850#define PXE_ROMID_IMP_HW_UNDI 0x80000000
851#define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
852#define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
853#define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
854#define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
855#define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
856#define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
857#define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
858#define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
859#define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
860#define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
861#define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
862#define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
863#define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
864#define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
865#define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
866#define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
867#define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
868#define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
869#define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
870#define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
871#define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
872
873typedef struct s_pxe_cdb {
874 PXE_OPCODE OpCode;
875 PXE_OPFLAGS OpFlags;
876 PXE_UINT16 CPBsize;
877 PXE_UINT16 DBsize;
878 PXE_UINT64 CPBaddr;
879 PXE_UINT64 DBaddr;
880 PXE_STATCODE StatCode;
881 PXE_STATFLAGS StatFlags;
882 PXE_UINT16 IFnum;
883 PXE_CONTROL Control;
884} PXE_CDB;
885
886typedef union u_pxe_ip_addr {
887 PXE_IPV6 IPv6;
888 PXE_IPV4 IPv4;
890
891typedef union pxe_device {
898 struct {
903 PXE_UINT32 BusType;
904
908 PXE_UINT16 Bus;
909 PXE_UINT8 Device;
910 PXE_UINT8 Function;
911 } PCI, PCC;
912} PXE_DEVICE;
913
917#define MAX_PCI_CONFIG_LEN 64
918#define MAX_EEPROM_LEN 128
919#define MAX_XMIT_BUFFERS 32
920#define MAX_MCAST_ADDRESS_CNT 8
921
922typedef struct s_pxe_cpb_start_30 {
933 UINT64 Delay;
934
949 UINT64 Block;
950
963 UINT64 Virt2Phys;
974 UINT64 Mem_IO;
976
977typedef struct s_pxe_cpb_start_31 {
988 UINT64 Delay;
989
1004 UINT64 Block;
1005
1029 UINT64 Mem_IO;
1046 UINT64 Map_Mem;
1047
1058
1069 UINT64 Sync_Mem;
1070
1079
1080#define TO_AND_FROM_DEVICE 0
1081#define FROM_DEVICE 1
1082#define TO_DEVICE 2
1083
1084#define PXE_DELAY_MILLISECOND 1000
1085#define PXE_DELAY_SECOND 1000000
1086#define PXE_IO_READ 0
1087#define PXE_IO_WRITE 1
1088#define PXE_MEM_READ 2
1089#define PXE_MEM_WRITE 4
1090
1100 PXE_UINT32 MemoryRequired;
1101
1105 PXE_UINT32 FrameDataLen;
1106
1112 PXE_UINT32 LinkSpeeds[4];
1113
1117 PXE_UINT32 NvCount;
1118
1122 PXE_UINT16 NvWidth;
1123
1129 PXE_UINT16 MediaHeaderLen;
1130
1134 PXE_UINT16 HWaddrLen;
1135
1140 PXE_UINT16 MCastFilterCnt;
1141
1149 PXE_UINT16 TxBufCnt;
1150 PXE_UINT16 TxBufSize;
1151 PXE_UINT16 RxBufCnt;
1152 PXE_UINT16 RxBufSize;
1153
1159 PXE_UINT8 IFtype;
1160
1165
1171
1172#define PXE_MAX_TXRX_UNIT_ETHER 1500
1173
1174#define PXE_HWADDR_LEN_ETHER 0x0006
1175#define PXE_MAC_HEADER_LEN_ETHER 0x000E
1176
1177#define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
1178#define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
1179
1180#define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
1181#define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
1182
1188 UINT32 BusType;
1189
1194 UINT16 Bus;
1195 UINT8 Device;
1196 UINT8 Function;
1197
1202 union {
1203 UINT8 Byte[256];
1204 UINT16 Word[128];
1205 UINT32 Dword[64];
1208
1214 PXE_UINT32 BusType;
1215
1220 PXE_UINT16 Bus;
1221 PXE_UINT8 Device;
1222 PXE_UINT8 Function;
1223
1228 union {
1229 PXE_UINT8 Byte[256];
1230 PXE_UINT16 Word[128];
1231 PXE_UINT32 Dword[64];
1234
1239
1240typedef struct s_pxe_cpb_initialize {
1247
1252 PXE_UINT32 MemoryLength;
1253
1259 PXE_UINT32 LinkSpeed;
1260
1271 PXE_UINT16 TxBufCnt;
1272 PXE_UINT16 TxBufSize;
1273 PXE_UINT16 RxBufCnt;
1274 PXE_UINT16 RxBufSize;
1275
1280 PXE_UINT8 DuplexMode;
1281
1282 PXE_UINT8 LoopBackMode;
1284
1285#define PXE_DUPLEX_DEFAULT 0x00
1286#define PXE_FORCE_FULL_DUPLEX 0x01
1287#define PXE_ENABLE_FULL_DUPLEX 0x02
1288#define PXE_FORCE_HALF_DUPLEX 0x04
1289#define PXE_DISABLE_FULL_DUPLEX 0x08
1290
1291#define LOOPBACK_NORMAL 0
1292#define LOOPBACK_INTERNAL 1
1293#define LOOPBACK_EXTERNAL 2
1294
1295typedef struct s_pxe_db_initialize {
1304 PXE_UINT32 MemoryUsed;
1305
1310 PXE_UINT16 TxBufCnt;
1311 PXE_UINT16 TxBufSize;
1312 PXE_UINT16 RxBufCnt;
1313 PXE_UINT16 RxBufSize;
1315
1321 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1323
1328 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1330
1336 PXE_MAC_ADDR StationAddr;
1338
1343 PXE_MAC_ADDR StationAddr;
1344
1348 PXE_MAC_ADDR BroadcastAddr;
1349
1353 PXE_MAC_ADDR PermanentAddr;
1355
1356typedef struct s_pxe_db_statistics {
1367
1373
1378#define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
1379
1383#define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
1384
1389#define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
1390
1395#define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
1396
1400#define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
1401
1405#define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
1406
1410#define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
1411
1415#define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
1416
1420#define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
1421
1426#define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
1427
1431#define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
1432#define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
1433#define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
1434#define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
1435#define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
1436#define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
1437#define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
1438#define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
1439#define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
1440#define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
1441
1445#define PXE_STATISTICS_COLLISIONS 0x14
1446
1450#define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
1451
1455#define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16
1456
1460#define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17
1461
1465#define PXE_STATISTICS_TX_ERROR_FRAMES 0x18
1466
1470#define PXE_STATISTICS_TX_RETRY_FRAMES 0x19
1471
1478
1483 PXE_MAC_ADDR MAC;
1485
1490 struct {
1494 PXE_UINT32 Addr;
1495
1499 union {
1500 PXE_UINT8 Byte;
1501 PXE_UINT16 Word;
1502 PXE_UINT32 Dword;
1506
1515 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1516
1520 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1521
1527
1528typedef struct s_pxe_db_nvdata {
1532 union {
1536 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1537
1541 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1542
1549
1550typedef struct s_pxe_db_get_status {
1555 PXE_UINT32 RxFrameLen;
1556
1560 PXE_UINT32 reserved;
1561
1567
1573 PXE_MAC_ADDR SrcAddr;
1574 PXE_MAC_ADDR DestAddr;
1575
1581
1585 PXE_UINT32 PacketLen;
1586
1592 PXE_UINT16 Protocol;
1593
1597 PXE_UINT16 MediaHeaderLen;
1599
1600#define PXE_PROTOCOL_ETHERNET_IP 0x0800
1601#define PXE_PROTOCOL_ETHERNET_ARP 0x0806
1602#define MAX_XMIT_FRAGMENTS 16
1603
1609 PXE_MAC_ADDR SrcAddr;
1610 PXE_MAC_ADDR DestAddr;
1611
1615 PXE_UINT32 PacketLen;
1616
1622 PXE_MEDIA_PROTOCOL Protocol;
1623
1627 PXE_UINT16 MediaHeaderLen;
1628
1632 PXE_UINT16 FragCnt;
1633
1637 PXE_UINT16 reserved;
1638
1643 struct {
1648
1652 PXE_UINT32 FragLen;
1653
1657 PXE_UINT32 reserved;
1658 } FragDesc[MAX_XMIT_FRAGMENTS];
1660
1661typedef struct s_pxe_cpb_transmit {
1667
1672 PXE_UINT32 DataLen;
1673
1677 PXE_UINT16 MediaheaderLen;
1678
1682 PXE_UINT16 reserved;
1684
1689 PXE_UINT32 FrameLen;
1690
1694 PXE_UINT16 MediaheaderLen;
1695
1699 PXE_UINT16 FragCnt;
1700
1705 struct {
1710
1714 PXE_UINT32 FragLen;
1715
1719 PXE_UINT32 reserved;
1720 } FragDesc[MAX_XMIT_FRAGMENTS];
1722
1723typedef struct s_pxe_cpb_receive {
1729
1735 PXE_UINT32 BufferLen;
1736
1740 PXE_UINT32 reserved;
1742
1743typedef struct s_pxe_db_receive {
1747 PXE_MAC_ADDR SrcAddr;
1748 PXE_MAC_ADDR DestAddr;
1749
1755 PXE_UINT32 FrameLen;
1756
1760 PXE_MEDIA_PROTOCOL Protocol;
1761
1765 PXE_UINT16 MediaHeaderLen;
1766
1770 PXE_FRAME_TYPE Type;
1771
1775 PXE_UINT8 reserved[7];
1777
1778#pragma pack()
1779
1780#endif
UINT64 UINTN
PXE_UINT16 PXE_STATFLAGS
Definition: UefiPxe.h:401
UINT64 PXE_UINT64
Definition: UefiPxe.h:74
#define MAX_XMIT_BUFFERS
recycling Q length for xmit_done.
Definition: UefiPxe.h:919
#define MAX_EEPROM_LEN
Definition: UefiPxe.h:918
PXE_UINT16 PXE_STATCODE
Definition: UefiPxe.h:594
union u_pxe_cpb_nvdata_bulk PXE_CPB_NVDATA_BULK
PXE_MEDIA_PROTOCOL Protocol
Definition: UefiPxe.h:1622
struct s_pxe_cpb_fill_header_fragmented::@971 FragDesc[MAX_XMIT_FRAGMENTS]
PXE_UINT64 MediaHeader
Definition: UefiPxe.h:1580
PXE_UINT16 Protocol
Definition: UefiPxe.h:1592
PXE_UINT32 PacketLen
Definition: UefiPxe.h:1585
PXE_MAC_ADDR SrcAddr
Definition: UefiPxe.h:1573
PXE_UINT16 MediaHeaderLen
Definition: UefiPxe.h:1597
PXE_UINT32 MemoryLength
Definition: UefiPxe.h:1252
PXE_UINT64 MemoryAddr
Definition: UefiPxe.h:1246
PXE_UINT16 TxBufCnt
Definition: UefiPxe.h:1271
PXE_UINT8 DuplexMode
Definition: UefiPxe.h:1280
PXE_UINT32 LinkSpeed
Definition: UefiPxe.h:1259
union s_pxe_cpb_nvdata_sparse::@968::@969 Data
struct s_pxe_cpb_nvdata_sparse::@968 Item[MAX_EEPROM_LEN]
PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT]
Definition: UefiPxe.h:1321
PXE_UINT32 reserved
Definition: UefiPxe.h:1740
PXE_UINT32 BufferLen
Definition: UefiPxe.h:1735
PXE_UINT64 BufferAddr
Definition: UefiPxe.h:1728
UINT64 Virt2Phys
Definition: UefiPxe.h:963
PXE_MAC_ADDR StationAddr
Definition: UefiPxe.h:1336
struct s_pxe_cpb_transmit_fragments::@972 FragDesc[MAX_XMIT_FRAGMENTS]
PXE_UINT16 MediaheaderLen
Definition: UefiPxe.h:1677
PXE_UINT32 DataLen
Definition: UefiPxe.h:1672
PXE_UINT64 FrameAddr
Definition: UefiPxe.h:1666
PXE_UINT16 reserved
Definition: UefiPxe.h:1682
PXE_UINT16 NvWidth
Definition: UefiPxe.h:1122
PXE_UINT8 SupportedLoopBackModes
Definition: UefiPxe.h:1169
PXE_UINT32 MemoryRequired
Definition: UefiPxe.h:1100
PXE_UINT32 FrameDataLen
Definition: UefiPxe.h:1105
PXE_UINT32 NvCount
Definition: UefiPxe.h:1117
PXE_UINT16 HWaddrLen
Definition: UefiPxe.h:1134
PXE_UINT16 TxBufCnt
Definition: UefiPxe.h:1149
PXE_UINT16 MCastFilterCnt
Definition: UefiPxe.h:1140
PXE_UINT8 SupportedDuplexModes
Definition: UefiPxe.h:1164
PXE_UINT32 LinkSpeeds[4]
Definition: UefiPxe.h:1112
PXE_UINT16 MediaHeaderLen
Definition: UefiPxe.h:1129
PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS]
Definition: UefiPxe.h:1565
PXE_UINT32 RxFrameLen
Definition: UefiPxe.h:1555
PXE_UINT32 reserved
Definition: UefiPxe.h:1560
PXE_UINT16 TxBufCnt
Definition: UefiPxe.h:1310
PXE_UINT32 MemoryUsed
Definition: UefiPxe.h:1304
PXE_UINT32 Dword[MAX_EEPROM_LEN]
Definition: UefiPxe.h:1546
union s_pxe_db_nvdata::@970 Data
PXE_UINT16 Word[MAX_EEPROM_LEN<< 1]
Definition: UefiPxe.h:1541
PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT]
Definition: UefiPxe.h:1328
PXE_MAC_ADDR SrcAddr
Definition: UefiPxe.h:1747
PXE_UINT32 FrameLen
Definition: UefiPxe.h:1755
PXE_UINT8 reserved[7]
Definition: UefiPxe.h:1775
PXE_FRAME_TYPE Type
Definition: UefiPxe.h:1770
PXE_UINT16 MediaHeaderLen
Definition: UefiPxe.h:1765
PXE_MEDIA_PROTOCOL Protocol
Definition: UefiPxe.h:1760
PXE_UINT64 Supported
Definition: UefiPxe.h:1366
PXE_UINT64 Data[64]
Definition: UefiPxe.h:1371
PXE_MAC_ADDR PermanentAddr
Definition: UefiPxe.h:1353
PXE_MAC_ADDR StationAddr
Definition: UefiPxe.h:1343
PXE_MAC_ADDR BroadcastAddr
Definition: UefiPxe.h:1348
PXE_UINT32 Implementation
Definition: UefiPxe.h:720
PXE_UINT8 Len
sizeof(PXE_HW_UNDI).
Definition: UefiPxe.h:712
PXE_UINT8 reserved
zero, not used.
Definition: UefiPxe.h:719
PXE_UINT32 Signature
PXE_ROMID_SIGNATURE.
Definition: UefiPxe.h:711
PXE_UINT8 Rev
PXE_ROMID_REV.
Definition: UefiPxe.h:714
PXE_UINT8 Fudge
makes 8-bit cksum equal zero.
Definition: UefiPxe.h:713
PXE_UINT8 MinorVer
PXE_ROMID_MINORVER.
Definition: UefiPxe.h:717
PXE_UINT8 IFcnt
physical connector count lower byte.
Definition: UefiPxe.h:715
PXE_UINT8 MajorVer
PXE_ROMID_MAJORVER.
Definition: UefiPxe.h:716
PXE_UINT8 IFcntExt
physical connector count upper byte.
Definition: UefiPxe.h:718
union s_pxe_pcc_config_info::@967 Config
PXE_UINT32 BusType
Definition: UefiPxe.h:1214
union s_pxe_pci_config_info::@966 Config
PXE_UINT32 Implementation
Implementation flags.
Definition: UefiPxe.h:817
PXE_UINT8 reserved1
zero, not used.
Definition: UefiPxe.h:816
PXE_UINT8 Rev
PXE_ROMID_REV.
Definition: UefiPxe.h:811
PXE_UINT64 EntryPoint
API entry point.
Definition: UefiPxe.h:818
PXE_UINT8 MajorVer
PXE_ROMID_MAJORVER.
Definition: UefiPxe.h:813
PXE_UINT8 MinorVer
PXE_ROMID_MINORVER.
Definition: UefiPxe.h:814
PXE_UINT32 Signature
PXE_ROMID_SIGNATURE.
Definition: UefiPxe.h:808
PXE_UINT8 IFcnt
physical connector count lower byte.
Definition: UefiPxe.h:812
PXE_UINT8 reserved2[3]
zero, not used.
Definition: UefiPxe.h:819
PXE_UINT8 IFcntExt
physical connector count upper byte.
Definition: UefiPxe.h:815
PXE_UINT8 Len
sizeof(PXE_SW_UNDI).
Definition: UefiPxe.h:809
PXE_UINT32 BusType[1]
list of supported bustypes.
Definition: UefiPxe.h:821
PXE_UINT8 BusCnt
number of bustypes supported.
Definition: UefiPxe.h:820
PXE_UINT8 Fudge
makes 8-bit cksum zero.
Definition: UefiPxe.h:810
PXE_UINT32 BusType
Definition: UefiPxe.h:903
PXE_UINT16 Bus
Definition: UefiPxe.h:908
struct pxe_device::@965 PCI
PXE_UINT32 Dword[MAX_EEPROM_LEN]
Definition: UefiPxe.h:1525
PXE_UINT16 Word[MAX_EEPROM_LEN<< 1]
Definition: UefiPxe.h:1520