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X86Cache.c
Go to the documentation of this file.
1
10#include <Base.h>
11#include <Library/BaseLib.h>
12#include <Library/DebugLib.h>
13
19VOID
20EFIAPI
22 VOID
23 )
24{
25}
26
52VOID *
53EFIAPI
55 IN VOID *Address,
56 IN UINTN Length
57 )
58{
59 if (Length == 0) {
60 return Address;
61 }
62
63 ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
64 return Address;
65}
66
77VOID
78EFIAPI
80 VOID
81 )
82{
83 AsmWbinvd ();
84}
85
112VOID *
113EFIAPI
115 IN VOID *Address,
116 IN UINTN Length
117 )
118{
119 UINT32 RegEbx;
120 UINT32 RegEdx;
121 UINTN CacheLineSize;
122 UINTN Start;
123 UINTN End;
124
125 if (Length == 0) {
126 return Address;
127 }
128
129 ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
130
131 //
132 // If the CPU does not support CLFLUSH instruction,
133 // then promote flush range to flush entire cache.
134 //
135 AsmCpuid (0x01, NULL, &RegEbx, NULL, &RegEdx);
136 if ((RegEdx & BIT19) == 0) {
137 AsmWbinvd ();
138 return Address;
139 }
140
141 //
142 // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H
143 //
144 CacheLineSize = (RegEbx & 0xff00) >> 5;
145
146 Start = (UINTN)Address;
147 //
148 // Calculate the cache line alignment
149 //
150 End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
151 Start &= ~((UINTN)CacheLineSize - 1);
152
153 do {
154 Start = (UINTN)AsmFlushCacheLine ((VOID *)Start) + CacheLineSize;
155 } while (Start != End);
156
157 return Address;
158}
159
170VOID
171EFIAPI
173 VOID
174 )
175{
177}
178
204VOID *
205EFIAPI
207 IN VOID *Address,
208 IN UINTN Length
209 )
210{
211 return WriteBackInvalidateDataCacheRange (Address, Length);
212}
213
225VOID
226EFIAPI
228 VOID
229 )
230{
231 AsmInvd ();
232}
233
261VOID *
262EFIAPI
264 IN VOID *Address,
265 IN UINTN Length
266 )
267{
268 //
269 // Invalidation of a data cache range without writing back is not supported on
270 // x86 architecture, so write back and invalidate operation is performed.
271 //
272 return WriteBackInvalidateDataCacheRange (Address, Length);
273}
UINT64 UINTN
#define MAX_ADDRESS
VOID *EFIAPI AsmFlushCacheLine(IN VOID *LinearAddress)
VOID EFIAPI AsmInvd(VOID)
VOID EFIAPI AsmWbinvd(VOID)
#define NULL
Definition: Base.h:319
#define IN
Definition: Base.h:279
UINT32 EFIAPI AsmCpuid(IN UINT32 Index, OUT UINT32 *RegisterEax OPTIONAL, OUT UINT32 *RegisterEbx OPTIONAL, OUT UINT32 *RegisterEcx OPTIONAL, OUT UINT32 *RegisterEdx OPTIONAL)
Definition: CpuId.c:36
VOID EFIAPI InvalidateDataCache(VOID)
Definition: X86Cache.c:227
VOID *EFIAPI WriteBackDataCacheRange(IN VOID *Address, IN UINTN Length)
Definition: X86Cache.c:206
VOID *EFIAPI InvalidateDataCacheRange(IN VOID *Address, IN UINTN Length)
Definition: X86Cache.c:263
VOID *EFIAPI WriteBackInvalidateDataCacheRange(IN VOID *Address, IN UINTN Length)
Definition: X86Cache.c:114
VOID EFIAPI InvalidateInstructionCache(VOID)
Definition: X86Cache.c:21
VOID EFIAPI WriteBackInvalidateDataCache(VOID)
Definition: X86Cache.c:79
VOID EFIAPI WriteBackDataCache(VOID)
Definition: X86Cache.c:172
VOID *EFIAPI InvalidateInstructionCacheRange(IN VOID *Address, IN UINTN Length)
Definition: X86Cache.c:54