TianoCore EDK2 master
Xeon5600Msr.h
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1
18#ifndef __XEON_5600_MSR_H__
19#define __XEON_5600_MSR_H__
20
22
32#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x25 || \
36 DisplayModel == 0x2C \
37 ) \
38 )
39
59#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
60
64typedef union {
68 struct {
78 UINT32 AESConfiguration : 2;
79 UINT32 Reserved1 : 30;
80 UINT32 Reserved2 : 32;
81 } Bits;
85 UINT32 Uint32;
89 UINT64 Uint64;
91
108#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
109
128#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
129
133typedef union {
137 struct {
142 UINT32 Maximum1C : 8;
147 UINT32 Maximum2C : 8;
152 UINT32 Maximum3C : 8;
157 UINT32 Maximum4C : 8;
162 UINT32 Maximum5C : 8;
167 UINT32 Maximum6C : 8;
168 UINT32 Reserved : 16;
169 } Bits;
173 UINT64 Uint64;
175
192#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0
193
194#endif