Xeon5600Msr.h

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#ifndef __XEON_5600_MSR_H__
#define __XEON_5600_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x25 || \
    DisplayModel == 0x2C    \
    )                       \
   )
 
#define MSR_XEON_5600_FEATURE_CONFIG  0x0000013C
 
typedef union {
  struct {
    UINT32    AESConfiguration : 2;
    UINT32    Reserved1        : 30;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
 
#define MSR_XEON_5600_OFFCORE_RSP_1  0x000001A7
 
#define MSR_XEON_5600_TURBO_RATIO_LIMIT  0x000001AD
 
typedef union {
  struct {
    UINT32    Maximum1C : 8;
    UINT32    Maximum2C : 8;
    UINT32    Maximum3C : 8;
    UINT32    Maximum4C : 8;
    UINT32    Maximum5C : 8;
    UINT32    Maximum6C : 8;
    UINT32    Reserved  : 16;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
 
#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS  0x000001B0
 
#endif