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Xeon5600Msr.h File Reference

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Data Structures

union  MSR_XEON_5600_FEATURE_CONFIG_REGISTER
 
union  MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
 

Macros

#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_XEON_5600_FEATURE_CONFIG   0x0000013C
 
#define MSR_XEON_5600_OFFCORE_RSP_1   0x000001A7
 
#define MSR_XEON_5600_TURBO_RATIO_LIMIT   0x000001AD
 
#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS   0x000001B0
 

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file Xeon5600Msr.h.

Macro Definition Documentation

◆ IS_XEON_5600_PROCESSOR

#define IS_XEON_5600_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x25 || \
DisplayModel == 0x2C \
) \
)

Is Intel(R) Xeon(R) Processor Series 5600?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.

Definition at line 32 of file Xeon5600Msr.h.

◆ MSR_XEON_5600_FEATURE_CONFIG

#define MSR_XEON_5600_FEATURE_CONFIG   0x0000013C

Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

Parameters
ECXMSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.

Example usage

UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
#define MSR_XEON_5600_FEATURE_CONFIG
Definition: Xeon5600Msr.h:59
Note
MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.

Definition at line 59 of file Xeon5600Msr.h.

◆ MSR_XEON_5600_IA32_ENERGY_PERF_BIAS

#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS   0x000001B0

Package. See Table 2-2.

Parameters
ECXMSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.

Definition at line 192 of file Xeon5600Msr.h.

◆ MSR_XEON_5600_OFFCORE_RSP_1

#define MSR_XEON_5600_OFFCORE_RSP_1   0x000001A7

Thread. Offcore Response Event Select Register (R/W).

Parameters
ECXMSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.

Definition at line 108 of file Xeon5600Msr.h.

◆ MSR_XEON_5600_TURBO_RATIO_LIMIT

#define MSR_XEON_5600_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters
ECXMSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.

Example usage

Note
MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

Definition at line 128 of file Xeon5600Msr.h.