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Aesni.c
Go to the documentation of this file.
1
9#include "CpuCommonFeatures.h"
10
20VOID *
21EFIAPI
23 IN UINTN NumberOfProcessors
24 )
25{
26 UINT64 *ConfigData;
27
28 ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);
29 ASSERT (ConfigData != NULL);
30 return ConfigData;
31}
32
49BOOLEAN
50EFIAPI
52 IN UINTN ProcessorNumber,
54 IN VOID *ConfigData OPTIONAL
55 )
56{
58
59 if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {
60 MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
61 ASSERT (MsrFeatureConfig != NULL);
62 MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
63 return TRUE;
64 }
65
66 return FALSE;
67}
68
86RETURN_STATUS
87EFIAPI
89 IN UINTN ProcessorNumber,
91 IN VOID *ConfigData OPTIONAL,
92 IN BOOLEAN State
93 )
94{
96
97 //
98 // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,
99 // Simply use MSR_SANDY_BRIDGE_FEATURE_CONFIG here
100 //
101 // The scope of the MSR_SANDY_BRIDGE_FEATURE_CONFIG is Core, only program MSR_FEATURE_CONFIG for thread 0
102 // of each core. Otherwise, once a thread in the core disabled AES, the other thread will cause GP when
103 // programming it.
104 //
105 if (CpuInfo->ProcessorInfo.Location.Thread == 0) {
106 MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
107 ASSERT (MsrFeatureConfig != NULL);
108 if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {
110 ProcessorNumber,
111 Msr,
114 Bits.AESConfiguration,
115 BIT0 | ((State) ? 0 : BIT1)
116 );
117 }
118 }
119
120 return RETURN_SUCCESS;
121}
UINT64 UINTN
VOID *EFIAPI AesniGetConfigData(IN UINTN NumberOfProcessors)
Definition: Aesni.c:22
BOOLEAN EFIAPI AesniSupport(IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
Definition: Aesni.c:51
RETURN_STATUS EFIAPI AesniInitialize(IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL, IN BOOLEAN State)
Definition: Aesni.c:88
VOID *EFIAPI AllocateZeroPool(IN UINTN AllocationSize)
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
#define NULL
Definition: Base.h:319
#define RETURN_SUCCESS
Definition: Base.h:1066
#define TRUE
Definition: Base.h:301
#define FALSE
Definition: Base.h:307
#define IN
Definition: Base.h:279
#define CPU_REGISTER_TABLE_WRITE_FIELD(ProcessorNumber, RegisterType, Index, Type, Field, Value)
#define MSR_SANDY_BRIDGE_FEATURE_CONFIG