Pentium4Msr.h

Go to the documentation of this file.

 
#ifndef __PENTIUM_4_MSR_H__
#define __PENTIUM_4_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x0F \
   )
 
#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE  0x00000006
 
#define MSR_PENTIUM_4_EBC_HARD_POWERON  0x0000002A
 
typedef union {
  struct {
    UINT32    OutputTriStateEnabled     : 1;
    UINT32    ExecuteBIST               : 1;
    UINT32    InOrderQueueDepth         : 1;
    UINT32    MCERR_ObservationDisabled : 1;
    UINT32    BINIT_ObservationEnabled  : 1;
    UINT32    APICClusterID             : 2;
    UINT32    BusParkDisable            : 1;
    UINT32    Reserved1                 : 4;
    UINT32    AgentID                   : 2;
    UINT32    Reserved2                 : 18;
    UINT32    Reserved3                 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;
 
#define MSR_PENTIUM_4_EBC_SOFT_POWERON  0x0000002B
 
typedef union {
  struct {
    UINT32    RCNT_SCNT                          : 1;
    UINT32    DataErrorCheckingDisable           : 1;
    UINT32    ResponseErrorCheckingDisable       : 1;
    UINT32    AddressRequestErrorCheckingDisable : 1;
    UINT32    InitiatorMCERR_Disable             : 1;
    UINT32    InternalMCERR_Disable              : 1;
    UINT32    BINIT_DriverDisable                : 1;
    UINT32    Reserved1                          : 25;
    UINT32    Reserved2                          : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;
 
#define MSR_PENTIUM_4_EBC_FREQUENCY_ID  0x0000002C
 
typedef union {
  struct {
    UINT32    Reserved1 : 16;
    UINT32    ScalableBusSpeed : 3;
    UINT32    Reserved2        : 5;
    UINT32    ClockRatio       : 8;
    UINT32    Reserved3        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;
 
#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1  0x0000002C
 
typedef union {
  struct {
    UINT32    Reserved1        : 21;
    UINT32    ScalableBusSpeed : 3;
    UINT32    Reserved2        : 8;
    UINT32    Reserved3        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;
 
#define MSR_PENTIUM_4_MCG_RAX  0x00000180
 
#define MSR_PENTIUM_4_MCG_RBX  0x00000181
 
#define MSR_PENTIUM_4_MCG_RCX  0x00000182
 
#define MSR_PENTIUM_4_MCG_RDX  0x00000183
 
#define MSR_PENTIUM_4_MCG_RSI  0x00000184
 
#define MSR_PENTIUM_4_MCG_RDI  0x00000185
 
#define MSR_PENTIUM_4_MCG_RBP  0x00000186
 
#define MSR_PENTIUM_4_MCG_RSP  0x00000187
 
#define MSR_PENTIUM_4_MCG_RFLAGS  0x00000188
 
#define MSR_PENTIUM_4_MCG_RIP  0x00000189
 
#define MSR_PENTIUM_4_MCG_MISC  0x0000018A
 
typedef union {
  struct {
    UINT32    DS        : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_4_MCG_MISC_REGISTER;
 
#define MSR_PENTIUM_4_MCG_R8  0x00000190
 
#define MSR_PENTIUM_4_MCG_R9  0x00000191
 
#define MSR_PENTIUM_4_MCG_R10  0x00000192
 
#define MSR_PENTIUM_4_MCG_R11  0x00000193
 
#define MSR_PENTIUM_4_MCG_R12  0x00000194
 
#define MSR_PENTIUM_4_MCG_R13  0x00000195
 
#define MSR_PENTIUM_4_MCG_R14  0x00000196
 
#define MSR_PENTIUM_4_MCG_R15  0x00000197
 
#define MSR_PENTIUM_4_THERM2_CTL  0x0000019D
 
#define MSR_PENTIUM_4_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    FastStrings : 1;
    UINT32    Reserved1   : 1;
    UINT32    FPU         : 1;
    UINT32    TM1         : 1;
    UINT32    SplitLockDisable : 1;
    UINT32    Reserved2        : 1;
    UINT32    ThirdLevelCacheDisable : 1;
    UINT32    PerformanceMonitoring  : 1;
    UINT32    SuppressLockEnable     : 1;
    UINT32    PrefetchQueueDisable   : 1;
    UINT32    FERR : 1;
    UINT32    BTS  : 1;
    UINT32    PEBS : 1;
    UINT32    TM2       : 1;
    UINT32    Reserved3 : 4;
    UINT32    MONITOR   : 1;
    UINT32    AdjacentCacheLinePrefetchDisable : 1;
    UINT32    Reserved4                        : 2;
    UINT32    LimitCpuidMaxval                 : 1;
    UINT32    xTPR_Message_Disable             : 1;
    UINT32    L1DataCacheContextMode : 1;
    UINT32    Reserved5              : 7;
    UINT32    Reserved6              : 2;
    UINT32    XD                     : 1;
    UINT32    Reserved7              : 29;
  } Bits;
  UINT64    Uint64;
} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_PENTIUM_4_PLATFORM_BRV  0x000001A1
 
typedef union {
  struct {
    UINT32    Reserved1 : 18;
    UINT32    PLATFORM  : 1;
    UINT32    Reserved2 : 13;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;
 
#define MSR_PENTIUM_4_LER_FROM_LIP  0x000001D7
 
#define MSR_PENTIUM_4_LER_TO_LIP  0x000001D8
 
#define MSR_PENTIUM_4_DEBUGCTLA  0x000001D9
 
#define MSR_PENTIUM_4_LASTBRANCH_TOS  0x000001DA
 
#define MSR_PENTIUM_4_LASTBRANCH_0  0x000001DB
#define MSR_PENTIUM_4_LASTBRANCH_1  0x000001DC
#define MSR_PENTIUM_4_LASTBRANCH_2  0x000001DD
#define MSR_PENTIUM_4_LASTBRANCH_3  0x000001DE
 
#define MSR_PENTIUM_4_BPU_COUNTER0  0x00000300
#define MSR_PENTIUM_4_BPU_COUNTER1  0x00000301
#define MSR_PENTIUM_4_BPU_COUNTER2  0x00000302
#define MSR_PENTIUM_4_BPU_COUNTER3  0x00000303
 
#define MSR_PENTIUM_4_MS_COUNTER0  0x00000304
#define MSR_PENTIUM_4_MS_COUNTER1  0x00000305
#define MSR_PENTIUM_4_MS_COUNTER2  0x00000306
#define MSR_PENTIUM_4_MS_COUNTER3  0x00000307
 
#define MSR_PENTIUM_4_FLAME_COUNTER0  0x00000308
#define MSR_PENTIUM_4_FLAME_COUNTER1  0x00000309
#define MSR_PENTIUM_4_FLAME_COUNTER2  0x0000030A
#define MSR_PENTIUM_4_FLAME_COUNTER3  0x0000030B
 
#define MSR_PENTIUM_4_IQ_COUNTER0  0x0000030C
#define MSR_PENTIUM_4_IQ_COUNTER1  0x0000030D
#define MSR_PENTIUM_4_IQ_COUNTER2  0x0000030E
#define MSR_PENTIUM_4_IQ_COUNTER3  0x0000030F
#define MSR_PENTIUM_4_IQ_COUNTER4  0x00000310
#define MSR_PENTIUM_4_IQ_COUNTER5  0x00000311
 
#define MSR_PENTIUM_4_BPU_CCCR0  0x00000360
#define MSR_PENTIUM_4_BPU_CCCR1  0x00000361
#define MSR_PENTIUM_4_BPU_CCCR2  0x00000362
#define MSR_PENTIUM_4_BPU_CCCR3  0x00000363
 
#define MSR_PENTIUM_4_MS_CCCR0  0x00000364
#define MSR_PENTIUM_4_MS_CCCR1  0x00000365
#define MSR_PENTIUM_4_MS_CCCR2  0x00000366
#define MSR_PENTIUM_4_MS_CCCR3  0x00000367
 
#define MSR_PENTIUM_4_FLAME_CCCR0  0x00000368
#define MSR_PENTIUM_4_FLAME_CCCR1  0x00000369
#define MSR_PENTIUM_4_FLAME_CCCR2  0x0000036A
#define MSR_PENTIUM_4_FLAME_CCCR3  0x0000036B
 
#define MSR_PENTIUM_4_IQ_CCCR0  0x0000036C
#define MSR_PENTIUM_4_IQ_CCCR1  0x0000036D
#define MSR_PENTIUM_4_IQ_CCCR2  0x0000036E
#define MSR_PENTIUM_4_IQ_CCCR3  0x0000036F
#define MSR_PENTIUM_4_IQ_CCCR4  0x00000370
#define MSR_PENTIUM_4_IQ_CCCR5  0x00000371
 
#define MSR_PENTIUM_4_BSU_ESCR0  0x000003A0
 
#define MSR_PENTIUM_4_BSU_ESCR1  0x000003A1
 
#define MSR_PENTIUM_4_FSB_ESCR0  0x000003A2
 
#define MSR_PENTIUM_4_FSB_ESCR1  0x000003A3
 
#define MSR_PENTIUM_4_FIRM_ESCR0  0x000003A4
 
#define MSR_PENTIUM_4_FIRM_ESCR1  0x000003A5
 
#define MSR_PENTIUM_4_FLAME_ESCR0  0x000003A6
 
#define MSR_PENTIUM_4_FLAME_ESCR1  0x000003A7
 
#define MSR_PENTIUM_4_DAC_ESCR0  0x000003A8
 
#define MSR_PENTIUM_4_DAC_ESCR1  0x000003A9
 
#define MSR_PENTIUM_4_MOB_ESCR0  0x000003AA
 
#define MSR_PENTIUM_4_MOB_ESCR1  0x000003AB
 
#define MSR_PENTIUM_4_PMH_ESCR0  0x000003AC
 
#define MSR_PENTIUM_4_PMH_ESCR1  0x000003AD
 
#define MSR_PENTIUM_4_SAAT_ESCR0  0x000003AE
 
#define MSR_PENTIUM_4_SAAT_ESCR1  0x000003AF
 
#define MSR_PENTIUM_4_U2L_ESCR0  0x000003B0
 
#define MSR_PENTIUM_4_U2L_ESCR1  0x000003B1
 
#define MSR_PENTIUM_4_BPU_ESCR0  0x000003B2
 
#define MSR_PENTIUM_4_BPU_ESCR1  0x000003B3
 
#define MSR_PENTIUM_4_IS_ESCR0  0x000003B4
 
#define MSR_PENTIUM_4_IS_ESCR1  0x000003B5
 
#define MSR_PENTIUM_4_ITLB_ESCR0  0x000003B6
 
#define MSR_PENTIUM_4_ITLB_ESCR1  0x000003B7
 
#define MSR_PENTIUM_4_CRU_ESCR0  0x000003B8
 
#define MSR_PENTIUM_4_CRU_ESCR1  0x000003B9
 
#define MSR_PENTIUM_4_IQ_ESCR0  0x000003BA
 
#define MSR_PENTIUM_4_IQ_ESCR1  0x000003BB
 
#define MSR_PENTIUM_4_RAT_ESCR0  0x000003BC
 
#define MSR_PENTIUM_4_RAT_ESCR1  0x000003BD
 
#define MSR_PENTIUM_4_SSU_ESCR0  0x000003BE
 
#define MSR_PENTIUM_4_MS_ESCR0  0x000003C0
 
#define MSR_PENTIUM_4_MS_ESCR1  0x000003C1
 
#define MSR_PENTIUM_4_TBPU_ESCR0  0x000003C2
 
#define MSR_PENTIUM_4_TBPU_ESCR1  0x000003C3
 
#define MSR_PENTIUM_4_TC_ESCR0  0x000003C4
 
#define MSR_PENTIUM_4_TC_ESCR1  0x000003C5
 
#define MSR_PENTIUM_4_IX_ESCR0  0x000003C8
 
#define MSR_PENTIUM_4_IX_ESCR1  0x000003C9
 
#define MSR_PENTIUM_4_ALF_ESCR0  0x000003CA
#define MSR_PENTIUM_4_ALF_ESCR1  0x000003CB
#define MSR_PENTIUM_4_CRU_ESCR2  0x000003CC
#define MSR_PENTIUM_4_CRU_ESCR3  0x000003CD
#define MSR_PENTIUM_4_CRU_ESCR4  0x000003E0
#define MSR_PENTIUM_4_CRU_ESCR5  0x000003E1
 
#define MSR_PENTIUM_4_TC_PRECISE_EVENT  0x000003F0
 
#define MSR_PENTIUM_4_PEBS_ENABLE  0x000003F1
 
typedef union {
  struct {
    UINT32    EventNum            : 13;
    UINT32    Reserved1           : 11;
    UINT32    UOP                 : 1;
    UINT32    ENABLE_PEBS_MY_THR  : 1;
    UINT32    ENABLE_PEBS_OTH_THR : 1;
    UINT32    Reserved2           : 5;
    UINT32    Reserved3           : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;
 
#define MSR_PENTIUM_4_PEBS_MATRIX_VERT  0x000003F2
 
#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP   0x00000680
#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP   0x00000681
#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP   0x00000682
#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP   0x00000683
#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP   0x00000684
#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP   0x00000685
#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP   0x00000686
#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP   0x00000687
#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP   0x00000688
#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP   0x00000689
#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP  0x0000068A
#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP  0x0000068B
#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP  0x0000068C
#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP  0x0000068D
#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP  0x0000068E
#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP  0x0000068F
 
#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP   0x000006C0
#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP   0x000006C1
#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP   0x000006C2
#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP   0x000006C3
#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP   0x000006C4
#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP   0x000006C5
#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP   0x000006C6
#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP   0x000006C7
#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP   0x000006C8
#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP   0x000006C9
#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP  0x000006CA
#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP  0x000006CB
#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP  0x000006CC
#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP  0x000006CD
#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP  0x000006CE
#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP  0x000006CF
 
#define MSR_PENTIUM_4_IFSB_BUSQ0  0x000107CC
 
#define MSR_PENTIUM_4_IFSB_BUSQ1  0x000107CD
 
#define MSR_PENTIUM_4_IFSB_SNPQ0  0x000107CE
 
#define MSR_PENTIUM_4_IFSB_SNPQ1  0x000107CF
 
#define MSR_PENTIUM_4_EFSB_DRDY0  0x000107D0
 
#define MSR_PENTIUM_4_EFSB_DRDY1  0x000107D1
 
#define MSR_PENTIUM_4_IFSB_CTL6  0x000107D2
 
#define MSR_PENTIUM_4_IFSB_CNTR7  0x000107D3
 
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0  0x000107CC
 
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1  0x000107CD
 
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2  0x000107CE
 
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3  0x000107CF
 
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4  0x000107D0
 
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5  0x000107D1
 
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6  0x000107D2
 
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7  0x000107D3
 
#endif