PentiumMMsr.h

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#ifndef __PENTIUM_M_MSR_H__
#define __PENTIUM_M_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   ( \
    DisplayModel == 0x0D \
    ) \
   )
 
#define MSR_PENTIUM_M_P5_MC_ADDR  0x00000000
 
#define MSR_PENTIUM_M_P5_MC_TYPE  0x00000001
 
#define MSR_PENTIUM_M_EBL_CR_POWERON  0x0000002A
 
typedef union {
  struct {
    UINT32    Reserved1                   : 1;
    UINT32    DataErrorCheckingEnable     : 1;
    UINT32    ResponseErrorCheckingEnable : 1;
    UINT32    MCERR_DriveEnable           : 1;
    UINT32    AddressParityEnable         : 1;
    UINT32    Reserved2                   : 2;
    UINT32    BINIT_DriverEnable          : 1;
    UINT32    OutputTriStateEnable        : 1;
    UINT32    ExecuteBIST                 : 1;
    UINT32    MCERR_ObservationEnabled    : 1;
    UINT32    Reserved3                   : 1;
    UINT32    BINIT_ObservationEnabled    : 1;
    UINT32    Reserved4                   : 1;
    UINT32    ResetVector                 : 1;
    UINT32    Reserved5                   : 1;
    UINT32    APICClusterID               : 2;
    UINT32    SystemBusFrequency          : 1;
    UINT32    Reserved6                   : 1;
    UINT32    SymmetricArbitrationID      : 2;
    UINT32    ClockFrequencyRatio         : 5;
    UINT32    Reserved7                   : 5;
    UINT32    Reserved8                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
 
#define MSR_PENTIUM_M_LASTBRANCH_0  0x00000040
#define MSR_PENTIUM_M_LASTBRANCH_1  0x00000041
#define MSR_PENTIUM_M_LASTBRANCH_2  0x00000042
#define MSR_PENTIUM_M_LASTBRANCH_3  0x00000043
#define MSR_PENTIUM_M_LASTBRANCH_4  0x00000044
#define MSR_PENTIUM_M_LASTBRANCH_5  0x00000045
#define MSR_PENTIUM_M_LASTBRANCH_6  0x00000046
#define MSR_PENTIUM_M_LASTBRANCH_7  0x00000047
 
#define MSR_PENTIUM_M_BBL_CR_CTL  0x00000119
 
#define MSR_PENTIUM_M_BBL_CR_CTL3  0x0000011E
 
typedef union {
  struct {
    UINT32    L2HardwareEnabled : 1;
    UINT32    Reserved1         : 4;
    UINT32    ECCCheckEnable    : 1;
    UINT32    Reserved2         : 2;
    UINT32    L2Enabled         : 1;
    UINT32    Reserved3         : 14;
    UINT32    L2NotPresent      : 1;
    UINT32    Reserved4         : 8;
    UINT32    Reserved5         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
 
#define MSR_PENTIUM_M_THERM2_CTL  0x0000019D
 
typedef union {
  struct {
    UINT32    Reserved1 : 16;
    UINT32    TM_SELECT : 1;
    UINT32    Reserved2 : 15;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_M_THERM2_CTL_REGISTER;
 
#define MSR_PENTIUM_M_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    Reserved1 : 3;
    UINT32    AutomaticThermalControlCircuit : 1;
    UINT32    Reserved2                      : 3;
    UINT32    PerformanceMonitoring          : 1;
    UINT32    Reserved3                      : 2;
    UINT32    FERR                 : 1;
    UINT32    BTS                  : 1;
    UINT32    PEBS                 : 1;
    UINT32    Reserved5            : 3;
    UINT32    EIST                 : 1;
    UINT32    Reserved6            : 6;
    UINT32    xTPR_Message_Disable : 1;
    UINT32    Reserved7            : 8;
    UINT32    Reserved8            : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_PENTIUM_M_LASTBRANCH_TOS  0x000001C9
 
#define MSR_PENTIUM_M_DEBUGCTLB  0x000001D9
 
#define MSR_PENTIUM_M_LER_TO_LIP  0x000001DD
 
#define MSR_PENTIUM_M_LER_FROM_LIP  0x000001DE
 
#define MSR_PENTIUM_M_MC4_CTL  0x0000040C
 
#define MSR_PENTIUM_M_MC4_STATUS  0x0000040D
 
#define MSR_PENTIUM_M_MC4_ADDR  0x0000040E
 
#define MSR_PENTIUM_M_MC3_CTL  0x00000410
 
#define MSR_PENTIUM_M_MC3_STATUS  0x00000411
 
#define MSR_PENTIUM_M_MC3_ADDR  0x00000412
 
#endif