TianoCore EDK2 master
PentiumMMsr.h
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1
18#ifndef __PENTIUM_M_MSR_H__
19#define __PENTIUM_M_MSR_H__
20
22
32#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x0D \
36 ) \
37 )
38
55#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
56
73#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
74
94#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
95
99typedef union {
103 struct {
104 UINT32 Reserved1 : 1;
125 UINT32 Reserved2 : 2;
138 UINT32 ExecuteBIST : 1;
144 UINT32 Reserved3 : 1;
150 UINT32 Reserved4 : 1;
155 UINT32 ResetVector : 1;
156 UINT32 Reserved5 : 1;
161 UINT32 APICClusterID : 2;
167 UINT32 Reserved6 : 1;
177 UINT32 Reserved7 : 5;
178 UINT32 Reserved8 : 32;
179 } Bits;
183 UINT32 Uint32;
187 UINT64 Uint64;
189
218#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
219#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
220#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
221#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
222#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
223#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
224#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
225#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
227
244#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
245
264#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
265
269typedef union {
273 struct {
279 UINT32 Reserved1 : 4;
286 UINT32 ECCCheckEnable : 1;
287 UINT32 Reserved2 : 2;
293 UINT32 L2Enabled : 1;
294 UINT32 Reserved3 : 14;
298 UINT32 L2NotPresent : 1;
299 UINT32 Reserved4 : 8;
300 UINT32 Reserved5 : 32;
301 } Bits;
305 UINT32 Uint32;
309 UINT64 Uint64;
311
330#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
331
335typedef union {
339 struct {
340 UINT32 Reserved1 : 16;
348 UINT32 TM_SELECT : 1;
349 UINT32 Reserved2 : 15;
350 UINT32 Reserved3 : 32;
351 } Bits;
355 UINT32 Uint32;
359 UINT64 Uint64;
361
381#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
382
386typedef union {
390 struct {
391 UINT32 Reserved1 : 3;
407 UINT32 Reserved2 : 3;
413 UINT32 Reserved3 : 2;
422 UINT32 FERR : 1;
428 UINT32 BTS : 1;
434 UINT32 PEBS : 1;
435 UINT32 Reserved5 : 3;
441 UINT32 EIST : 1;
442 UINT32 Reserved6 : 6;
450 UINT32 Reserved7 : 8;
451 UINT32 Reserved8 : 32;
452 } Bits;
456 UINT32 Uint32;
460 UINT64 Uint64;
462
482#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
483
502#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
503
524#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
525
545#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
546
563#define MSR_PENTIUM_M_MC4_CTL 0x0000040C
564
581#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
582
602#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
603
620#define MSR_PENTIUM_M_MC3_CTL 0x00000410
621
638#define MSR_PENTIUM_M_MC3_STATUS 0x00000411
639
659#define MSR_PENTIUM_M_MC3_ADDR 0x00000412
660
661#endif