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PentiumMMsr.h File Reference

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Data Structures

union  MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
 
union  MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
 
union  MSR_PENTIUM_M_THERM2_CTL_REGISTER
 
union  MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
 

Macros

#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_PENTIUM_M_P5_MC_ADDR   0x00000000
 
#define MSR_PENTIUM_M_P5_MC_TYPE   0x00000001
 
#define MSR_PENTIUM_M_EBL_CR_POWERON   0x0000002A
 
#define MSR_PENTIUM_M_BBL_CR_CTL   0x00000119
 
#define MSR_PENTIUM_M_BBL_CR_CTL3   0x0000011E
 
#define MSR_PENTIUM_M_THERM2_CTL   0x0000019D
 
#define MSR_PENTIUM_M_IA32_MISC_ENABLE   0x000001A0
 
#define MSR_PENTIUM_M_LASTBRANCH_TOS   0x000001C9
 
#define MSR_PENTIUM_M_DEBUGCTLB   0x000001D9
 
#define MSR_PENTIUM_M_LER_TO_LIP   0x000001DD
 
#define MSR_PENTIUM_M_LER_FROM_LIP   0x000001DE
 
#define MSR_PENTIUM_M_MC4_CTL   0x0000040C
 
#define MSR_PENTIUM_M_MC4_STATUS   0x0000040D
 
#define MSR_PENTIUM_M_MC4_ADDR   0x0000040E
 
#define MSR_PENTIUM_M_MC3_CTL   0x00000410
 
#define MSR_PENTIUM_M_MC3_STATUS   0x00000411
 
#define MSR_PENTIUM_M_MC3_ADDR   0x00000412
 
#define MSR_PENTIUM_M_LASTBRANCH_0   0x00000040
 
#define MSR_PENTIUM_M_LASTBRANCH_1   0x00000041
 
#define MSR_PENTIUM_M_LASTBRANCH_2   0x00000042
 
#define MSR_PENTIUM_M_LASTBRANCH_3   0x00000043
 
#define MSR_PENTIUM_M_LASTBRANCH_4   0x00000044
 
#define MSR_PENTIUM_M_LASTBRANCH_5   0x00000045
 
#define MSR_PENTIUM_M_LASTBRANCH_6   0x00000046
 
#define MSR_PENTIUM_M_LASTBRANCH_7   0x00000047
 

Detailed Description

MSR Definitions for Pentium M Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file PentiumMMsr.h.

Macro Definition Documentation

◆ IS_PENTIUM_M_PROCESSOR

#define IS_PENTIUM_M_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x0D \
) \
)

Is Pentium M Processors?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.

Definition at line 32 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_BBL_CR_CTL

#define MSR_PENTIUM_M_BBL_CR_CTL   0x00000119

Reserved.

Parameters
ECXMSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
#define MSR_PENTIUM_M_BBL_CR_CTL
Definition: PentiumMMsr.h:244
Note
MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.

Definition at line 244 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_BBL_CR_CTL3

#define MSR_PENTIUM_M_BBL_CR_CTL3   0x0000011E
Parameters
ECXMSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
EAXLower 32-bits of MSR value. Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.

Example usage

Note
MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.

Definition at line 264 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_DEBUGCTLB

#define MSR_PENTIUM_M_DEBUGCTLB   0x000001D9

Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters
ECXMSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_DEBUGCTLB
Definition: PentiumMMsr.h:502
Note
MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.

Definition at line 502 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_EBL_CR_POWERON

#define MSR_PENTIUM_M_EBL_CR_POWERON   0x0000002A

Processor Hard Power-On Configuration (R/W) Enables and disables processor features. (R) Indicates current processor configuration.

Parameters
ECXMSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
EAXLower 32-bits of MSR value. Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.

Example usage

Note
MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.

Definition at line 94 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_IA32_MISC_ENABLE

#define MSR_PENTIUM_M_IA32_MISC_ENABLE   0x000001A0

Enable Miscellaneous Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters
ECXMSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
EAXLower 32-bits of MSR value. Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.

Example usage

Note
MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

Definition at line 381 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_0

#define MSR_PENTIUM_M_LASTBRANCH_0   0x00000040

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters
ECXMSR_PENTIUM_M_LASTBRANCH_n
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_LASTBRANCH_0
Definition: PentiumMMsr.h:218
Note
MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

Definition at line 218 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_1

#define MSR_PENTIUM_M_LASTBRANCH_1   0x00000041

Definition at line 219 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_2

#define MSR_PENTIUM_M_LASTBRANCH_2   0x00000042

Definition at line 220 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_3

#define MSR_PENTIUM_M_LASTBRANCH_3   0x00000043

Definition at line 221 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_4

#define MSR_PENTIUM_M_LASTBRANCH_4   0x00000044

Definition at line 222 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_5

#define MSR_PENTIUM_M_LASTBRANCH_5   0x00000045

Definition at line 223 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_6

#define MSR_PENTIUM_M_LASTBRANCH_6   0x00000046

Definition at line 224 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_7

#define MSR_PENTIUM_M_LASTBRANCH_7   0x00000047

Definition at line 225 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LASTBRANCH_TOS

#define MSR_PENTIUM_M_LASTBRANCH_TOS   0x000001C9

Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See also: - MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters
ECXMSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

Definition at line 482 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LER_FROM_LIP

#define MSR_PENTIUM_M_LER_FROM_LIP   0x000001DE

Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".

Parameters
ECXMSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_LER_FROM_LIP
Definition: PentiumMMsr.h:545
Note
MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

Definition at line 545 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_LER_TO_LIP

#define MSR_PENTIUM_M_LER_TO_LIP   0x000001DD

Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".

Parameters
ECXMSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_LER_TO_LIP
Definition: PentiumMMsr.h:524
Note
MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

Definition at line 524 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_MC3_ADDR

#define MSR_PENTIUM_M_MC3_ADDR   0x00000412

See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Parameters
ECXMSR_PENTIUM_M_MC3_ADDR (0x00000412)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_MC3_ADDR
Definition: PentiumMMsr.h:659
Note
MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.

Definition at line 659 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_MC3_CTL

#define MSR_PENTIUM_M_MC3_CTL   0x00000410

See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".

Parameters
ECXMSR_PENTIUM_M_MC3_CTL (0x00000410)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_MC3_CTL
Definition: PentiumMMsr.h:620
Note
MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.

Definition at line 620 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_MC3_STATUS

#define MSR_PENTIUM_M_MC3_STATUS   0x00000411

See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".

Parameters
ECXMSR_PENTIUM_M_MC3_STATUS (0x00000411)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_MC3_STATUS
Definition: PentiumMMsr.h:638
Note
MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.

Definition at line 638 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_MC4_ADDR

#define MSR_PENTIUM_M_MC4_ADDR   0x0000040E

See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Parameters
ECXMSR_PENTIUM_M_MC4_ADDR (0x0000040E)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_MC4_ADDR
Definition: PentiumMMsr.h:602
Note
MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.

Definition at line 602 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_MC4_CTL

#define MSR_PENTIUM_M_MC4_CTL   0x0000040C

See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".

Parameters
ECXMSR_PENTIUM_M_MC4_CTL (0x0000040C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_MC4_CTL
Definition: PentiumMMsr.h:563
Note
MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.

Definition at line 563 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_MC4_STATUS

#define MSR_PENTIUM_M_MC4_STATUS   0x0000040D

See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".

Parameters
ECXMSR_PENTIUM_M_MC4_STATUS (0x0000040D)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_MC4_STATUS
Definition: PentiumMMsr.h:581
Note
MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.

Definition at line 581 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_P5_MC_ADDR

#define MSR_PENTIUM_M_P5_MC_ADDR   0x00000000

See Section 2.22, "MSRs in Pentium Processors.".

Parameters
ECXMSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_P5_MC_ADDR
Definition: PentiumMMsr.h:55
Note
MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.

Definition at line 55 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_P5_MC_TYPE

#define MSR_PENTIUM_M_P5_MC_TYPE   0x00000001

See Section 2.22, "MSRs in Pentium Processors.".

Parameters
ECXMSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_PENTIUM_M_P5_MC_TYPE
Definition: PentiumMMsr.h:73
Note
MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.

Definition at line 73 of file PentiumMMsr.h.

◆ MSR_PENTIUM_M_THERM2_CTL

#define MSR_PENTIUM_M_THERM2_CTL   0x0000019D
Parameters
ECXMSR_PENTIUM_M_THERM2_CTL (0x0000019D)
EAXLower 32-bits of MSR value. Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.

Example usage

Note
MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.

Definition at line 330 of file PentiumMMsr.h.