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SmbiosProcessorAArch64.c
Go to the documentation of this file.
1
10#include <Uefi.h>
12#include <Library/ArmLib.h>
13
14#include "SmbiosProcessor.h"
15
24UINT64
26 IN UINT8 CacheLevel,
27 IN BOOLEAN DataCache,
28 IN BOOLEAN UnifiedCache
29 )
30{
31 CCSIDR_DATA Ccsidr;
32 CSSELR_DATA Csselr;
33 BOOLEAN CcidxSupported;
34 UINT64 CacheSize;
35
36 Csselr.Data = 0;
37 Csselr.Bits.Level = CacheLevel - 1;
38 Csselr.Bits.InD = (!DataCache && !UnifiedCache);
39
40 Ccsidr.Data = ReadCCSIDR (Csselr.Data);
41
42 CcidxSupported = ArmHasCcidx ();
43
44 if (CcidxSupported) {
45 CacheSize = (1 << (Ccsidr.BitsCcidxAA64.LineSize + 4)) *
46 (Ccsidr.BitsCcidxAA64.Associativity + 1) *
47 (Ccsidr.BitsCcidxAA64.NumSets + 1);
48 } else {
49 CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *
50 (Ccsidr.BitsNonCcidx.Associativity + 1) *
51 (Ccsidr.BitsNonCcidx.NumSets + 1);
52 }
53
54 return CacheSize;
55}
56
65UINT32
67 IN UINT8 CacheLevel,
68 IN BOOLEAN DataCache,
69 IN BOOLEAN UnifiedCache
70 )
71{
72 CCSIDR_DATA Ccsidr;
73 CSSELR_DATA Csselr;
74 BOOLEAN CcidxSupported;
75 UINT32 Associativity;
76
77 Csselr.Data = 0;
78 Csselr.Bits.Level = CacheLevel - 1;
79 Csselr.Bits.InD = (!DataCache && !UnifiedCache);
80
81 Ccsidr.Data = ReadCCSIDR (Csselr.Data);
82
83 CcidxSupported = ArmHasCcidx ();
84
85 if (CcidxSupported) {
86 Associativity = Ccsidr.BitsCcidxAA64.Associativity + 1;
87 } else {
88 Associativity = Ccsidr.BitsNonCcidx.Associativity + 1;
89 }
90
91 return Associativity;
92}
BOOLEAN EFIAPI ArmHasCcidx(VOID)
Definition: AArch64Lib.c:43
UINTN ReadCCSIDR(IN UINT32 CSSELR)
#define IN
Definition: Base.h:279
UINT64 SmbiosProcessorGetCacheSize(IN UINT8 CacheLevel, IN BOOLEAN DataCache, IN BOOLEAN UnifiedCache)
UINT32 SmbiosProcessorGetCacheAssociativity(IN UINT8 CacheLevel, IN BOOLEAN DataCache, IN BOOLEAN UnifiedCache)
Defines the structure of the CCSIDR (Current Cache Size ID) register.
Definition: ArmCache.h:39
UINT64 Associativity
Associativity - 1.
Definition: ArmCache.h:42
struct CCSIDR_DATA::@2 BitsCcidxAA64
Bitfield definition of the register when FEAT_IDX is supported.
struct CCSIDR_DATA::@1 BitsNonCcidx
Bitfield definition of the register when FEAT_CCIDX is not supported.
UINT64 Data
The entire 64-bit value.
Definition: ArmCache.h:60
UINT64 LineSize
Line size (Log2(Num bytes in cache) - 4)
Definition: ArmCache.h:41
UINT64 NumSets
Number of sets in the cache -1.
Definition: ArmCache.h:43
Defines the structure of the CSSELR (Cache Size Selection) register.
Definition: ArmCache.h:19
UINT32 Level
Cache level (zero based)
Definition: ArmCache.h:22
UINT32 Data
The entire 32-bit value.
Definition: ArmCache.h:26
UINT32 InD
Instruction not Data bit.
Definition: ArmCache.h:21
struct CSSELR_DATA::@0 Bits
Bitfield definition of the register.