28 IN BOOLEAN UnifiedCache
33 BOOLEAN CcidxSupported;
38 Csselr.
Bits.
InD = (!DataCache && !UnifiedCache);
69 IN BOOLEAN UnifiedCache
74 BOOLEAN CcidxSupported;
79 Csselr.
Bits.
InD = (!DataCache && !UnifiedCache);
BOOLEAN EFIAPI ArmHasCcidx(VOID)
UINTN ReadCCSIDR(IN UINT32 CSSELR)
UINT64 SmbiosProcessorGetCacheSize(IN UINT8 CacheLevel, IN BOOLEAN DataCache, IN BOOLEAN UnifiedCache)
UINT32 SmbiosProcessorGetCacheAssociativity(IN UINT8 CacheLevel, IN BOOLEAN DataCache, IN BOOLEAN UnifiedCache)
Defines the structure of the CCSIDR (Current Cache Size ID) register.
UINT64 Associativity
Associativity - 1.
struct CCSIDR_DATA::@2 BitsCcidxAA64
Bitfield definition of the register when FEAT_IDX is supported.
struct CCSIDR_DATA::@1 BitsNonCcidx
Bitfield definition of the register when FEAT_CCIDX is not supported.
UINT64 Data
The entire 64-bit value.
UINT64 LineSize
Line size (Log2(Num bytes in cache) - 4)
UINT64 NumSets
Number of sets in the cache -1.
Defines the structure of the CSSELR (Cache Size Selection) register.
UINT32 Level
Cache level (zero based)
UINT32 Data
The entire 32-bit value.
UINT32 InD
Instruction not Data bit.
struct CSSELR_DATA::@0 Bits
Bitfield definition of the register.