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BroadwellMsr.h File Reference

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Data Structures

union  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER
 
union  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER
 
union  MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER
 
union  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER
 

Macros

#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS   0x0000038E
 
#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL   0x000000E2
 
#define MSR_BROADWELL_TURBO_RATIO_LIMIT   0x000001AD
 
#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT   0x00000620
 
#define MSR_BROADWELL_PP0_ENERGY_STATUS   0x00000639
 

Detailed Description

MSR Definitions for Intel processors based on the Broadwell microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file BroadwellMsr.h.

Macro Definition Documentation

◆ IS_BROADWELL_PROCESSOR

#define IS_BROADWELL_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3D || \
DisplayModel == 0x47 || \
DisplayModel == 0x4F || \
DisplayModel == 0x56 \
) \
)

Is Intel processors based on the Broadwell microarchitecture?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.

Definition at line 32 of file BroadwellMsr.h.

◆ MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS

#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS   0x0000038E

Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".

Parameters
ECXMSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
EAXLower 32-bits of MSR value. Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.

Example usage

#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
Definition: BroadwellMsr.h:61
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
Note
MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.

Definition at line 61 of file BroadwellMsr.h.

◆ MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT

#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT   0x00000620

Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.

Parameters
ECXMSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
EAXLower 32-bits of MSR value. Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.

Example usage

Definition at line 299 of file BroadwellMsr.h.

◆ MSR_BROADWELL_PKG_CST_CONFIG_CONTROL

#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL   0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. <http://biosbits.org>__.

Parameters
ECXMSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAXLower 32-bits of MSR value. Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

Note
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

Definition at line 146 of file BroadwellMsr.h.

◆ MSR_BROADWELL_PP0_ENERGY_STATUS

#define MSR_BROADWELL_PP0_ENERGY_STATUS   0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters
ECXMSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_BROADWELL_PP0_ENERGY_STATUS
Definition: BroadwellMsr.h:349
Note
MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

Definition at line 349 of file BroadwellMsr.h.

◆ MSR_BROADWELL_TURBO_RATIO_LIMIT

#define MSR_BROADWELL_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters
ECXMSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
EAXLower 32-bits of MSR value. Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.

Example usage

Note
MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

Definition at line 231 of file BroadwellMsr.h.