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SmbiosProcessorArmCommon.c
Go to the documentation of this file.
1
11#include <Uefi.h>
15#include <Library/ArmLib.h>
16#include <Library/ArmSmcLib.h>
18
19#include "SmbiosProcessor.h"
20
25UINT8
27 VOID
28 )
29{
30 CLIDR_DATA Clidr;
31 UINT8 CacheLevel;
32 UINT8 MaxCacheLevel;
33
34 MaxCacheLevel = 0;
35
36 // Read the CLIDR register to find out what caches are present.
37 Clidr.Data = ReadCLIDR ();
38
39 // Get the cache type for the L1 cache. If it's 0, there are no caches.
40 if (CLIDR_GET_CACHE_TYPE (Clidr.Data, 1) == ClidrCacheTypeNone) {
41 return 0;
42 }
43
44 for (CacheLevel = 1; CacheLevel <= MAX_ARM_CACHE_LEVEL; CacheLevel++) {
45 if (CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel) == ClidrCacheTypeNone) {
46 MaxCacheLevel = CacheLevel;
47 break;
48 }
49 }
50
51 return MaxCacheLevel;
52}
53
60BOOLEAN
62 UINT8 CacheLevel
63 )
64{
65 CLIDR_CACHE_TYPE CacheType;
66 CLIDR_DATA Clidr;
67 BOOLEAN SeparateCaches;
68
69 SeparateCaches = FALSE;
70
71 Clidr.Data = ReadCLIDR ();
72
73 CacheType = CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel - 1);
74
75 if (CacheType == ClidrCacheTypeSeparate) {
76 SeparateCaches = TRUE;
77 }
78
79 return SeparateCaches;
80}
81
86BOOLEAN
88 VOID
89 )
90{
91 INT32 SmcCallStatus;
92 BOOLEAN Arm64SocIdSupported;
93 UINTN SmcParam;
94
95 Arm64SocIdSupported = FALSE;
96
97 SmcCallStatus = ArmCallSmc0 (SMCCC_VERSION, NULL, NULL, NULL);
98
99 if ((SmcCallStatus < 0) || ((SmcCallStatus >> 16) >= 1)) {
100 SmcParam = SMCCC_ARCH_SOC_ID;
101 SmcCallStatus = ArmCallSmc1 (SMCCC_ARCH_FEATURES, &SmcParam, NULL, NULL);
102 if (SmcCallStatus >= 0) {
103 Arm64SocIdSupported = TRUE;
104 }
105 }
106
107 return Arm64SocIdSupported;
108}
109
120 OUT INT32 *Jep106Code,
121 OUT INT32 *SocRevision
122 )
123{
124 INT32 SmcCallStatus;
125 EFI_STATUS Status;
126 UINTN SmcParam;
127
128 Status = EFI_SUCCESS;
129
130 SmcParam = 0;
131 SmcCallStatus = ArmCallSmc1 (SMCCC_ARCH_SOC_ID, &SmcParam, NULL, NULL);
132
133 if (SmcCallStatus >= 0) {
134 *Jep106Code = SmcCallStatus;
135 } else {
136 Status = EFI_UNSUPPORTED;
137 }
138
139 SmcParam = 1;
140 SmcCallStatus = ArmCallSmc1 (SMCCC_ARCH_SOC_ID, &SmcParam, NULL, NULL);
141
142 if (SmcCallStatus >= 0) {
143 *SocRevision = SmcCallStatus;
144 } else {
145 Status = EFI_UNSUPPORTED;
146 }
147
148 return Status;
149}
150
156UINT64
158 VOID
159 )
160{
161 INT32 Jep106Code;
162 INT32 SocRevision;
163 UINT64 ProcessorId;
164
165 if (HasSmcArm64SocId ()) {
166 SmbiosGetSmcArm64SocId (&Jep106Code, &SocRevision);
167 ProcessorId = ((UINT64)SocRevision << 32) | Jep106Code;
168 } else {
169 ProcessorId = ArmReadMidr ();
170 }
171
172 return ProcessorId;
173}
174
179UINTN
181 VOID
182 )
183{
184 return ArmReadCntFrq ();
185}
186
191UINT8
193 VOID
194 )
195{
196 return ProcessorFamilyIndicatorFamily2;
197}
198
203UINT16
205 VOID
206 )
207{
208 UINTN MainIdRegister;
209 UINT16 ProcessorFamily2;
210
211 MainIdRegister = ArmReadMidr ();
212
213 if (((MainIdRegister >> 16) & 0xF) < 8) {
214 ProcessorFamily2 = ProcessorFamilyARM;
215 } else {
216 if (sizeof (VOID *) == 4) {
217 ProcessorFamily2 = ProcessorFamilyARMv7;
218 } else {
219 ProcessorFamily2 = ProcessorFamilyARMv8;
220 }
221 }
222
223 return ProcessorFamily2;
224}
225
232 VOID
233 )
234{
235 PROCESSOR_CHARACTERISTIC_FLAGS Characteristics;
236
237 ZeroMem (&Characteristics, sizeof (Characteristics));
238
239 Characteristics.ProcessorArm64SocId = HasSmcArm64SocId ();
240
241 return Characteristics;
242}
UINT64 UINTN
CLIDR_CACHE_TYPE
The cache types reported in the CLIDR register.
Definition: ArmCache.h:95
@ ClidrCacheTypeSeparate
There are separate data and instruction caches.
Definition: ArmCache.h:103
@ ClidrCacheTypeNone
No cache is present.
Definition: ArmCache.h:97
UINT32 ReadCLIDR(VOID)
UINTN ArmCallSmc1(IN UINTN Function, IN OUT UINTN *Arg1 OPTIONAL, OUT UINTN *Arg2 OPTIONAL, OUT UINTN *Arg3 OPTIONAL)
Definition: ArmSmc.c:100
UINTN ArmCallSmc0(IN UINTN Function, OUT UINTN *Arg1 OPTIONAL, OUT UINTN *Arg2 OPTIONAL, OUT UINTN *Arg3 OPTIONAL)
Definition: ArmSmc.c:121
VOID *EFIAPI ZeroMem(OUT VOID *Buffer, IN UINTN Length)
#define NULL
Definition: Base.h:319
#define TRUE
Definition: Base.h:301
#define FALSE
Definition: Base.h:307
#define OUT
Definition: Base.h:284
UINT8 SmbiosProcessorGetMaxCacheLevel(VOID)
UINTN SmbiosGetExternalClockFrequency(VOID)
UINT8 SmbiosGetProcessorFamily(VOID)
EFI_STATUS SmbiosGetSmcArm64SocId(OUT INT32 *Jep106Code, OUT INT32 *SocRevision)
BOOLEAN SmbiosProcessorHasSeparateCaches(UINT8 CacheLevel)
UINT16 SmbiosGetProcessorFamily2(VOID)
UINT64 SmbiosGetProcessorId(VOID)
BOOLEAN HasSmcArm64SocId(VOID)
PROCESSOR_CHARACTERISTIC_FLAGS SmbiosGetProcessorCharacteristics(VOID)
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
#define EFI_SUCCESS
Definition: UefiBaseType.h:112
UINT32 Data
The entire 32-bit value.
Definition: ArmCache.h:91