IvyBridgeMsr.h

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#ifndef __IVY_BRIDGE_MSR_H__
#define __IVY_BRIDGE_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x3A || \
    DisplayModel == 0x3E    \
    )                       \
   )
 
#define MSR_IVY_BRIDGE_PLATFORM_INFO  0x000000CE
 
typedef union {
  struct {
    UINT32    Reserved1              : 8;
    UINT32    MaximumNonTurboRatio   : 8;
    UINT32    Reserved2              : 12;
    UINT32    RatioLimit             : 1;
    UINT32    TDPLimit               : 1;
    UINT32    Reserved3              : 2;
    UINT32    LowPowerModeSupport    : 1;
    UINT32    ConfigTDPLevels        : 2;
    UINT32    Reserved4              : 5;
    UINT32    MaximumEfficiencyRatio : 8;
    UINT32    MinimumOperatingRatio  : 8;
    UINT32    Reserved5              : 8;
  } Bits;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
 
#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL  0x000000E2
 
typedef union {
  struct {
    UINT32    Limit          : 3;
    UINT32    Reserved1      : 7;
    UINT32    IO_MWAIT       : 1;
    UINT32    Reserved2      : 4;
    UINT32    CFGLock        : 1;
    UINT32    Reserved3      : 9;
    UINT32    C3AutoDemotion : 1;
    UINT32    C1AutoDemotion : 1;
    UINT32    C3Undemotion   : 1;
    UINT32    C1Undemotion   : 1;
    UINT32    Reserved4      : 3;
    UINT32    Reserved5      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
 
#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL  0x00000648
 
typedef union {
  struct {
    UINT32    Config_TDP_Base : 8;
    UINT32    Reserved1       : 24;
    UINT32    Reserved2       : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;
 
#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1  0x00000649
 
typedef union {
  struct {
    UINT32    PKG_TDP_LVL1          : 15;
    UINT32    Reserved1             : 1;
    UINT32    Config_TDP_LVL1_Ratio : 8;
    UINT32    Reserved2             : 8;
    UINT32    PKG_MAX_PWR_LVL1      : 15;
    UINT32    Reserved3             : 1;
    UINT32    PKG_MIN_PWR_LVL1      : 15;
    UINT32    Reserved4             : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;
 
#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2  0x0000064A
 
typedef union {
  struct {
    UINT32    PKG_TDP_LVL2          : 15;
    UINT32    Reserved1             : 1;
    UINT32    Config_TDP_LVL2_Ratio : 8;
    UINT32    Reserved2             : 8;
    UINT32    PKG_MAX_PWR_LVL2      : 15;
    UINT32    Reserved3             : 1;
    UINT32    PKG_MIN_PWR_LVL2      : 15;
    UINT32    Reserved4             : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;
 
#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL  0x0000064B
 
typedef union {
  struct {
    UINT32    TDP_LEVEL       : 2;
    UINT32    Reserved1       : 29;
    UINT32    Config_TDP_Lock : 1;
    UINT32    Reserved2       : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;
 
#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO  0x0000064C
 
typedef union {
  struct {
    UINT32    MAX_NON_TURBO_RATIO         : 8;
    UINT32    Reserved1                   : 23;
    UINT32    TURBO_ACTIVATION_RATIO_Lock : 1;
    UINT32    Reserved2                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;
 
#define MSR_IVY_BRIDGE_PPIN_CTL  0x0000004E
 
typedef union {
  struct {
    UINT32    LockOut     : 1;
    UINT32    Enable_PPIN : 1;
    UINT32    Reserved1   : 30;
    UINT32    Reserved2   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;
 
#define MSR_IVY_BRIDGE_PPIN  0x0000004F
 
#define MSR_IVY_BRIDGE_PLATFORM_INFO_1  0x000000CE
 
typedef union {
  struct {
    UINT32    Reserved1              : 8;
    UINT32    MaximumNonTurboRatio   : 8;
    UINT32    Reserved2              : 7;
    UINT32    PPIN_CAP               : 1;
    UINT32    Reserved3              : 4;
    UINT32    RatioLimit             : 1;
    UINT32    TDPLimit               : 1;
    UINT32    TJOFFSET               : 1;
    UINT32    Reserved4              : 1;
    UINT32    Reserved5              : 8;
    UINT32    MaximumEfficiencyRatio : 8;
    UINT32    Reserved6              : 16;
  } Bits;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;
 
#define MSR_IVY_BRIDGE_ERROR_CONTROL  0x0000017F
 
typedef union {
  struct {
    UINT32    Reserved1         : 1;
    UINT32    MemErrorLogEnable : 1;
    UINT32    Reserved2         : 30;
    UINT32    Reserved3         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;
 
#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET  0x000001A2
 
typedef union {
  struct {
    UINT32    Reserved1           : 16;
    UINT32    TemperatureTarget   : 8;
    UINT32    TCCActivationOffset : 4;
    UINT32    Reserved2           : 4;
    UINT32    Reserved3           : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
 
#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1  0x000001AE
 
typedef union {
  struct {
    UINT32    Maximum9C                             : 8;
    UINT32    Maximum10C                            : 8;
    UINT32    Maximum11C                            : 8;
    UINT32    Maximum12C                            : 8;
    UINT32    Maximum13C                            : 8;
    UINT32    Maximum14C                            : 8;
    UINT32    Maximum15C                            : 8;
    UINT32    Reserved                              : 7;
    UINT32    TurboRatioLimitConfigurationSemaphore : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;
 
#define MSR_IVY_BRIDGE_IA32_MC6_MISC  0x0000041B
 
typedef union {
  struct {
    UINT32    RecoverableAddressLSB   : 6;
    UINT32    AddressMode             : 3;
    UINT32    Reserved1               : 7;
    UINT32    PCIExpressRequestorID   : 16;
    UINT32    PCIExpressSegmentNumber : 8;
    UINT32    Reserved2               : 24;
  } Bits;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
 
#define MSR_IVY_BRIDGE_IA32_MC29_CTL  0x00000474
#define MSR_IVY_BRIDGE_IA32_MC30_CTL  0x00000478
#define MSR_IVY_BRIDGE_IA32_MC31_CTL  0x0000047C
 
#define MSR_IVY_BRIDGE_IA32_MC29_STATUS  0x00000475
#define MSR_IVY_BRIDGE_IA32_MC30_STATUS  0x00000479
#define MSR_IVY_BRIDGE_IA32_MC31_STATUS  0x0000047D
 
#define MSR_IVY_BRIDGE_IA32_MC29_ADDR  0x00000476
#define MSR_IVY_BRIDGE_IA32_MC30_ADDR  0x0000047A
#define MSR_IVY_BRIDGE_IA32_MC31_ADDR  0x0000047E
 
#define MSR_IVY_BRIDGE_IA32_MC29_MISC  0x00000477
#define MSR_IVY_BRIDGE_IA32_MC30_MISC  0x0000047B
#define MSR_IVY_BRIDGE_IA32_MC31_MISC  0x0000047F
 
#define MSR_IVY_BRIDGE_PKG_PERF_STATUS  0x00000613
 
#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT  0x00000618
 
#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS  0x00000619
 
#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS  0x0000061B
 
#define MSR_IVY_BRIDGE_DRAM_POWER_INFO  0x0000061C
 
#define MSR_IVY_BRIDGE_PEBS_ENABLE  0x000003F1
 
typedef union {
  struct {
    UINT32    PEBS_EN_PMC0 : 1;
    UINT32    PEBS_EN_PMC1 : 1;
    UINT32    PEBS_EN_PMC2 : 1;
    UINT32    PEBS_EN_PMC3 : 1;
    UINT32    Reserved1    : 28;
    UINT32    LL_EN_PMC0   : 1;
    UINT32    LL_EN_PMC1   : 1;
    UINT32    LL_EN_PMC2   : 1;
    UINT32    LL_EN_PMC3   : 1;
    UINT32    Reserved2    : 28;
  } Bits;
  UINT64    Uint64;
} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;
 
#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL  0x00000C00
 
#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS  0x00000C01
 
#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG  0x00000C06
 
#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS  0x00000C15
 
#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS  0x00000C35
 
#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1  0x00000D1A
 
#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1  0x00000D3A
 
#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1  0x00000D5A
 
#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1  0x00000D7A
 
#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1  0x00000D9A
 
#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1  0x00000DBA
 
#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1  0x00000DDA
 
#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1  0x00000DFA
 
#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL  0x00000E04
 
#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0  0x00000E10
 
#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1  0x00000E11
 
#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2  0x00000E12
 
#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3  0x00000E13
 
#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER  0x00000E14
 
#define MSR_IVY_BRIDGE_C8_PMON_CTR0  0x00000E16
 
#define MSR_IVY_BRIDGE_C8_PMON_CTR1  0x00000E17
 
#define MSR_IVY_BRIDGE_C8_PMON_CTR2  0x00000E18
 
#define MSR_IVY_BRIDGE_C8_PMON_CTR3  0x00000E19
 
#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1  0x00000E1A
 
#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL  0x00000E24
 
#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0  0x00000E30
 
#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1  0x00000E31
 
#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2  0x00000E32
 
#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3  0x00000E33
 
#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER  0x00000E34
 
#define MSR_IVY_BRIDGE_C9_PMON_CTR0  0x00000E36
 
#define MSR_IVY_BRIDGE_C9_PMON_CTR1  0x00000E37
 
#define MSR_IVY_BRIDGE_C9_PMON_CTR2  0x00000E38
 
#define MSR_IVY_BRIDGE_C9_PMON_CTR3  0x00000E39
 
#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1  0x00000E3A
 
#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL  0x00000E44
 
#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0  0x00000E50
 
#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1  0x00000E51
 
#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2  0x00000E52
 
#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3  0x00000E53
 
#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER  0x00000E54
 
#define MSR_IVY_BRIDGE_C10_PMON_CTR0  0x00000E56
 
#define MSR_IVY_BRIDGE_C10_PMON_CTR1  0x00000E57
 
#define MSR_IVY_BRIDGE_C10_PMON_CTR2  0x00000E58
 
#define MSR_IVY_BRIDGE_C10_PMON_CTR3  0x00000E59
 
#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1  0x00000E5A
 
#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL  0x00000E64
 
#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0  0x00000E70
 
#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1  0x00000E71
 
#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2  0x00000E72
 
#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3  0x00000E73
 
#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER  0x00000E74
 
#define MSR_IVY_BRIDGE_C11_PMON_CTR0  0x00000E76
 
#define MSR_IVY_BRIDGE_C11_PMON_CTR1  0x00000E77
 
#define MSR_IVY_BRIDGE_C11_PMON_CTR2  0x00000E78
 
#define MSR_IVY_BRIDGE_C11_PMON_CTR3  0x00000E79
 
#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1  0x00000E7A
 
#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL  0x00000E84
 
#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0  0x00000E90
 
#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1  0x00000E91
 
#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2  0x00000E92
 
#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3  0x00000E93
 
#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER  0x00000E94
 
#define MSR_IVY_BRIDGE_C12_PMON_CTR0  0x00000E96
 
#define MSR_IVY_BRIDGE_C12_PMON_CTR1  0x00000E97
 
#define MSR_IVY_BRIDGE_C12_PMON_CTR2  0x00000E98
 
#define MSR_IVY_BRIDGE_C12_PMON_CTR3  0x00000E99
 
#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1  0x00000E9A
 
#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL  0x00000EA4
 
#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0  0x00000EB0
 
#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1  0x00000EB1
 
#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2  0x00000EB2
 
#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3  0x00000EB3
 
#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER  0x00000EB4
 
#define MSR_IVY_BRIDGE_C13_PMON_CTR0  0x00000EB6
 
#define MSR_IVY_BRIDGE_C13_PMON_CTR1  0x00000EB7
 
#define MSR_IVY_BRIDGE_C13_PMON_CTR2  0x00000EB8
 
#define MSR_IVY_BRIDGE_C13_PMON_CTR3  0x00000EB9
 
#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1  0x00000EBA
 
#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL  0x00000EC4
 
#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0  0x00000ED0
 
#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1  0x00000ED1
 
#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2  0x00000ED2
 
#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3  0x00000ED3
 
#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER  0x00000ED4
 
#define MSR_IVY_BRIDGE_C14_PMON_CTR0  0x00000ED6
 
#define MSR_IVY_BRIDGE_C14_PMON_CTR1  0x00000ED7
 
#define MSR_IVY_BRIDGE_C14_PMON_CTR2  0x00000ED8
 
#define MSR_IVY_BRIDGE_C14_PMON_CTR3  0x00000ED9
 
#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1  0x00000EDA
 
#endif