PendingBreak.c

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#include "CpuCommonFeatures.h"
 
BOOLEAN
EFIAPI
PendingBreakSupport (
  IN UINTN                             ProcessorNumber,
  IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,
  IN VOID                              *ConfigData  OPTIONAL
  )
{
  if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
      IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
  {
    return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1);
  }
 
  return FALSE;
}
 
RETURN_STATUS
EFIAPI
PendingBreakInitialize (
  IN UINTN                             ProcessorNumber,
  IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,
  IN VOID                              *ConfigData   OPTIONAL,
  IN BOOLEAN                           State
  )
{
  //
  // The scope of the MSR_ATOM_IA32_MISC_ENABLE is core for below processor type, only program
  // MSR_ATOM_IA32_MISC_ENABLE for thread 0 in each core.
  //
  // Support function has check the processer type for this feature, no need to check again
  // here.
  //
  if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
    return RETURN_SUCCESS;
  }
 
  //
  // ATOM, CORE2, CORE, PENTIUM_4 and IS_PENTIUM_M_PROCESSOR have the same MSR index,
  // Simply use MSR_ATOM_IA32_MISC_ENABLE here
  //
  CPU_REGISTER_TABLE_WRITE_FIELD (
    ProcessorNumber,
    Msr,
    MSR_ATOM_IA32_MISC_ENABLE,
    MSR_ATOM_IA32_MISC_ENABLE_REGISTER,
    Bits.FERR,
    (State) ? 1 : 0
    );
  return RETURN_SUCCESS;
}