TianoCore EDK2 master
SilvermontMsr.h
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1
18#ifndef __SILVERMONT_MSR_H__
19#define __SILVERMONT_MSR_H__
20
22
32#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x37 || \
36 DisplayModel == 0x4A || \
37 DisplayModel == 0x4D || \
38 DisplayModel == 0x5A || \
39 DisplayModel == 0x5D \
40 ) \
41 )
42
60#define MSR_SILVERMONT_PLATFORM_ID 0x00000017
61
65typedef union {
69 struct {
70 UINT32 Reserved1 : 8;
75 UINT32 Reserved2 : 19;
76 UINT32 Reserved3 : 18;
80 UINT32 PlatformId : 3;
81 UINT32 Reserved4 : 11;
82 } Bits;
86 UINT64 Uint64;
88
107#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A
108
112typedef union {
116 struct {
117 UINT32 Reserved1 : 32;
118 UINT32 Reserved2 : 32;
119 } Bits;
123 UINT32 Uint32;
127 UINT64 Uint64;
129
147#define MSR_SILVERMONT_SMI_COUNT 0x00000034
148
152typedef union {
156 struct {
161 UINT32 SMICount : 32;
162 UINT32 Reserved : 32;
163 } Bits;
167 UINT32 Uint32;
171 UINT64 Uint64;
173
194#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A
195
199typedef union {
203 struct {
207 UINT32 Lock : 1;
208 UINT32 Reserved1 : 1;
213 UINT32 Reserved2 : 29;
214 UINT32 Reserved3 : 32;
215 } Bits;
219 UINT32 Uint32;
223 UINT64 Uint64;
225
254#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040
255#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041
256#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042
257#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043
258#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044
259#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045
260#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046
261#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047
263
290#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060
291#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061
292#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062
293#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063
294#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064
295#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065
296#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066
297#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067
299
318#define MSR_SILVERMONT_FSB_FREQ 0x000000CD
319
323typedef union {
327 struct {
352 UINT32 Reserved1 : 28;
353 UINT32 Reserved2 : 32;
354 } Bits;
358 UINT32 Uint32;
362 UINT64 Uint64;
364
383#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE
384
388typedef union {
392 struct {
393 UINT32 Reserved1 : 8;
400 UINT32 Reserved2 : 16;
401 UINT32 Reserved3 : 32;
402 } Bits;
406 UINT32 Uint32;
410 UINT64 Uint64;
412
433#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
434
438typedef union {
442 struct {
451 UINT32 Limit : 3;
452 UINT32 Reserved1 : 7;
458 UINT32 IO_MWAIT : 1;
459 UINT32 Reserved2 : 4;
464 UINT32 CFGLock : 1;
465 UINT32 Reserved3 : 16;
466 UINT32 Reserved4 : 32;
467 } Bits;
471 UINT32 Uint32;
475 UINT64 Uint64;
477
497#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4
498
502typedef union {
506 struct {
515 UINT32 Lvl2Base : 16;
523 UINT32 CStateRange : 3;
524 UINT32 Reserved1 : 13;
525 UINT32 Reserved2 : 32;
526 } Bits;
530 UINT32 Uint32;
534 UINT64 Uint64;
536
555#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E
556
560typedef union {
564 struct {
570 UINT32 Reserved1 : 7;
576 UINT32 L2Enabled : 1;
577 UINT32 Reserved2 : 14;
581 UINT32 L2NotPresent : 1;
582 UINT32 Reserved3 : 8;
583 UINT32 Reserved4 : 32;
584 } Bits;
588 UINT32 Uint32;
592 UINT64 Uint64;
594
614#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C
615
619typedef union {
623 struct {
634 UINT32 Reserved1 : 30;
635 UINT32 Reserved2 : 32;
636 } Bits;
640 UINT32 Uint32;
644 UINT64 Uint64;
646
666#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0
667
671typedef union {
675 struct {
679 UINT32 FastStrings : 1;
680 UINT32 Reserved1 : 2;
686 UINT32 Reserved2 : 3;
691 UINT32 Reserved3 : 3;
695 UINT32 BTS : 1;
700 UINT32 PEBS : 1;
701 UINT32 Reserved4 : 3;
706 UINT32 EIST : 1;
707 UINT32 Reserved5 : 1;
711 UINT32 MONITOR : 1;
712 UINT32 Reserved6 : 3;
721 UINT32 Reserved7 : 8;
722 UINT32 Reserved8 : 2;
726 UINT32 XD : 1;
727 UINT32 Reserved9 : 3;
740 UINT32 Reserved10 : 25;
741 } Bits;
745 UINT64 Uint64;
747
766#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2
767
771typedef union {
775 struct {
776 UINT32 Reserved1 : 16;
789 UINT32 TargetOffset : 6;
790 UINT32 Reserved2 : 2;
791 UINT32 Reserved3 : 32;
792 } Bits;
796 UINT32 Uint32;
800 UINT64 Uint64;
802
821#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4
822
826typedef union {
830 struct {
837 UINT32 Reserved1 : 1;
844 UINT32 Reserved2 : 29;
845 UINT32 Reserved3 : 32;
846 } Bits;
850 UINT32 Uint32;
854 UINT64 Uint64;
856
873#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6
874
891#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7
892
911#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD
912
916typedef union {
920 struct {
925 UINT32 Maximum1C : 8;
930 UINT32 Maximum2C : 8;
935 UINT32 Maximum3C : 8;
940 UINT32 Maximum4C : 8;
945 UINT32 Maximum5C : 8;
950 UINT32 Maximum6C : 8;
955 UINT32 Maximum7C : 8;
960 UINT32 Maximum8C : 8;
961 } Bits;
965 UINT64 Uint64;
967
987#define MSR_SILVERMONT_LBR_SELECT 0x000001C8
988
992typedef union {
996 struct {
1000 UINT32 CPL_EQ_0 : 1;
1004 UINT32 CPL_NEQ_0 : 1;
1008 UINT32 JCC : 1;
1012 UINT32 NEAR_REL_CALL : 1;
1016 UINT32 NEAR_IND_CALL : 1;
1020 UINT32 NEAR_RET : 1;
1024 UINT32 NEAR_IND_JMP : 1;
1028 UINT32 NEAR_REL_JMP : 1;
1032 UINT32 FAR_BRANCH : 1;
1033 UINT32 Reserved1 : 23;
1034 UINT32 Reserved2 : 32;
1035 } Bits;
1039 UINT32 Uint32;
1043 UINT64 Uint64;
1045
1064#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9
1065
1083#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD
1084
1103#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE
1104
1124#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1
1125
1129typedef union {
1133 struct {
1137 UINT32 PEBS : 1;
1138 UINT32 Reserved1 : 31;
1139 UINT32 Reserved2 : 32;
1140 } Bits;
1144 UINT32 Uint32;
1148 UINT64 Uint64;
1150
1170#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA
1171
1191#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD
1192
1208#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1209
1226#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491
1227
1247#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660
1248
1267#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606
1268
1272typedef union {
1276 struct {
1283 UINT32 PowerUnits : 4;
1284 UINT32 Reserved1 : 4;
1292 UINT32 Reserved2 : 3;
1297 UINT32 TimeUnits : 4;
1298 UINT32 Reserved3 : 12;
1299 UINT32 Reserved4 : 32;
1300 } Bits;
1304 UINT32 Uint32;
1308 UINT64 Uint64;
1310
1329#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610
1330
1334typedef union {
1338 struct {
1343 UINT32 Limit : 15;
1348 UINT32 Enable : 1;
1353 UINT32 ClampingLimit : 1;
1358 UINT32 Time : 7;
1359 UINT32 Reserved1 : 8;
1360 UINT32 Reserved2 : 32;
1361 } Bits;
1365 UINT32 Uint32;
1369 UINT64 Uint64;
1371
1388#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611
1389
1406#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639
1407
1425#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
1426
1445#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
1446
1465#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664
1466
1484#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E
1485
1489typedef union {
1493 struct {
1500 UINT32 ThermalSpecPower : 15;
1501 UINT32 Reserved1 : 17;
1502 UINT32 Reserved2 : 32;
1503 } Bits;
1507 UINT32 Uint32;
1511 UINT64 Uint64;
1513
1532#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638
1533
1537typedef union {
1541 struct {
1546 UINT32 Limit : 15;
1551 UINT32 Enable : 1;
1552 UINT32 Reserved1 : 1;
1563 UINT32 Time : 7;
1564 UINT32 Reserved2 : 8;
1565 UINT32 Reserved3 : 32;
1566 } Bits;
1570 UINT32 Uint32;
1574 UINT64 Uint64;
1576
1577#endif