SilvermontMsr.h

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#ifndef __SILVERMONT_MSR_H__
#define __SILVERMONT_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x37 || \
    DisplayModel == 0x4A || \
    DisplayModel == 0x4D || \
    DisplayModel == 0x5A || \
    DisplayModel == 0x5D    \
    )                       \
   )
 
#define MSR_SILVERMONT_PLATFORM_ID  0x00000017
 
typedef union {
  struct {
    UINT32    Reserved1             : 8;
    UINT32    MaximumQualifiedRatio : 5;
    UINT32    Reserved2             : 19;
    UINT32    Reserved3             : 18;
    UINT32    PlatformId            : 3;
    UINT32    Reserved4             : 11;
  } Bits;
  UINT64    Uint64;
} MSR_SILVERMONT_PLATFORM_ID_REGISTER;
 
#define MSR_SILVERMONT_EBL_CR_POWERON  0x0000002A
 
typedef union {
  struct {
    UINT32    Reserved1 : 32;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;
 
#define MSR_SILVERMONT_SMI_COUNT  0x00000034
 
typedef union {
  struct {
    UINT32    SMICount : 32;
    UINT32    Reserved : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_SMI_COUNT_REGISTER;
 
#define MSR_SILVERMONT_IA32_FEATURE_CONTROL  0x0000003A
 
typedef union {
  struct {
    UINT32    Lock                : 1;
    UINT32    Reserved1           : 1;
    UINT32    EnableVmxOutsideSmx : 1;
    UINT32    Reserved2           : 29;
    UINT32    Reserved3           : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;
 
#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP  0x00000040
#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP  0x00000041
#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP  0x00000042
#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP  0x00000043
#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP  0x00000044
#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP  0x00000045
#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP  0x00000046
#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP  0x00000047
 
#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP  0x00000060
#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP  0x00000061
#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP  0x00000062
#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP  0x00000063
#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP  0x00000064
#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP  0x00000065
#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP  0x00000066
#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP  0x00000067
 
#define MSR_SILVERMONT_FSB_FREQ  0x000000CD
 
typedef union {
  struct {
    UINT32    ScalableBusSpeed : 4;
    UINT32    Reserved1        : 28;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_FSB_FREQ_REGISTER;
 
#define MSR_SILVERMONT_PLATFORM_INFO  0x000000CE
 
typedef union {
  struct {
    UINT32    Reserved1             : 8;
    UINT32    MaximumNon_TurboRatio : 8;
    UINT32    Reserved2             : 16;
    UINT32    Reserved3             : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;
 
#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL  0x000000E2
 
typedef union {
  struct {
    UINT32    Limit     : 3;
    UINT32    Reserved1 : 7;
    UINT32    IO_MWAIT  : 1;
    UINT32    Reserved2 : 4;
    UINT32    CFGLock   : 1;
    UINT32    Reserved3 : 16;
    UINT32    Reserved4 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
 
#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE  0x000000E4
 
typedef union {
  struct {
    UINT32    Lvl2Base    : 16;
    UINT32    CStateRange : 3;
    UINT32    Reserved1   : 13;
    UINT32    Reserved2   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;
 
#define MSR_SILVERMONT_BBL_CR_CTL3  0x0000011E
 
typedef union {
  struct {
    UINT32    L2HardwareEnabled : 1;
    UINT32    Reserved1         : 7;
    UINT32    L2Enabled         : 1;
    UINT32    Reserved2         : 14;
    UINT32    L2NotPresent      : 1;
    UINT32    Reserved3         : 8;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;
 
#define MSR_SILVERMONT_FEATURE_CONFIG  0x0000013C
 
typedef union {
  struct {
    UINT32    AESConfiguration : 2;
    UINT32    Reserved1        : 30;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;
 
#define MSR_SILVERMONT_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    FastStrings                    : 1;
    UINT32    Reserved1                      : 2;
    UINT32    AutomaticThermalControlCircuit : 1;
    UINT32    Reserved2                      : 3;
    UINT32    PerformanceMonitoring          : 1;
    UINT32    Reserved3                      : 3;
    UINT32    BTS                            : 1;
    UINT32    PEBS                           : 1;
    UINT32    Reserved4                      : 3;
    UINT32    EIST                           : 1;
    UINT32    Reserved5                      : 1;
    UINT32    MONITOR                        : 1;
    UINT32    Reserved6                      : 3;
    UINT32    LimitCpuidMaxval               : 1;
    UINT32    xTPR_Message_Disable           : 1;
    UINT32    Reserved7                      : 8;
    UINT32    Reserved8                      : 2;
    UINT32    XD                             : 1;
    UINT32    Reserved9                      : 3;
    UINT32    TurboModeDisable : 1;
    UINT32    Reserved10       : 25;
  } Bits;
  UINT64    Uint64;
} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_SILVERMONT_TEMPERATURE_TARGET  0x000001A2
 
typedef union {
  struct {
    UINT32    Reserved1         : 16;
    UINT32    TemperatureTarget : 8;
    UINT32    TargetOffset      : 6;
    UINT32    Reserved2         : 2;
    UINT32    Reserved3         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;
 
#define MSR_SILVERMONT_MISC_FEATURE_CONTROL  0x000001A4
 
typedef union {
  struct {
    UINT32    L2HardwarePrefetcherDisable  : 1;
    UINT32    Reserved1                    : 1;
    UINT32    DCUHardwarePrefetcherDisable : 1;
    UINT32    Reserved2                    : 29;
    UINT32    Reserved3                    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;
 
#define MSR_SILVERMONT_OFFCORE_RSP_0  0x000001A6
 
#define MSR_SILVERMONT_OFFCORE_RSP_1  0x000001A7
 
#define MSR_SILVERMONT_TURBO_RATIO_LIMIT  0x000001AD
 
typedef union {
  struct {
    UINT32    Maximum1C : 8;
    UINT32    Maximum2C : 8;
    UINT32    Maximum3C : 8;
    UINT32    Maximum4C : 8;
    UINT32    Maximum5C : 8;
    UINT32    Maximum6C : 8;
    UINT32    Maximum7C : 8;
    UINT32    Maximum8C : 8;
  } Bits;
  UINT64    Uint64;
} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;
 
#define MSR_SILVERMONT_LBR_SELECT  0x000001C8
 
typedef union {
  struct {
    UINT32    CPL_EQ_0      : 1;
    UINT32    CPL_NEQ_0     : 1;
    UINT32    JCC           : 1;
    UINT32    NEAR_REL_CALL : 1;
    UINT32    NEAR_IND_CALL : 1;
    UINT32    NEAR_RET      : 1;
    UINT32    NEAR_IND_JMP  : 1;
    UINT32    NEAR_REL_JMP  : 1;
    UINT32    FAR_BRANCH    : 1;
    UINT32    Reserved1     : 23;
    UINT32    Reserved2     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_LBR_SELECT_REGISTER;
 
#define MSR_SILVERMONT_LASTBRANCH_TOS  0x000001C9
 
#define MSR_SILVERMONT_LER_FROM_LIP  0x000001DD
 
#define MSR_SILVERMONT_LER_TO_LIP  0x000001DE
 
#define MSR_SILVERMONT_PEBS_ENABLE  0x000003F1
 
typedef union {
  struct {
    UINT32    PEBS      : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;
 
#define MSR_SILVERMONT_PKG_C6_RESIDENCY  0x000003FA
 
#define MSR_SILVERMONT_CORE_C6_RESIDENCY  0x000003FD
 
#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM  0x0000048C
 
#define MSR_SILVERMONT_IA32_VMX_FMFUNC  0x00000491
 
#define MSR_SILVERMONT_CORE_C1_RESIDENCY  0x00000660
 
#define MSR_SILVERMONT_RAPL_POWER_UNIT  0x00000606
 
typedef union {
  struct {
    UINT32    PowerUnits        : 4;
    UINT32    Reserved1         : 4;
    UINT32    EnergyStatusUnits : 5;
    UINT32    Reserved2         : 3;
    UINT32    TimeUnits         : 4;
    UINT32    Reserved3         : 12;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;
 
#define MSR_SILVERMONT_PKG_POWER_LIMIT  0x00000610
 
typedef union {
  struct {
    UINT32    Limit         : 15;
    UINT32    Enable        : 1;
    UINT32    ClampingLimit : 1;
    UINT32    Time          : 7;
    UINT32    Reserved1     : 8;
    UINT32    Reserved2     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;
 
#define MSR_SILVERMONT_PKG_ENERGY_STATUS  0x00000611
 
#define MSR_SILVERMONT_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG  0x00000668
 
#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG  0x00000669
 
#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER  0x00000664
 
#define MSR_SILVERMONT_PKG_POWER_INFO  0x0000066E
 
typedef union {
  struct {
    UINT32    ThermalSpecPower : 15;
    UINT32    Reserved1        : 17;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;
 
#define MSR_SILVERMONT_PP0_POWER_LIMIT  0x00000638
 
typedef union {
  struct {
    UINT32    Limit     : 15;
    UINT32    Enable    : 1;
    UINT32    Reserved1 : 1;
    UINT32    Time      : 7;
    UINT32    Reserved2 : 8;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;
 
#endif