TianoCore EDK2
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MADT_GENERATOR_REVISION :
MadtGenerator.c
Main :
VariableLockRequestToLockUnitTest.c
MAJOR_REVISION_BIT_SHIFT :
TableGenerator.h
MAJOR_REVISION_MASK :
TableGenerator.h
MAX :
Base.h
MAX_2_BITS :
ProcessorBind.h
MAX_AARCH64_EXCEPTION :
DebugSupport.h
MAX_ACPI_TABLE_PARSERS :
AcpiTableParser.h
MAX_ADDRESS :
ProcessorBind.h
MAX_ALLOC_ADDRESS :
ProcessorBind.h
MAX_AML_NAMESTRING_SIZE :
AmlDefines.h
MAX_ARM_EXCEPTION :
DebugSupport.h
MAX_ASL_NAMESTRING_SIZE :
AmlDefines.h
MAX_BIT :
ProcessorBind.h
MAX_CHAR :
BootOption.c
,
FileExplorer.h
MAX_CMN600_DEVICES_SUPPORTED :
SsdtCmn600Generator.h
MAX_DEBUG_MESSAGE_LENGTH :
DebugLibPosix.c
MAX_DTC_COUNT :
SsdtCmn600Generator.h
MAX_EBC_EXCEPTION :
DebugSupport.h
MAX_EEPROM_LEN :
UefiPxe.h
MAX_EXTENDED_DATA_SIZE :
StatusCodeDataTypeDebug.h
MAX_FILE_NAME_LEN :
AcpiView.h
MAX_FLASH_DEVICES :
NorFlashKvmtool.c
MAX_INT8 :
Base.h
MAX_INTN :
ProcessorBind.h
MAX_NODE_COUNT :
SsdtCpuTopologyGenerator.h
MAX_PCC_SUBSPACES :
PcctParser.h
MAX_PCI_CONFIG_LEN :
UefiPxe.h
MAX_PCI_ROOT_COMPLEXES_SUPPORTED :
SsdtPcieGenerator.h
MAX_SERIAL_PORTS_SUPPORTED :
SsdtSerialPortGenerator.c
MAX_SIGNATURE_SIZE :
CryptPkcs7Sign.c
MAX_TLS_SESSION_ID_LENGTH :
Tls.h
MAX_TOPA_ENTRY_COUNT :
ProcTrace.c
MAX_UINTN :
ProcessorBind.h
MAX_XMIT_BUFFERS :
UefiPxe.h
MAXIMUM_DISPLAYCOUNT :
Dp.h
MAXIMUM_VALUE_CHARACTERS :
PrintLib.h
MBEDTLS_AES_C :
mbedtls_config.h
MBEDTLS_ALLOW_PRIVATE_ACCESS :
mbedtls_config.h
MBEDTLS_ASN1_PARSE_C :
mbedtls_config.h
MBEDTLS_ASN1_WRITE_C :
mbedtls_config.h
MBEDTLS_BASE64_C :
mbedtls_config.h
MBEDTLS_BIGNUM_C :
mbedtls_config.h
MBEDTLS_CHACHA20_C :
mbedtls_config.h
MBEDTLS_CHACHAPOLY_C :
mbedtls_config.h
MBEDTLS_CIPHER_C :
mbedtls_config.h
MBEDTLS_CIPHER_MODE_CBC :
mbedtls_config.h
MBEDTLS_CTR_DRBG_C :
mbedtls_config.h
MBEDTLS_DHM_C :
mbedtls_config.h
MBEDTLS_ECDH_C :
mbedtls_config.h
MBEDTLS_ECDSA_C :
mbedtls_config.h
MBEDTLS_ECP_C :
mbedtls_config.h
MBEDTLS_ECP_NIST_OPTIM :
mbedtls_config.h
MBEDTLS_ECP_RESTARTABLE :
mbedtls_config.h
MBEDTLS_ENTROPY_C :
mbedtls_config.h
MBEDTLS_ERROR_C :
mbedtls_config.h
MBEDTLS_ERROR_STRERROR_DUMMY :
mbedtls_config.h
MBEDTLS_GCM_C :
mbedtls_config.h
MBEDTLS_GENPRIME :
mbedtls_config.h
MBEDTLS_HAVE_ASM :
mbedtls_config.h
MBEDTLS_HAVE_TIME :
mbedtls_config.h
MBEDTLS_HKDF_C :
mbedtls_config.h
MBEDTLS_HMAC_DRBG_C :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_PSK_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_RSA_ENABLED :
mbedtls_config.h
MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED :
mbedtls_config.h
MBEDTLS_MD5_C :
mbedtls_config.h
MBEDTLS_MD_C :
mbedtls_config.h
MBEDTLS_NET_C :
mbedtls_config.h
MBEDTLS_NO_UDBL_DIVISION :
mbedtls_config.h
MBEDTLS_OID_C :
mbedtls_config.h
MBEDTLS_OID_PKCS7 :
CryptPkcs7Internal.h
MBEDTLS_PEM_PARSE_C :
mbedtls_config.h
MBEDTLS_PEM_WRITE_C :
mbedtls_config.h
MBEDTLS_PK_C :
mbedtls_config.h
MBEDTLS_PK_PARSE_C :
mbedtls_config.h
MBEDTLS_PK_WRITE_C :
mbedtls_config.h
MBEDTLS_PKCS1_V15 :
mbedtls_config.h
MBEDTLS_PKCS1_V21 :
mbedtls_config.h
MBEDTLS_PKCS5_C :
mbedtls_config.h
MBEDTLS_PKCS7_C :
mbedtls_config.h
MBEDTLS_PLATFORM_C :
mbedtls_config.h
MBEDTLS_PLATFORM_MEMORY :
mbedtls_config.h
MBEDTLS_PLATFORM_NO_STD_FUNCTIONS :
mbedtls_config.h
MBEDTLS_POLY1305_C :
mbedtls_config.h
MBEDTLS_RSA_C :
mbedtls_config.h
MBEDTLS_SHA1_C :
mbedtls_config.h
MBEDTLS_SHA224_C :
mbedtls_config.h
MBEDTLS_SHA256_C :
mbedtls_config.h
MBEDTLS_SHA256_SMALLER :
mbedtls_config.h
MBEDTLS_SHA384_C :
mbedtls_config.h
MBEDTLS_SHA512_C :
mbedtls_config.h
MBEDTLS_SHA512_SMALLER :
mbedtls_config.h
MBEDTLS_SSL_ALL_ALERT_MESSAGES :
mbedtls_config.h
MBEDTLS_SSL_ALPN :
mbedtls_config.h
MBEDTLS_SSL_CACHE_C :
mbedtls_config.h
MBEDTLS_SSL_CLI_C :
mbedtls_config.h
MBEDTLS_SSL_CONTEXT_SERIALIZATION :
mbedtls_config.h
MBEDTLS_SSL_COOKIE_C :
mbedtls_config.h
MBEDTLS_SSL_DTLS_CONNECTION_ID :
mbedtls_config.h
MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT :
mbedtls_config.h
MBEDTLS_SSL_ENCRYPT_THEN_MAC :
mbedtls_config.h
MBEDTLS_SSL_EXTENDED_MASTER_SECRET :
mbedtls_config.h
MBEDTLS_SSL_KEEP_PEER_CERTIFICATE :
mbedtls_config.h
MBEDTLS_SSL_MAX_EARLY_DATA_SIZE :
mbedtls_config.h
MBEDTLS_SSL_MAX_FRAGMENT_LENGTH :
mbedtls_config.h
MBEDTLS_SSL_PROTO_DTLS :
mbedtls_config.h
MBEDTLS_SSL_PROTO_TLS1_2 :
mbedtls_config.h
MBEDTLS_SSL_RENEGOTIATION :
mbedtls_config.h
MBEDTLS_SSL_SERVER_NAME_INDICATION :
mbedtls_config.h
MBEDTLS_SSL_SESSION_TICKETS :
mbedtls_config.h
MBEDTLS_SSL_SRV_C :
mbedtls_config.h
MBEDTLS_SSL_TICKET_C :
mbedtls_config.h
MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS :
mbedtls_config.h
MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED :
mbedtls_config.h
MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED :
mbedtls_config.h
MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED :
mbedtls_config.h
MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE :
mbedtls_config.h
MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH :
mbedtls_config.h
MBEDTLS_SSL_TLS_C :
mbedtls_config.h
MBEDTLS_VERSION_C :
mbedtls_config.h
MBEDTLS_X509_CREATE_C :
mbedtls_config.h
MBEDTLS_X509_CRL_PARSE_C :
mbedtls_config.h
MBEDTLS_X509_CRT_PARSE_C :
mbedtls_config.h
MBEDTLS_X509_CRT_WRITE_C :
mbedtls_config.h
MBEDTLS_X509_CSR_PARSE_C :
mbedtls_config.h
MBEDTLS_X509_CSR_WRITE_C :
mbedtls_config.h
MBEDTLS_X509_RSASSA_PSS_SUPPORT :
mbedtls_config.h
MBEDTLS_X509_USE_C :
mbedtls_config.h
MCFG_GENERATOR_REVISION :
McfgGenerator.c
MCTP_BASELINE_MINIMUM_UNIT_TRANSMISSION_SIZE :
Mctp.h
MCTP_CONTROL_COMPLETION_CODES_SUCCESS :
Mctp.h
MCTP_CONTROL_RESERVED :
Mctp.h
MCTP_MESSAGE_TYPE_CONTROL :
Mctp.h
MCTP_NULL_DESTINATION_ENDPOINT_ID :
Mctp.h
MD5_DIGEST_SIZE :
BaseCryptLib.h
MDE_CPU_AARCH64 :
ProcessorBind.h
MDE_CPU_ARM :
ProcessorBind.h
MDE_CPU_EBC :
ProcessorBind.h
MDE_CPU_IA32 :
ProcessorBind.h
MDE_CPU_RISCV64 :
ProcessorBind.h
MDE_CPU_X64 :
ProcessorBind.h
MEDIA_CDROM_DP :
DevicePath.h
MEDIA_FILEPATH_DP :
DevicePath.h
MEDIA_HARDDRIVE_DP :
DevicePath.h
MEDIA_PIWG_FW_FILE_DP :
DevicePath.h
MEDIA_PIWG_FW_VOL_DP :
DevicePath.h
MEDIA_PROTOCOL_DP :
DevicePath.h
MEDIA_RAM_DISK_DP :
DevicePath.h
MEDIA_RELATIVE_OFFSET_RANGE_DP :
DevicePath.h
MEDIA_VENDOR_DP :
DevicePath.h
MEMORY_ADDRESS_SIZE_LIMIT :
ConfigurationManager.h
MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME :
MemoryOverwriteControl.h
MEMORY_STATUS_CODE_RECORD_GUID :
MemoryStatusCodeRecord.h
MESSAGING_DEVICE_PATH :
DevicePath.h
MFI_SCSI_IO_TYPE_A :
ScsiIo.h
MFI_SCSI_IO_TYPE_B :
ScsiIo.h
MFI_SCSI_IO_TYPE_BRIDGE :
ScsiIo.h
MFI_SCSI_IO_TYPE_OCRW :
ScsiIo.h
MFI_SCSI_IO_TYPE_OSD :
ScsiIo.h
MFI_SCSI_IO_TYPE_RAID :
ScsiIo.h
MFI_SCSI_IO_TYPE_RBC :
ScsiIo.h
MFI_SCSI_IO_TYPE_SES :
ScsiIo.h
MIN :
Base.h
MIN_EXT_PCC_SUBSPACE_MEM_RANGE_LEN :
PcctParser.h
MIN_INT8 :
Base.h
MIN_INTN :
ProcessorBind.h
MIN_MEMORY_RANGE_LENGTH :
PcctParser.h
MIN_UART_ADDRESS_LENGTH :
SsdtSerialPortFixupLib.c
MINOR_REVISION_MASK :
TableGenerator.h
MM_ACPI_S3_ENABLE_HOB_GUID :
MmAcpiS3Enable.h
MM_COMM_BUFFER_HOB_GUID :
MmCommBuffer.h
MM_CPU_OFFSET :
IntelMmSaveState.c
MM_CPU_SYNC_CONFIG_HOB_GUID :
MmCpuSyncConfig.h
MM_MMST_SIGNATURE :
PiMmCis.h
MM_PROFILE_DATA_HOB_GUID :
MmProfileData.h
MM_RESOURCE_ATTRIBUTE_LOGGING :
MmProfileData.h
MM_UNBLOCK_REGION_HOB_GUID :
MmUnblockRegion.h
MOR_CLEAR_MEMORY_BIT_MASK :
MemoryOverwriteControl.h
MOR_CLEAR_MEMORY_BIT_OFFSET :
MemoryOverwriteControl.h
MOR_CLEAR_MEMORY_VALUE :
MemoryOverwriteControl.h
MOR_DISABLE_AUTO_DETECT_VALUE :
MemoryOverwriteControl.h
MOR_DISABLEAUTODETECT_BIT_MASK :
MemoryOverwriteControl.h
MSG_1394_DP :
DevicePath.h
MSG_ATAPI_DP :
DevicePath.h
MSG_BLUETOOTH_DP :
DevicePath.h
MSG_BLUETOOTH_LE_DP :
DevicePath.h
MSG_DEVICE_LOGICAL_UNIT_DP :
DevicePath.h
MSG_DNS_DP :
DevicePath.h
MSG_EMMC_DP :
DevicePath.h
MSG_FIBRECHANNEL_DP :
DevicePath.h
MSG_FIBRECHANNELEX_DP :
DevicePath.h
MSG_I2O_DP :
DevicePath.h
MSG_INFINIBAND_DP :
DevicePath.h
MSG_IPv4_DP :
DevicePath.h
MSG_IPv6_DP :
DevicePath.h
MSG_ISCSI_DP :
DevicePath.h
MSG_MAC_ADDR_DP :
DevicePath.h
MSG_NVME_NAMESPACE_DP :
DevicePath.h
MSG_NVME_OF_NAMESPACE_DP :
DevicePath.h
MSG_SASEX_DP :
DevicePath.h
MSG_SATA_DP :
DevicePath.h
MSG_SCSI_DP :
DevicePath.h
MSG_SD_DP :
DevicePath.h
MSG_UART_DP :
DevicePath.h
MSG_UFS_DP :
DevicePath.h
MSG_URI_DP :
DevicePath.h
MSG_USB_CLASS_DP :
DevicePath.h
MSG_USB_DP :
DevicePath.h
MSG_USB_WWID_DP :
DevicePath.h
MSG_VLAN_DP :
DevicePath.h
MSG_WIFI_DP :
DevicePath.h
MSR_ATOM_BBL_CR_CTL3 :
AtomMsr.h
MSR_ATOM_EBL_CR_POWERON :
AtomMsr.h
MSR_ATOM_FSB_FREQ :
AtomMsr.h
MSR_ATOM_IA32_MISC_ENABLE :
AtomMsr.h
MSR_ATOM_LASTBRANCH_0_FROM_IP :
AtomMsr.h
MSR_ATOM_LASTBRANCH_0_TO_IP :
AtomMsr.h
MSR_ATOM_LASTBRANCH_TOS :
AtomMsr.h
MSR_ATOM_LER_FROM_LIP :
AtomMsr.h
MSR_ATOM_LER_TO_LIP :
AtomMsr.h
MSR_ATOM_PEBS_ENABLE :
AtomMsr.h
MSR_ATOM_PERF_STATUS :
AtomMsr.h
MSR_ATOM_PKG_C2_RESIDENCY :
AtomMsr.h
MSR_ATOM_PKG_C4_RESIDENCY :
AtomMsr.h
MSR_ATOM_PKG_C6_RESIDENCY :
AtomMsr.h
MSR_ATOM_PLATFORM_ID :
AtomMsr.h
MSR_ATOM_THERM2_CTL :
AtomMsr.h
MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS :
BroadwellMsr.h
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT :
BroadwellMsr.h
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL :
BroadwellMsr.h
MSR_BROADWELL_PP0_ENERGY_STATUS :
BroadwellMsr.h
MSR_BROADWELL_TURBO_RATIO_LIMIT :
BroadwellMsr.h
MSR_CORE2_EBL_CR_POWERON :
Core2Msr.h
MSR_CORE2_EMON_L3_CTR_CTL0 :
Core2Msr.h
MSR_CORE2_EMON_L3_GL_CTL :
Core2Msr.h
MSR_CORE2_FEATURE_CONTROL :
Core2Msr.h
MSR_CORE2_FSB_FREQ :
Core2Msr.h
MSR_CORE2_IA32_MISC_ENABLE :
Core2Msr.h
MSR_CORE2_LASTBRANCH_0_FROM_IP :
Core2Msr.h
MSR_CORE2_LASTBRANCH_0_TO_IP :
Core2Msr.h
MSR_CORE2_LASTBRANCH_TOS :
Core2Msr.h
MSR_CORE2_LER_FROM_LIP :
Core2Msr.h
MSR_CORE2_LER_TO_LIP :
Core2Msr.h
MSR_CORE2_PEBS_ENABLE :
Core2Msr.h
MSR_CORE2_PERF_CAPABILITIES :
Core2Msr.h
MSR_CORE2_PERF_FIXED_CTR0 :
Core2Msr.h
MSR_CORE2_PERF_FIXED_CTR_CTRL :
Core2Msr.h
MSR_CORE2_PERF_GLOBAL_CTRL :
Core2Msr.h
MSR_CORE2_PERF_GLOBAL_OVF_CTRL :
Core2Msr.h
MSR_CORE2_PERF_GLOBAL_STATUS :
Core2Msr.h
MSR_CORE2_PERF_STATUS :
Core2Msr.h
MSR_CORE2_PLATFORM_ID :
Core2Msr.h
MSR_CORE2_SMRR_PHYSBASE :
Core2Msr.h
MSR_CORE2_SMRR_PHYSMASK :
Core2Msr.h
MSR_CORE2_THERM2_CTL :
Core2Msr.h
MSR_CORE_BBL_CR_CTL3 :
CoreMsr.h
MSR_CORE_EBL_CR_POWERON :
CoreMsr.h
MSR_CORE_FSB_FREQ :
CoreMsr.h
MSR_CORE_IA32_EFER :
CoreMsr.h
MSR_CORE_IA32_MISC_ENABLE :
CoreMsr.h
MSR_CORE_LASTBRANCH_0 :
CoreMsr.h
MSR_CORE_LASTBRANCH_TOS :
CoreMsr.h
MSR_CORE_LER_FROM_LIP :
CoreMsr.h
MSR_CORE_LER_TO_LIP :
CoreMsr.h
MSR_CORE_MC3_ADDR :
CoreMsr.h
MSR_CORE_MC3_MISC :
CoreMsr.h
MSR_CORE_MC4_ADDR :
CoreMsr.h
MSR_CORE_MC4_CTL :
CoreMsr.h
MSR_CORE_MC4_STATUS :
CoreMsr.h
MSR_CORE_MC5_ADDR :
CoreMsr.h
MSR_CORE_MC5_CTL :
CoreMsr.h
MSR_CORE_MC5_MISC :
CoreMsr.h
MSR_CORE_MC5_STATUS :
CoreMsr.h
MSR_CORE_MTRRFIX16K_80000 :
CoreMsr.h
MSR_CORE_MTRRFIX16K_A0000 :
CoreMsr.h
MSR_CORE_MTRRFIX4K_C0000 :
CoreMsr.h
MSR_CORE_MTRRFIX4K_C8000 :
CoreMsr.h
MSR_CORE_MTRRFIX4K_D0000 :
CoreMsr.h
MSR_CORE_MTRRFIX4K_D8000 :
CoreMsr.h
MSR_CORE_MTRRFIX4K_E0000 :
CoreMsr.h
MSR_CORE_MTRRFIX4K_E8000 :
CoreMsr.h
MSR_CORE_MTRRFIX4K_F0000 :
CoreMsr.h
MSR_CORE_MTRRFIX4K_F8000 :
CoreMsr.h
MSR_CORE_MTRRFIX64K_00000 :
CoreMsr.h
MSR_CORE_MTRRPHYSBASE0 :
CoreMsr.h
MSR_CORE_MTRRPHYSMASK0 :
CoreMsr.h
MSR_CORE_P5_MC_ADDR :
CoreMsr.h
MSR_CORE_P5_MC_TYPE :
CoreMsr.h
MSR_CORE_THERM2_CTL :
CoreMsr.h
MSR_GOLDMONT_CORE_C3_RESIDENCY :
GoldmontMsr.h
MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS :
GoldmontMsr.h
MSR_GOLDMONT_DRAM_ENERGY_STATUS :
GoldmontMsr.h
MSR_GOLDMONT_DRAM_PERF_STATUS :
GoldmontMsr.h
MSR_GOLDMONT_DRAM_POWER_INFO :
GoldmontMsr.h
MSR_GOLDMONT_DRAM_POWER_LIMIT :
GoldmontMsr.h
MSR_GOLDMONT_FEATURE_CONTROL :
GoldmontMsr.h
MSR_GOLDMONT_IA32_L2_QOS_MASK_0 :
GoldmontMsr.h
MSR_GOLDMONT_IA32_L2_QOS_MASK_3 :
GoldmontMsr.h
MSR_GOLDMONT_IA32_MISC_ENABLE :
GoldmontMsr.h
MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET :
GoldmontMsr.h
MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET :
GoldmontMsr.h
MSR_GOLDMONT_IA32_PQR_ASSOC :
GoldmontMsr.h
MSR_GOLDMONT_LASTBRANCH_0_FROM_IP :
GoldmontMsr.h
MSR_GOLDMONT_LASTBRANCH_0_TO_IP :
GoldmontMsr.h
MSR_GOLDMONT_LASTBRANCH_TOS :
GoldmontMsr.h
MSR_GOLDMONT_LBR_SELECT :
GoldmontMsr.h
MSR_GOLDMONT_MISC_FEATURE_CONTROL :
GoldmontMsr.h
MSR_GOLDMONT_MISC_PWR_MGMT :
GoldmontMsr.h
MSR_GOLDMONT_PEBS_ENABLE :
GoldmontMsr.h
MSR_GOLDMONT_PKG_C10_RESIDENCY :
GoldmontMsr.h
MSR_GOLDMONT_PKG_C2_RESIDENCY :
GoldmontMsr.h
MSR_GOLDMONT_PKG_C3_RESIDENCY :
GoldmontMsr.h
MSR_GOLDMONT_PKG_C6_RESIDENCY :
GoldmontMsr.h
MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL :
GoldmontMsr.h
MSR_GOLDMONT_PKG_ENERGY_STATUS :
GoldmontMsr.h
MSR_GOLDMONT_PKG_PERF_STATUS :
GoldmontMsr.h
MSR_GOLDMONT_PKG_POWER_INFO :
GoldmontMsr.h
MSR_GOLDMONT_PKG_POWER_LIMIT :
GoldmontMsr.h
MSR_GOLDMONT_PKGC3_IRTL :
GoldmontMsr.h
MSR_GOLDMONT_PKGC_IRTL1 :
GoldmontMsr.h
MSR_GOLDMONT_PKGC_IRTL2 :
GoldmontMsr.h
MSR_GOLDMONT_PLATFORM_INFO :
GoldmontMsr.h
MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP :
GoldmontPlusMsr.h
MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP :
GoldmontPlusMsr.h
MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 :
GoldmontPlusMsr.h
MSR_GOLDMONT_PLUS_PEBS_ENABLE :
GoldmontPlusMsr.h
MSR_GOLDMONT_POWER_CTL :
GoldmontMsr.h
MSR_GOLDMONT_PP0_ENERGY_STATUS :
GoldmontMsr.h
MSR_GOLDMONT_PP1_ENERGY_STATUS :
GoldmontMsr.h
MSR_GOLDMONT_RAPL_POWER_UNIT :
GoldmontMsr.h
MSR_GOLDMONT_SGXOWNEREPOCH0 :
GoldmontMsr.h
MSR_GOLDMONT_SGXOWNEREPOCH1 :
GoldmontMsr.h
MSR_GOLDMONT_SMM_BLOCKED :
GoldmontMsr.h
MSR_GOLDMONT_SMM_DELAYED :
GoldmontMsr.h
MSR_GOLDMONT_SMM_FEATURE_CONTROL :
GoldmontMsr.h
MSR_GOLDMONT_SMM_MCA_CAP :
GoldmontMsr.h
MSR_GOLDMONT_TURBO_ACTIVATION_RATIO :
GoldmontMsr.h
MSR_GOLDMONT_TURBO_GROUP_CORECNT :
GoldmontMsr.h
MSR_GOLDMONT_TURBO_RATIO_LIMIT :
GoldmontMsr.h
MSR_HASWELL_CONFIG_TDP_CONTROL :
HaswellMsr.h
MSR_HASWELL_CONFIG_TDP_LEVEL1 :
HaswellMsr.h
MSR_HASWELL_CONFIG_TDP_LEVEL2 :
HaswellMsr.h
MSR_HASWELL_CONFIG_TDP_NOMINAL :
HaswellMsr.h
MSR_HASWELL_CORE_PERF_LIMIT_REASONS :
HaswellMsr.h
MSR_HASWELL_DRAM_ENERGY_STATUS :
HaswellMsr.h
MSR_HASWELL_DRAM_PERF_STATUS :
HaswellMsr.h
MSR_HASWELL_E_C0_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C0_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C10_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C11_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C12_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C13_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_BOX_FILTER :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C14_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C15_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C16_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C17_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C1_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C2_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C3_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C4_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C5_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C6_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C7_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C8_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_BOX_FILTER0 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_BOX_FILTER1 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_C9_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS :
HaswellEMsr.h
MSR_HASWELL_E_CORE_THREAD_COUNT :
HaswellEMsr.h
MSR_HASWELL_E_DRAM_ENERGY_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_DRAM_PERF_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_DRAM_POWER_INFO :
HaswellEMsr.h
MSR_HASWELL_E_DRAM_POWER_LIMIT :
HaswellEMsr.h
MSR_HASWELL_E_ERROR_CONTROL :
HaswellEMsr.h
MSR_HASWELL_E_IA32_MCG_CAP :
HaswellEMsr.h
MSR_HASWELL_E_IA32_PQR_ASSOC :
HaswellEMsr.h
MSR_HASWELL_E_IA32_QM_EVTSEL :
HaswellEMsr.h
MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT :
HaswellEMsr.h
MSR_HASWELL_E_PCIE_PLL_RATIO :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_BOX_FILTER :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_PCU_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL :
HaswellEMsr.h
MSR_HASWELL_E_PMON_GLOBAL_CONFIG :
HaswellEMsr.h
MSR_HASWELL_E_PMON_GLOBAL_CTL :
HaswellEMsr.h
MSR_HASWELL_E_PMON_GLOBAL_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_PP0_ENERGY_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_RAPL_POWER_UNIT :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_BOX_FILTER :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_S0_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_BOX_FILTER :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_S1_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_BOX_FILTER :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_S2_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_BOX_CTL :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_BOX_FILTER :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_CTR2 :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_CTR3 :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_EVNTSEL2 :
HaswellEMsr.h
MSR_HASWELL_E_S3_PMON_EVNTSEL3 :
HaswellEMsr.h
MSR_HASWELL_E_SMM_MCA_CAP :
HaswellEMsr.h
MSR_HASWELL_E_THREAD_ID_INFO :
HaswellEMsr.h
MSR_HASWELL_E_TURBO_RATIO_LIMIT :
HaswellEMsr.h
MSR_HASWELL_E_TURBO_RATIO_LIMIT1 :
HaswellEMsr.h
MSR_HASWELL_E_TURBO_RATIO_LIMIT2 :
HaswellEMsr.h
MSR_HASWELL_E_U_PMON_BOX_STATUS :
HaswellEMsr.h
MSR_HASWELL_E_U_PMON_CTR0 :
HaswellEMsr.h
MSR_HASWELL_E_U_PMON_CTR1 :
HaswellEMsr.h
MSR_HASWELL_E_U_PMON_EVNTSEL0 :
HaswellEMsr.h
MSR_HASWELL_E_U_PMON_EVNTSEL1 :
HaswellEMsr.h
MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL :
HaswellEMsr.h
MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR :
HaswellEMsr.h
MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS :
HaswellMsr.h
MSR_HASWELL_IA32_PERFEVTSEL0 :
HaswellMsr.h
MSR_HASWELL_IA32_PERFEVTSEL2 :
HaswellMsr.h
MSR_HASWELL_LBR_SELECT :
HaswellMsr.h
MSR_HASWELL_PKG_C10_RESIDENCY :
HaswellMsr.h
MSR_HASWELL_PKG_C8_RESIDENCY :
HaswellMsr.h
MSR_HASWELL_PKG_C9_RESIDENCY :
HaswellMsr.h
MSR_HASWELL_PKG_CST_CONFIG_CONTROL :
HaswellMsr.h
MSR_HASWELL_PKG_PERF_STATUS :
HaswellMsr.h
MSR_HASWELL_PKGC_IRTL1 :
HaswellMsr.h
MSR_HASWELL_PKGC_IRTL2 :
HaswellMsr.h
MSR_HASWELL_PLATFORM_INFO :
HaswellMsr.h
MSR_HASWELL_PP0_ENERGY_STATUS :
HaswellMsr.h
MSR_HASWELL_PP1_ENERGY_STATUS :
HaswellMsr.h
MSR_HASWELL_PP1_POLICY :
HaswellMsr.h
MSR_HASWELL_PP1_POWER_LIMIT :
HaswellMsr.h
MSR_HASWELL_RAPL_POWER_UNIT :
HaswellMsr.h
MSR_HASWELL_RING_PERF_LIMIT_REASONS :
HaswellMsr.h
MSR_HASWELL_SMM_BLOCKED :
HaswellMsr.h
MSR_HASWELL_SMM_DELAYED :
HaswellMsr.h
MSR_HASWELL_SMM_FEATURE_CONTROL :
HaswellMsr.h
MSR_HASWELL_SMM_MCA_CAP :
HaswellMsr.h
MSR_HASWELL_TURBO_ACTIVATION_RATIO :
HaswellMsr.h
MSR_HASWELL_TURBO_RATIO_LIMIT :
HaswellMsr.h
MSR_HASWELL_UNC_ARB_PERFCTR0 :
HaswellMsr.h
MSR_HASWELL_UNC_ARB_PERFCTR1 :
HaswellMsr.h
MSR_HASWELL_UNC_ARB_PERFEVTSEL0 :
HaswellMsr.h
MSR_HASWELL_UNC_ARB_PERFEVTSEL1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_0_PERFCTR0 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_0_PERFCTR1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_1_PERFCTR0 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_1_PERFCTR1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_2_PERFCTR0 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_2_PERFCTR1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_3_PERFCTR0 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_3_PERFCTR1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 :
HaswellMsr.h
MSR_HASWELL_UNC_CBO_CONFIG :
HaswellMsr.h
MSR_HASWELL_UNC_PERF_FIXED_CTR :
HaswellMsr.h
MSR_HASWELL_UNC_PERF_FIXED_CTRL :
HaswellMsr.h
MSR_HASWELL_UNC_PERF_GLOBAL_CTRL :
HaswellMsr.h
MSR_HASWELL_UNC_PERF_GLOBAL_STATUS :
HaswellMsr.h
MSR_IA32_A_PMC0 :
ArchitecturalMsr.h
MSR_IA32_APERF :
ArchitecturalMsr.h
MSR_IA32_APIC_BASE :
ArchitecturalMsr.h
MSR_IA32_BIOS_SIGN_ID :
ArchitecturalMsr.h
MSR_IA32_BIOS_UPDT_TRIG :
ArchitecturalMsr.h
MSR_IA32_BNDCFGS :
ArchitecturalMsr.h
MSR_IA32_CLOCK_MODULATION :
ArchitecturalMsr.h
MSR_IA32_CPU_DCA_CAP :
ArchitecturalMsr.h
MSR_IA32_CSTAR :
ArchitecturalMsr.h
MSR_IA32_DCA_0_CAP :
ArchitecturalMsr.h
MSR_IA32_DEBUG_INTERFACE :
ArchitecturalMsr.h
MSR_IA32_DEBUGCTL :
ArchitecturalMsr.h
MSR_IA32_DS_AREA :
ArchitecturalMsr.h
MSR_IA32_EFER :
ArchitecturalMsr.h
MSR_IA32_ENERGY_PERF_BIAS :
ArchitecturalMsr.h
MSR_IA32_FEATURE_CONTROL :
ArchitecturalMsr.h
MSR_IA32_FIXED_CTR0 :
ArchitecturalMsr.h
MSR_IA32_FIXED_CTR1 :
ArchitecturalMsr.h
MSR_IA32_FIXED_CTR2 :
ArchitecturalMsr.h
MSR_IA32_FIXED_CTR_CTRL :
ArchitecturalMsr.h
MSR_IA32_FMASK :
ArchitecturalMsr.h
MSR_IA32_FS_BASE :
ArchitecturalMsr.h
MSR_IA32_GS_BASE :
ArchitecturalMsr.h
MSR_IA32_HWP_CAPABILITIES :
ArchitecturalMsr.h
MSR_IA32_HWP_INTERRUPT :
ArchitecturalMsr.h
MSR_IA32_HWP_REQUEST :
ArchitecturalMsr.h
MSR_IA32_HWP_REQUEST_PKG :
ArchitecturalMsr.h
MSR_IA32_HWP_STATUS :
ArchitecturalMsr.h
MSR_IA32_KERNEL_GS_BASE :
ArchitecturalMsr.h
MSR_IA32_L2_QOS_CFG :
ArchitecturalMsr.h
MSR_IA32_L3_QOS_CFG :
ArchitecturalMsr.h
MSR_IA32_LSTAR :
ArchitecturalMsr.h
MSR_IA32_MC0_ADDR :
ArchitecturalMsr.h
MSR_IA32_MC0_CTL :
ArchitecturalMsr.h
MSR_IA32_MC0_CTL2 :
ArchitecturalMsr.h
MSR_IA32_MC0_MISC :
ArchitecturalMsr.h
MSR_IA32_MC0_STATUS :
ArchitecturalMsr.h
MSR_IA32_MCG_CAP :
ArchitecturalMsr.h
MSR_IA32_MCG_CTL :
ArchitecturalMsr.h
MSR_IA32_MCG_EXT_CTL :
ArchitecturalMsr.h
MSR_IA32_MCG_STATUS :
ArchitecturalMsr.h
MSR_IA32_MISC_ENABLE :
ArchitecturalMsr.h
MSR_IA32_MONITOR_FILTER_SIZE :
ArchitecturalMsr.h
MSR_IA32_MPERF :
ArchitecturalMsr.h
MSR_IA32_MTRR_DEF_TYPE :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX16K_80000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX16K_A0000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX4K_C0000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX4K_C8000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX4K_D0000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX4K_D8000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX4K_E0000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX4K_E8000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX4K_F0000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX4K_F8000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_FIX64K_00000 :
ArchitecturalMsr.h
MSR_IA32_MTRR_PHYSBASE0 :
ArchitecturalMsr.h
MSR_IA32_MTRR_PHYSMASK0 :
ArchitecturalMsr.h
MSR_IA32_MTRRCAP :
ArchitecturalMsr.h
MSR_IA32_P5_MC_ADDR :
ArchitecturalMsr.h
MSR_IA32_P5_MC_TYPE :
ArchitecturalMsr.h
MSR_IA32_PACKAGE_THERM_INTERRUPT :
ArchitecturalMsr.h
MSR_IA32_PACKAGE_THERM_STATUS :
ArchitecturalMsr.h
MSR_IA32_PAT :
ArchitecturalMsr.h
MSR_IA32_PEBS_ENABLE :
ArchitecturalMsr.h
MSR_IA32_PERF_CAPABILITIES :
ArchitecturalMsr.h
MSR_IA32_PERF_CTL :
ArchitecturalMsr.h
MSR_IA32_PERF_GLOBAL_CTRL :
ArchitecturalMsr.h
MSR_IA32_PERF_GLOBAL_INUSE :
ArchitecturalMsr.h
MSR_IA32_PERF_GLOBAL_OVF_CTRL :
ArchitecturalMsr.h
MSR_IA32_PERF_GLOBAL_STATUS :
ArchitecturalMsr.h
MSR_IA32_PERF_GLOBAL_STATUS_RESET :
ArchitecturalMsr.h
MSR_IA32_PERF_GLOBAL_STATUS_SET :
ArchitecturalMsr.h
MSR_IA32_PERF_STATUS :
ArchitecturalMsr.h
MSR_IA32_PERFEVTSEL0 :
ArchitecturalMsr.h
MSR_IA32_PKG_HDC_CTL :
ArchitecturalMsr.h
MSR_IA32_PLATFORM_DCA_CAP :
ArchitecturalMsr.h
MSR_IA32_PLATFORM_ID :
ArchitecturalMsr.h
MSR_IA32_PM_CTL1 :
ArchitecturalMsr.h
MSR_IA32_PM_ENABLE :
ArchitecturalMsr.h
MSR_IA32_PMC0 :
ArchitecturalMsr.h
MSR_IA32_PQR_ASSOC :
ArchitecturalMsr.h
MSR_IA32_QM_CTR :
ArchitecturalMsr.h
MSR_IA32_QM_EVTSEL :
ArchitecturalMsr.h
MSR_IA32_RTIT_ADDR0_A :
ArchitecturalMsr.h
MSR_IA32_RTIT_ADDR0_B :
ArchitecturalMsr.h
MSR_IA32_RTIT_CR3_MATCH :
ArchitecturalMsr.h
MSR_IA32_RTIT_CTL :
ArchitecturalMsr.h
,
GoldmontMsr.h
MSR_IA32_RTIT_OUTPUT_BASE :
ArchitecturalMsr.h
MSR_IA32_RTIT_OUTPUT_MASK_PTRS :
ArchitecturalMsr.h
MSR_IA32_RTIT_STATUS :
ArchitecturalMsr.h
MSR_IA32_SGX_SVN_STATUS :
ArchitecturalMsr.h
MSR_IA32_SGXLEPUBKEYHASH0 :
ArchitecturalMsr.h
MSR_IA32_SMBASE :
ArchitecturalMsr.h
MSR_IA32_SMM_MONITOR_CTL :
ArchitecturalMsr.h
MSR_IA32_SMRR_PHYSBASE :
ArchitecturalMsr.h
MSR_IA32_SMRR_PHYSMASK :
ArchitecturalMsr.h
MSR_IA32_STAR :
ArchitecturalMsr.h
MSR_IA32_SYSENTER_CS :
ArchitecturalMsr.h
MSR_IA32_SYSENTER_EIP :
ArchitecturalMsr.h
MSR_IA32_SYSENTER_ESP :
ArchitecturalMsr.h
MSR_IA32_THERM_INTERRUPT :
ArchitecturalMsr.h
MSR_IA32_THERM_STATUS :
ArchitecturalMsr.h
MSR_IA32_THREAD_STALL :
ArchitecturalMsr.h
MSR_IA32_TIME_STAMP_COUNTER :
ArchitecturalMsr.h
MSR_IA32_TME_ACTIVATE :
ArchitecturalMsr.h
MSR_IA32_TSC_ADJUST :
ArchitecturalMsr.h
MSR_IA32_TSC_AUX :
ArchitecturalMsr.h
MSR_IA32_TSC_DEADLINE :
ArchitecturalMsr.h
MSR_IA32_VMX_BASIC :
ArchitecturalMsr.h
MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE :
ArchitecturalMsr.h
MSR_IA32_VMX_CR0_FIXED0 :
ArchitecturalMsr.h
MSR_IA32_VMX_CR0_FIXED1 :
ArchitecturalMsr.h
MSR_IA32_VMX_CR4_FIXED0 :
ArchitecturalMsr.h
MSR_IA32_VMX_CR4_FIXED1 :
ArchitecturalMsr.h
MSR_IA32_VMX_ENTRY_CTLS :
ArchitecturalMsr.h
MSR_IA32_VMX_EPT_VPID_CAP :
ArchitecturalMsr.h
MSR_IA32_VMX_EXIT_CTLS :
ArchitecturalMsr.h
MSR_IA32_VMX_MISC :
ArchitecturalMsr.h
MSR_IA32_VMX_PINBASED_CTLS :
ArchitecturalMsr.h
MSR_IA32_VMX_PROCBASED_CTLS :
ArchitecturalMsr.h
MSR_IA32_VMX_PROCBASED_CTLS2 :
ArchitecturalMsr.h
MSR_IA32_VMX_TRUE_ENTRY_CTLS :
ArchitecturalMsr.h
MSR_IA32_VMX_TRUE_EXIT_CTLS :
ArchitecturalMsr.h
MSR_IA32_VMX_TRUE_PINBASED_CTLS :
ArchitecturalMsr.h
MSR_IA32_VMX_TRUE_PROCBASED_CTLS :
ArchitecturalMsr.h
MSR_IA32_VMX_VMCS_ENUM :
ArchitecturalMsr.h
MSR_IA32_VMX_VMFUNC :
ArchitecturalMsr.h
MSR_IA32_X2APIC_APICID :
ArchitecturalMsr.h
MSR_IA32_X2APIC_CUR_COUNT :
ArchitecturalMsr.h
MSR_IA32_X2APIC_DIV_CONF :
ArchitecturalMsr.h
MSR_IA32_X2APIC_EOI :
ArchitecturalMsr.h
MSR_IA32_X2APIC_ESR :
ArchitecturalMsr.h
MSR_IA32_X2APIC_ICR :
ArchitecturalMsr.h
MSR_IA32_X2APIC_INIT_COUNT :
ArchitecturalMsr.h
MSR_IA32_X2APIC_IRR0 :
ArchitecturalMsr.h
MSR_IA32_X2APIC_ISR0 :
ArchitecturalMsr.h
MSR_IA32_X2APIC_LDR :
ArchitecturalMsr.h
MSR_IA32_X2APIC_LVT_CMCI :
ArchitecturalMsr.h
MSR_IA32_X2APIC_LVT_ERROR :
ArchitecturalMsr.h
MSR_IA32_X2APIC_LVT_LINT0 :
ArchitecturalMsr.h
MSR_IA32_X2APIC_LVT_LINT1 :
ArchitecturalMsr.h
MSR_IA32_X2APIC_LVT_PMI :
ArchitecturalMsr.h
MSR_IA32_X2APIC_LVT_THERMAL :
ArchitecturalMsr.h
MSR_IA32_X2APIC_LVT_TIMER :
ArchitecturalMsr.h
MSR_IA32_X2APIC_PPR :
ArchitecturalMsr.h
MSR_IA32_X2APIC_SELF_IPI :
ArchitecturalMsr.h
MSR_IA32_X2APIC_SIVR :
ArchitecturalMsr.h
MSR_IA32_X2APIC_TMR0 :
ArchitecturalMsr.h
MSR_IA32_X2APIC_TPR :
ArchitecturalMsr.h
MSR_IA32_X2APIC_VERSION :
ArchitecturalMsr.h
MSR_IA32_XSS :
ArchitecturalMsr.h
MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_BOX_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_CTR0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_CTR1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_CTR2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_CTR3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_BOX_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_CTR0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_CTR1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_CTR2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_CTR3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_BOX_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_CTR0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_CTR1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_CTR2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_CTR3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_BOX_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_CTR0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_CTR1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_CTR2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_CTR3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_BOX_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_CTR0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_CTR1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_CTR2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_CTR3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_BOX_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_CTR0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_CTR1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_CTR2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_CTR3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_BOX_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_CTR0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_CTR1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_CTR2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_CTR3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_DRAM_PERF_STATUS :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_DRAM_POWER_INFO :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_DRAM_POWER_LIMIT :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_ERROR_CONTROL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_IA32_MC29_ADDR :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_IA32_MC29_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_IA32_MC29_MISC :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_IA32_MC29_STATUS :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_IA32_MC6_MISC :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PEBS_ENABLE :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PKG_PERF_STATUS :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PLATFORM_INFO :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PLATFORM_INFO_1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PMON_GLOBAL_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PP0_ENERGY_STATUS :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PPIN :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_PPIN_CTL :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_TEMPERATURE_TARGET :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 :
IvyBridgeMsr.h
MSR_IVY_BRIDGE_U_PMON_BOX_STATUS :
IvyBridgeMsr.h
MSR_NEHALEM_B0_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_MASK :
NehalemMsr.h
MSR_NEHALEM_B0_PMON_MATCH :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_MASK :
NehalemMsr.h
MSR_NEHALEM_B1_PMON_MATCH :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_C0_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_C1_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_C2_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_C3_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_C4_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_C5_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_C6_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_C7_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_CORE_C3_RESIDENCY :
NehalemMsr.h
MSR_NEHALEM_CORE_C6_RESIDENCY :
NehalemMsr.h
MSR_NEHALEM_GQ_SNOOP_MESF :
NehalemMsr.h
MSR_NEHALEM_IA32_MISC_ENABLE :
NehalemMsr.h
MSR_NEHALEM_LASTBRANCH_0_FROM_IP :
NehalemMsr.h
MSR_NEHALEM_LASTBRANCH_0_TO_IP :
NehalemMsr.h
MSR_NEHALEM_LASTBRANCH_TOS :
NehalemMsr.h
MSR_NEHALEM_LBR_SELECT :
NehalemMsr.h
MSR_NEHALEM_LER_FROM_LIP :
NehalemMsr.h
MSR_NEHALEM_LER_TO_LIP :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_ADDR_MASK :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_ADDR_MATCH :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_DSP :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_ISS :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_MAP :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_MM_CONFIG :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_MSC_THR :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_PGT :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_PLD :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_TIMESTAMP :
NehalemMsr.h
MSR_NEHALEM_M0_PMON_ZDP :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_ADDR_MASK :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_ADDR_MATCH :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_DSP :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_ISS :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_MAP :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_MM_CONFIG :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_MSC_THR :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_PGT :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_PLD :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_TIMESTAMP :
NehalemMsr.h
MSR_NEHALEM_M1_PMON_ZDP :
NehalemMsr.h
MSR_NEHALEM_MISC_FEATURE_CONTROL :
NehalemMsr.h
MSR_NEHALEM_MISC_PWR_MGMT :
NehalemMsr.h
MSR_NEHALEM_OFFCORE_RSP_0 :
NehalemMsr.h
MSR_NEHALEM_PEBS_ENABLE :
NehalemMsr.h
MSR_NEHALEM_PEBS_LD_LAT :
NehalemMsr.h
MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_PERF_GLOBAL_STATUS :
NehalemMsr.h
MSR_NEHALEM_PKG_C3_RESIDENCY :
NehalemMsr.h
MSR_NEHALEM_PKG_C6_RESIDENCY :
NehalemMsr.h
MSR_NEHALEM_PKG_C7_RESIDENCY :
NehalemMsr.h
MSR_NEHALEM_PKG_CST_CONFIG_CONTROL :
NehalemMsr.h
MSR_NEHALEM_PLATFORM_ID :
NehalemMsr.h
MSR_NEHALEM_PLATFORM_INFO :
NehalemMsr.h
MSR_NEHALEM_PMG_IO_CAPTURE_BASE :
NehalemMsr.h
MSR_NEHALEM_POWER_CTL :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_CTR4 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_CTR5 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_CTR6 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_CTR7 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_EVNT_SEL4 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_EVNT_SEL5 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_EVNT_SEL6 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_EVNT_SEL7 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_IPERF0_P0 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_IPERF0_P1 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_IPERF0_P2 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_IPERF0_P3 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_IPERF0_P4 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_IPERF0_P5 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_IPERF0_P6 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_IPERF0_P7 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_QLX_P0 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_QLX_P1 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_QLX_P2 :
NehalemMsr.h
MSR_NEHALEM_R0_PMON_QLX_P3 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_CTR10 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_CTR11 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_CTR12 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_CTR13 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_CTR14 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_CTR15 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_CTR8 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_CTR9 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_EVNT_SEL10 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_EVNT_SEL11 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_EVNT_SEL12 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_EVNT_SEL13 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_EVNT_SEL14 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_EVNT_SEL15 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_EVNT_SEL8 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_EVNT_SEL9 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_IPERF1_P10 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_IPERF1_P11 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_IPERF1_P12 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_IPERF1_P13 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_IPERF1_P14 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_IPERF1_P15 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_IPERF1_P8 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_IPERF1_P9 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_QLX_P4 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_QLX_P5 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_QLX_P6 :
NehalemMsr.h
MSR_NEHALEM_R1_PMON_QLX_P7 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_MASK :
NehalemMsr.h
MSR_NEHALEM_S0_PMON_MATCH :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_MASK :
NehalemMsr.h
MSR_NEHALEM_S1_PMON_MATCH :
NehalemMsr.h
MSR_NEHALEM_SMI_COUNT :
NehalemMsr.h
MSR_NEHALEM_TEMPERATURE_TARGET :
NehalemMsr.h
MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT :
NehalemMsr.h
MSR_NEHALEM_TURBO_RATIO_LIMIT :
NehalemMsr.h
MSR_NEHALEM_U_PMON_CTR :
NehalemMsr.h
MSR_NEHALEM_U_PMON_EVNT_SEL :
NehalemMsr.h
MSR_NEHALEM_U_PMON_GLOBAL_CTRL :
NehalemMsr.h
MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_U_PMON_GLOBAL_STATUS :
NehalemMsr.h
MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH :
NehalemMsr.h
MSR_NEHALEM_UNCORE_FIXED_CTR0 :
NehalemMsr.h
MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL :
NehalemMsr.h
MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL :
NehalemMsr.h
MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS :
NehalemMsr.h
MSR_NEHALEM_UNCORE_PERFEVTSEL0 :
NehalemMsr.h
MSR_NEHALEM_UNCORE_PMC0 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_BOX_CTRL :
NehalemMsr.h
MSR_NEHALEM_W_PMON_BOX_OVF_CTRL :
NehalemMsr.h
MSR_NEHALEM_W_PMON_BOX_STATUS :
NehalemMsr.h
MSR_NEHALEM_W_PMON_CTR0 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_CTR1 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_CTR2 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_CTR3 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_EVNT_SEL0 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_EVNT_SEL1 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_EVNT_SEL2 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_EVNT_SEL3 :
NehalemMsr.h
MSR_NEHALEM_W_PMON_FIXED_CTR :
NehalemMsr.h
MSR_NEHALEM_W_PMON_FIXED_CTR_CTL :
NehalemMsr.h
MSR_P6_APIC_BASE :
P6Msr.h
MSR_P6_BBL_CR_ADDR :
P6Msr.h
MSR_P6_BBL_CR_BUSY :
P6Msr.h
MSR_P6_BBL_CR_CTL :
P6Msr.h
MSR_P6_BBL_CR_CTL3 :
P6Msr.h
MSR_P6_BBL_CR_D0 :
P6Msr.h
MSR_P6_BBL_CR_DECC :
P6Msr.h
MSR_P6_BBL_CR_TRIG :
P6Msr.h
MSR_P6_BIOS_SIGN :
P6Msr.h
MSR_P6_BIOS_UPDT_TRIG :
P6Msr.h
MSR_P6_DEBUGCTLMSR :
P6Msr.h
MSR_P6_EBL_CR_POWERON :
P6Msr.h
MSR_P6_IA32_PLATFORM_ID :
P6Msr.h
MSR_P6_LASTBRANCHFROMIP :
P6Msr.h
MSR_P6_LASTBRANCHTOIP :
P6Msr.h
MSR_P6_LASTINTFROMIP :
P6Msr.h
MSR_P6_LASTINTTOIP :
P6Msr.h
MSR_P6_MC0_ADDR :
P6Msr.h
MSR_P6_MC0_CTL :
P6Msr.h
MSR_P6_MC0_MISC :
P6Msr.h
MSR_P6_MC0_STATUS :
P6Msr.h
MSR_P6_MCG_CAP :
P6Msr.h
MSR_P6_MCG_CTL :
P6Msr.h
MSR_P6_MCG_STATUS :
P6Msr.h
MSR_P6_MTRRCAP :
P6Msr.h
MSR_P6_MTRRDEFTYPE :
P6Msr.h
MSR_P6_MTRRFIX16K_80000 :
P6Msr.h
MSR_P6_MTRRFIX16K_A0000 :
P6Msr.h
MSR_P6_MTRRFIX4K_C0000 :
P6Msr.h
MSR_P6_MTRRFIX4K_C8000 :
P6Msr.h
MSR_P6_MTRRFIX4K_D0000 :
P6Msr.h
MSR_P6_MTRRFIX4K_D8000 :
P6Msr.h
MSR_P6_MTRRFIX4K_E0000 :
P6Msr.h
MSR_P6_MTRRFIX4K_E8000 :
P6Msr.h
MSR_P6_MTRRFIX4K_F0000 :
P6Msr.h
MSR_P6_MTRRFIX4K_F8000 :
P6Msr.h
MSR_P6_MTRRFIX64K_00000 :
P6Msr.h
MSR_P6_MTRRPHYSBASE0 :
P6Msr.h
MSR_P6_MTRRPHYSMASK0 :
P6Msr.h
MSR_P6_P5_MC_ADDR :
P6Msr.h
MSR_P6_P5_MC_TYPE :
P6Msr.h
MSR_P6_PERFCTR0 :
P6Msr.h
MSR_P6_PERFEVTSEL0 :
P6Msr.h
MSR_P6_SYSENTER_CS_MSR :
P6Msr.h
MSR_P6_SYSENTER_EIP_MSR :
P6Msr.h
MSR_P6_SYSENTER_ESP_MSR :
P6Msr.h
MSR_P6_TEST_CTL :
P6Msr.h
MSR_P6_TSC :
P6Msr.h
MSR_PENTIUM_4_ALF_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_BPU_CCCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_BPU_COUNTER0 :
Pentium4Msr.h
MSR_PENTIUM_4_BPU_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_BPU_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_BSU_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_BSU_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_CRU_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_CRU_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_DAC_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_DAC_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_DEBUGCTLA :
Pentium4Msr.h
MSR_PENTIUM_4_EBC_FREQUENCY_ID :
Pentium4Msr.h
MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 :
Pentium4Msr.h
MSR_PENTIUM_4_EBC_HARD_POWERON :
Pentium4Msr.h
MSR_PENTIUM_4_EBC_SOFT_POWERON :
Pentium4Msr.h
MSR_PENTIUM_4_EFSB_DRDY0 :
Pentium4Msr.h
MSR_PENTIUM_4_EFSB_DRDY1 :
Pentium4Msr.h
MSR_PENTIUM_4_EMON_L3_CTR_CTL0 :
Pentium4Msr.h
MSR_PENTIUM_4_EMON_L3_CTR_CTL1 :
Pentium4Msr.h
MSR_PENTIUM_4_EMON_L3_CTR_CTL2 :
Pentium4Msr.h
MSR_PENTIUM_4_EMON_L3_CTR_CTL3 :
Pentium4Msr.h
MSR_PENTIUM_4_EMON_L3_CTR_CTL4 :
Pentium4Msr.h
MSR_PENTIUM_4_EMON_L3_CTR_CTL5 :
Pentium4Msr.h
MSR_PENTIUM_4_EMON_L3_CTR_CTL6 :
Pentium4Msr.h
MSR_PENTIUM_4_EMON_L3_CTR_CTL7 :
Pentium4Msr.h
MSR_PENTIUM_4_FIRM_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_FIRM_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_FLAME_CCCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_FLAME_COUNTER0 :
Pentium4Msr.h
MSR_PENTIUM_4_FLAME_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_FLAME_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_FSB_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_FSB_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_IA32_MISC_ENABLE :
Pentium4Msr.h
MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE :
Pentium4Msr.h
MSR_PENTIUM_4_IFSB_BUSQ0 :
Pentium4Msr.h
MSR_PENTIUM_4_IFSB_BUSQ1 :
Pentium4Msr.h
MSR_PENTIUM_4_IFSB_CNTR7 :
Pentium4Msr.h
MSR_PENTIUM_4_IFSB_CTL6 :
Pentium4Msr.h
MSR_PENTIUM_4_IFSB_SNPQ0 :
Pentium4Msr.h
MSR_PENTIUM_4_IFSB_SNPQ1 :
Pentium4Msr.h
MSR_PENTIUM_4_IQ_CCCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_IQ_COUNTER0 :
Pentium4Msr.h
MSR_PENTIUM_4_IQ_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_IQ_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_IS_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_IS_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_ITLB_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_ITLB_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_IX_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_IX_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_LASTBRANCH_0 :
Pentium4Msr.h
MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP :
Pentium4Msr.h
MSR_PENTIUM_4_LASTBRANCH_0_TO_IP :
Pentium4Msr.h
MSR_PENTIUM_4_LASTBRANCH_TOS :
Pentium4Msr.h
MSR_PENTIUM_4_LER_FROM_LIP :
Pentium4Msr.h
MSR_PENTIUM_4_LER_TO_LIP :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_MISC :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_R10 :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_R11 :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_R12 :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_R13 :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_R14 :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_R15 :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_R8 :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_R9 :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RAX :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RBP :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RBX :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RCX :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RDI :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RDX :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RFLAGS :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RIP :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RSI :
Pentium4Msr.h
MSR_PENTIUM_4_MCG_RSP :
Pentium4Msr.h
MSR_PENTIUM_4_MOB_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_MOB_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_MS_CCCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_MS_COUNTER0 :
Pentium4Msr.h
MSR_PENTIUM_4_MS_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_MS_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_PEBS_ENABLE :
Pentium4Msr.h
MSR_PENTIUM_4_PEBS_MATRIX_VERT :
Pentium4Msr.h
MSR_PENTIUM_4_PLATFORM_BRV :
Pentium4Msr.h
MSR_PENTIUM_4_PMH_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_PMH_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_RAT_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_RAT_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_SAAT_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_SAAT_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_SSU_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_TBPU_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_TBPU_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_TC_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_TC_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_4_TC_PRECISE_EVENT :
Pentium4Msr.h
MSR_PENTIUM_4_THERM2_CTL :
Pentium4Msr.h
MSR_PENTIUM_4_U2L_ESCR0 :
Pentium4Msr.h
MSR_PENTIUM_4_U2L_ESCR1 :
Pentium4Msr.h
MSR_PENTIUM_CESR :
PentiumMsr.h
MSR_PENTIUM_CTR0 :
PentiumMsr.h
MSR_PENTIUM_M_BBL_CR_CTL :
PentiumMMsr.h
MSR_PENTIUM_M_BBL_CR_CTL3 :
PentiumMMsr.h
MSR_PENTIUM_M_DEBUGCTLB :
PentiumMMsr.h
MSR_PENTIUM_M_EBL_CR_POWERON :
PentiumMMsr.h
MSR_PENTIUM_M_IA32_MISC_ENABLE :
PentiumMMsr.h
MSR_PENTIUM_M_LASTBRANCH_0 :
PentiumMMsr.h
MSR_PENTIUM_M_LASTBRANCH_TOS :
PentiumMMsr.h
MSR_PENTIUM_M_LER_FROM_LIP :
PentiumMMsr.h
MSR_PENTIUM_M_LER_TO_LIP :
PentiumMMsr.h
MSR_PENTIUM_M_MC3_ADDR :
PentiumMMsr.h
MSR_PENTIUM_M_MC3_CTL :
PentiumMMsr.h
MSR_PENTIUM_M_MC3_STATUS :
PentiumMMsr.h
MSR_PENTIUM_M_MC4_ADDR :
PentiumMMsr.h
MSR_PENTIUM_M_MC4_CTL :
PentiumMMsr.h
MSR_PENTIUM_M_MC4_STATUS :
PentiumMMsr.h
MSR_PENTIUM_M_P5_MC_ADDR :
PentiumMMsr.h
MSR_PENTIUM_M_P5_MC_TYPE :
PentiumMMsr.h
MSR_PENTIUM_M_THERM2_CTL :
PentiumMMsr.h
MSR_PENTIUM_P5_MC_ADDR :
PentiumMsr.h
MSR_PENTIUM_P5_MC_TYPE :
PentiumMsr.h
MSR_PENTIUM_TSC :
PentiumMsr.h
MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_DRAM_PERF_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_DRAM_POWER_INFO :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_ERROR_CONTROL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_FEATURE_CONFIG :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_MC4_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_MC4_CTL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_MISC_ENABLE :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_LASTBRANCH_TOS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_LBR_SELECT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_LER_FROM_LIP :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_LER_TO_LIP :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_MISC_PWR_MGMT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_OFFCORE_RSP_0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_OFFCORE_RSP_1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_CTR2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_CTR3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PEBS_ENABLE :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PEBS_LD_LAT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PEBS_NUM_ALT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PERF_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_PERF_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_POWER_INFO :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKG_POWER_LIMIT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKGC3_IRTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKGC6_IRTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PKGC7_IRTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PLATFORM_INFO :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_POWER_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PP0_POLICY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PP0_POWER_LIMIT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PP1_POLICY :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_PP1_POWER_LIMIT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_RAPL_POWER_UNIT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_SMI_COUNT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_TEMPERATURE_TARGET :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_U_PMON_CTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_U_PMON_CTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_CBO_CONFIG :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL :
SandyBridgeMsr.h
MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS :
SandyBridgeMsr.h
MSR_SEV_ES_GHCB :
SevSnpMsr.h
MSR_SEV_STATUS :
SevSnpMsr.h
MSR_SILVERMONT_BBL_CR_CTL3 :
SilvermontMsr.h
MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG :
SilvermontMsr.h
MSR_SILVERMONT_CORE_C1_RESIDENCY :
SilvermontMsr.h
MSR_SILVERMONT_CORE_C6_RESIDENCY :
SilvermontMsr.h
MSR_SILVERMONT_EBL_CR_POWERON :
SilvermontMsr.h
MSR_SILVERMONT_FEATURE_CONFIG :
SilvermontMsr.h
MSR_SILVERMONT_FSB_FREQ :
SilvermontMsr.h
MSR_SILVERMONT_IA32_FEATURE_CONTROL :
SilvermontMsr.h
MSR_SILVERMONT_IA32_MISC_ENABLE :
SilvermontMsr.h
MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM :
SilvermontMsr.h
MSR_SILVERMONT_IA32_VMX_FMFUNC :
SilvermontMsr.h
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP :
SilvermontMsr.h
MSR_SILVERMONT_LASTBRANCH_0_TO_IP :
SilvermontMsr.h
MSR_SILVERMONT_LASTBRANCH_TOS :
SilvermontMsr.h
MSR_SILVERMONT_LBR_SELECT :
SilvermontMsr.h
MSR_SILVERMONT_LER_FROM_LIP :
SilvermontMsr.h
MSR_SILVERMONT_LER_TO_LIP :
SilvermontMsr.h
MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG :
SilvermontMsr.h
MSR_SILVERMONT_MC6_RESIDENCY_COUNTER :
SilvermontMsr.h
MSR_SILVERMONT_MISC_FEATURE_CONTROL :
SilvermontMsr.h
MSR_SILVERMONT_OFFCORE_RSP_0 :
SilvermontMsr.h
MSR_SILVERMONT_OFFCORE_RSP_1 :
SilvermontMsr.h
MSR_SILVERMONT_PEBS_ENABLE :
SilvermontMsr.h
MSR_SILVERMONT_PKG_C6_RESIDENCY :
SilvermontMsr.h
MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL :
SilvermontMsr.h
MSR_SILVERMONT_PKG_ENERGY_STATUS :
SilvermontMsr.h
MSR_SILVERMONT_PKG_POWER_INFO :
SilvermontMsr.h
MSR_SILVERMONT_PKG_POWER_LIMIT :
SilvermontMsr.h
MSR_SILVERMONT_PLATFORM_ID :
SilvermontMsr.h
MSR_SILVERMONT_PLATFORM_INFO :
SilvermontMsr.h
MSR_SILVERMONT_PMG_IO_CAPTURE_BASE :
SilvermontMsr.h
MSR_SILVERMONT_PP0_ENERGY_STATUS :
SilvermontMsr.h
MSR_SILVERMONT_PP0_POWER_LIMIT :
SilvermontMsr.h
MSR_SILVERMONT_RAPL_POWER_UNIT :
SilvermontMsr.h
MSR_SILVERMONT_SMI_COUNT :
SilvermontMsr.h
MSR_SILVERMONT_TEMPERATURE_TARGET :
SilvermontMsr.h
MSR_SILVERMONT_TURBO_RATIO_LIMIT :
SilvermontMsr.h
MSR_SKYLAKE_ANY_CORE_C0 :
SkylakeMsr.h
MSR_SKYLAKE_ANY_GFXE_C0 :
SkylakeMsr.h
MSR_SKYLAKE_BR_DETECT_CTRL :
SkylakeMsr.h
MSR_SKYLAKE_BR_DETECT_STATUS :
SkylakeMsr.h
MSR_SKYLAKE_CORE_C1_RESIDENCY :
SkylakeMsr.h
MSR_SKYLAKE_CORE_C3_RESIDENCY :
SkylakeMsr.h
MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 :
SkylakeMsr.h
MSR_SKYLAKE_CORE_HDC_RESIDENCY :
SkylakeMsr.h
MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS :
SkylakeMsr.h
MSR_SKYLAKE_DRAM_ENERGY_STATUS :
SkylakeMsr.h
MSR_SKYLAKE_DRAM_PERF_STATUS :
SkylakeMsr.h
MSR_SKYLAKE_DRAM_POWER_INFO :
SkylakeMsr.h
MSR_SKYLAKE_DRAM_POWER_LIMIT :
SkylakeMsr.h
MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS :
SkylakeMsr.h
MSR_SKYLAKE_IA32_L3_QOS_MASK_0 :
SkylakeMsr.h
MSR_SKYLAKE_IA32_MCG_CAP :
SkylakeMsr.h
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS :
SkylakeMsr.h
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET :
SkylakeMsr.h
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET :
SkylakeMsr.h
MSR_SKYLAKE_IA32_PQR_ASSOC :
SkylakeMsr.h
MSR_SKYLAKE_IA32_QM_EVTSEL :
SkylakeMsr.h
MSR_SKYLAKE_LASTBRANCH_16_FROM_IP :
SkylakeMsr.h
MSR_SKYLAKE_LASTBRANCH_16_TO_IP :
SkylakeMsr.h
MSR_SKYLAKE_LASTBRANCH_TOS :
SkylakeMsr.h
MSR_SKYLAKE_LBR_INFO_0 :
SkylakeMsr.h
MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT :
SkylakeMsr.h
MSR_SKYLAKE_PEBS_FRONTEND :
SkylakeMsr.h
MSR_SKYLAKE_PKG_C3_RESIDENCY :
SkylakeMsr.h
MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL :
SkylakeMsr.h
MSR_SKYLAKE_PKG_HDC_CONFIG :
SkylakeMsr.h
MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY :
SkylakeMsr.h
MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY :
SkylakeMsr.h
MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER :
SkylakeMsr.h
MSR_SKYLAKE_PLATFORM_INFO :
SkylakeMsr.h
MSR_SKYLAKE_PLATFORM_POWER_LIMIT :
SkylakeMsr.h
MSR_SKYLAKE_POWER_CTL :
SkylakeMsr.h
MSR_SKYLAKE_PP0_ENERGY_STATUS :
SkylakeMsr.h
MSR_SKYLAKE_PPERF :
SkylakeMsr.h
MSR_SKYLAKE_PPIN :
SkylakeMsr.h
MSR_SKYLAKE_PPIN_CTL :
SkylakeMsr.h
MSR_SKYLAKE_PRMRR_PHYS_BASE :
SkylakeMsr.h
MSR_SKYLAKE_PRMRR_PHYS_MASK :
SkylakeMsr.h
MSR_SKYLAKE_PRMRR_VALID_CONFIG :
SkylakeMsr.h
MSR_SKYLAKE_RAPL_POWER_UNIT :
SkylakeMsr.h
MSR_SKYLAKE_RING_PERF_LIMIT_REASONS :
SkylakeMsr.h
MSR_SKYLAKE_RING_RATIO_LIMIT :
SkylakeMsr.h
MSR_SKYLAKE_SGXOWNEREPOCH0 :
SkylakeMsr.h
MSR_SKYLAKE_SGXOWNEREPOCH1 :
SkylakeMsr.h
MSR_SKYLAKE_SMM_MCA_CAP :
SkylakeMsr.h
MSR_SKYLAKE_TEMPERATURE_TARGET :
SkylakeMsr.h
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE :
SkylakeMsr.h
MSR_SKYLAKE_TURBO_RATIO_LIMIT :
SkylakeMsr.h
MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES :
SkylakeMsr.h
MSR_SKYLAKE_UNC_ARB_PERFCTR0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_ARB_PERFCTR1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 :
SkylakeMsr.h
MSR_SKYLAKE_UNC_CBO_CONFIG :
SkylakeMsr.h
MSR_SKYLAKE_UNC_PERF_FIXED_CTR :
SkylakeMsr.h
MSR_SKYLAKE_UNC_PERF_FIXED_CTRL :
SkylakeMsr.h
MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL :
SkylakeMsr.h
MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS :
SkylakeMsr.h
MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE :
SkylakeMsr.h
MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK :
SkylakeMsr.h
MSR_SKYLAKE_WEIGHTED_CORE_C0 :
SkylakeMsr.h
MSR_SVSM_CAA :
SvsmMsr.h
MSR_XEON_5600_FEATURE_CONFIG :
Xeon5600Msr.h
MSR_XEON_5600_IA32_ENERGY_PERF_BIAS :
Xeon5600Msr.h
MSR_XEON_5600_OFFCORE_RSP_1 :
Xeon5600Msr.h
MSR_XEON_5600_TURBO_RATIO_LIMIT :
Xeon5600Msr.h
MSR_XEON_D_CORE_PERF_LIMIT_REASONS :
XeonDMsr.h
MSR_XEON_D_DRAM_ENERGY_STATUS :
XeonDMsr.h
MSR_XEON_D_DRAM_PERF_STATUS :
XeonDMsr.h
MSR_XEON_D_DRAM_POWER_INFO :
XeonDMsr.h
MSR_XEON_D_DRAM_POWER_LIMIT :
XeonDMsr.h
MSR_XEON_D_IA32_L3_QOS_CFG :
XeonDMsr.h
MSR_XEON_D_IA32_L3_QOS_MASK_0 :
XeonDMsr.h
MSR_XEON_D_IA32_MCG_CAP :
XeonDMsr.h
MSR_XEON_D_IA32_PQR_ASSOC :
XeonDMsr.h
MSR_XEON_D_IA32_QM_EVTSEL :
XeonDMsr.h
MSR_XEON_D_MSRUNCORE_RATIO_LIMIT :
XeonDMsr.h
MSR_XEON_D_PKG_CST_CONFIG_CONTROL :
XeonDMsr.h
MSR_XEON_D_PLATFORM_INFO :
XeonDMsr.h
MSR_XEON_D_PP0_ENERGY_STATUS :
XeonDMsr.h
MSR_XEON_D_PPIN :
XeonDMsr.h
MSR_XEON_D_PPIN_CTL :
XeonDMsr.h
MSR_XEON_D_RAPL_POWER_UNIT :
XeonDMsr.h
MSR_XEON_D_SMM_MCA_CAP :
XeonDMsr.h
MSR_XEON_D_TEMPERATURE_TARGET :
XeonDMsr.h
MSR_XEON_D_TURBO_RATIO_LIMIT :
XeonDMsr.h
MSR_XEON_D_TURBO_RATIO_LIMIT1 :
XeonDMsr.h
MSR_XEON_D_TURBO_RATIO_LIMIT3 :
XeonDMsr.h
MSR_XEON_E7_C8_PMON_BOX_CTRL :
XeonE7Msr.h
MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL :
XeonE7Msr.h
MSR_XEON_E7_C8_PMON_BOX_STATUS :
XeonE7Msr.h
MSR_XEON_E7_C8_PMON_CTR0 :
XeonE7Msr.h
MSR_XEON_E7_C8_PMON_EVNT_SEL0 :
XeonE7Msr.h
MSR_XEON_E7_C9_PMON_BOX_CTRL :
XeonE7Msr.h
MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL :
XeonE7Msr.h
MSR_XEON_E7_C9_PMON_BOX_STATUS :
XeonE7Msr.h
MSR_XEON_E7_C9_PMON_CTR0 :
XeonE7Msr.h
MSR_XEON_E7_C9_PMON_EVNT_SEL0 :
XeonE7Msr.h
MSR_XEON_E7_FEATURE_CONFIG :
XeonE7Msr.h
MSR_XEON_E7_OFFCORE_RSP_1 :
XeonE7Msr.h
MSR_XEON_E7_TURBO_RATIO_LIMIT :
XeonE7Msr.h
MSR_XEON_PHI_CONFIG_TDP_CONTROL :
XeonPhiMsr.h
MSR_XEON_PHI_CONFIG_TDP_LEVEL1 :
XeonPhiMsr.h
MSR_XEON_PHI_CONFIG_TDP_LEVEL2 :
XeonPhiMsr.h
MSR_XEON_PHI_CONFIG_TDP_NOMINAL :
XeonPhiMsr.h
MSR_XEON_PHI_CORE_C6_RESIDENCY :
XeonPhiMsr.h
MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS :
XeonPhiMsr.h
MSR_XEON_PHI_DRAM_ENERGY_STATUS :
XeonPhiMsr.h
MSR_XEON_PHI_DRAM_PERF_STATUS :
XeonPhiMsr.h
MSR_XEON_PHI_DRAM_POWER_INFO :
XeonPhiMsr.h
MSR_XEON_PHI_DRAM_POWER_LIMIT :
XeonPhiMsr.h
MSR_XEON_PHI_FEATURE_CONFIG :
XeonPhiMsr.h
MSR_XEON_PHI_IA32_MISC_ENABLE :
XeonPhiMsr.h
MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM :
XeonPhiMsr.h
MSR_XEON_PHI_IA32_VMX_FMFUNC :
XeonPhiMsr.h
MSR_XEON_PHI_LASTBRANCH_TOS :
XeonPhiMsr.h
MSR_XEON_PHI_LBR_SELECT :
XeonPhiMsr.h
MSR_XEON_PHI_LER_FROM_LIP :
XeonPhiMsr.h
MSR_XEON_PHI_LER_TO_LIP :
XeonPhiMsr.h
MSR_XEON_PHI_MC0_RESIDENCY :
XeonPhiMsr.h
MSR_XEON_PHI_MC6_RESIDENCY :
XeonPhiMsr.h
MSR_XEON_PHI_MISC_FEATURE_CONTROL :
XeonPhiMsr.h
MSR_XEON_PHI_MISC_FEATURE_ENABLES :
XeonPhiMsr.h
MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT :
XeonPhiMsr.h
MSR_XEON_PHI_OFFCORE_RSP_0 :
XeonPhiMsr.h
MSR_XEON_PHI_OFFCORE_RSP_1 :
XeonPhiMsr.h
MSR_XEON_PHI_PEBS_ENABLE :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_C2_RESIDENCY :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_C3_RESIDENCY :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_C6_RESIDENCY :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_C7_RESIDENCY :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_ENERGY_STATUS :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_PERF_STATUS :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_POWER_INFO :
XeonPhiMsr.h
MSR_XEON_PHI_PKG_POWER_LIMIT :
XeonPhiMsr.h
MSR_XEON_PHI_PLATFORM_INFO :
XeonPhiMsr.h
MSR_XEON_PHI_PMG_IO_CAPTURE_BASE :
XeonPhiMsr.h
MSR_XEON_PHI_PP0_ENERGY_STATUS :
XeonPhiMsr.h
MSR_XEON_PHI_PP0_POWER_LIMIT :
XeonPhiMsr.h
MSR_XEON_PHI_PPIN :
XeonPhiMsr.h
MSR_XEON_PHI_PPIN_CTL :
XeonPhiMsr.h
MSR_XEON_PHI_RAPL_POWER_UNIT :
XeonPhiMsr.h
MSR_XEON_PHI_SMI_COUNT :
XeonPhiMsr.h
MSR_XEON_PHI_SMM_MCA_CAP :
XeonPhiMsr.h
MSR_XEON_PHI_TEMPERATURE_TARGET :
XeonPhiMsr.h
MSR_XEON_PHI_TURBO_ACTIVATION_RATIO :
XeonPhiMsr.h
MSR_XEON_PHI_TURBO_RATIO_LIMIT :
XeonPhiMsr.h
MTFTP4_SERVICE_SIGNATURE :
Mtftp4Impl.h
MTFTP_DEFAULT_BLKSIZE :
Tftp.c
MTFTP_DEFAULT_WINDOWSIZE :
Tftp.c
MTFTP_MIN_BLKSIZE :
Tftp.c
MTFTP_MIN_WINDOWSIZE :
Tftp.c
Generated on Fri Nov 15 2024 18:01:58 for TianoCore EDK2 by
1.9.6