#include <Register/Intel/ArchitecturalMsr.h>

Data Structures
union	MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER

union	MSR_SKYLAKE_POWER_CTL_REGISTER

union	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER

union	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER

union	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER

union	MSR_SKYLAKE_PEBS_FRONTEND_REGISTER

union	MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER

union	MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER

union	MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER

union	MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER

union	MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER

union	MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER

union	MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER

union	MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER

union	MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER

union	MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER

union	MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER

union	MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER

union	MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER

union	MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER

union	MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER

union	MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER

union	MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER

union	MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER

union	MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER

union	MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER

union	MSR_SKYLAKE_PPIN_CTL_REGISTER

union	MSR_SKYLAKE_PLATFORM_INFO_REGISTER

union	MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER

union	MSR_SKYLAKE_IA32_MCG_CAP_REGISTER

union	MSR_SKYLAKE_SMM_MCA_CAP_REGISTER

union	MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER

union	MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER

union	MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER

union	MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER

union	MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER

union	MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER

union	MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER

union	MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER

Macros
#define	IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel)

#define	MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD

#define	MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9

#define	MSR_SKYLAKE_POWER_CTL 0x000001FC

#define	MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300

#define	MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0

#define	MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301

#define	MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1

#define	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E

#define	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390

#define	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391

#define	MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7

#define	MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639

#define	MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D

#define	MSR_SKYLAKE_PPERF 0x0000064E

#define	MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F

#define	MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652

#define	MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653

#define	MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655

#define	MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656

#define	MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658

#define	MSR_SKYLAKE_ANY_CORE_C0 0x00000659

#define	MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A

#define	MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B

#define	MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C

#define	MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0

#define	MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1

#define	MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394

#define	MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395

#define	MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396

#define	MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0

#define	MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1

#define	MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2

#define	MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3

#define	MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700

#define	MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701

#define	MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706

#define	MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707

#define	MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710

#define	MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711

#define	MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716

#define	MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717

#define	MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720

#define	MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721

#define	MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726

#define	MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727

#define	MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730

#define	MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731

#define	MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736

#define	MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737

#define	MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01

#define	MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02

#define	MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080

#define	MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4

#define	MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5

#define	MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB

#define	MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4

#define	MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5

#define	MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620

#define	MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350

#define	MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351

#define	MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8

#define	MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660

#define	MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662

#define	MSR_SKYLAKE_PPIN_CTL 0x0000004E

#define	MSR_SKYLAKE_PPIN 0x0000004F

#define	MSR_SKYLAKE_PLATFORM_INFO 0x000000CE

#define	MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2

#define	MSR_SKYLAKE_IA32_MCG_CAP 0x00000179

#define	MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D

#define	MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2

#define	MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE

#define	MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606

#define	MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618

#define	MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619

#define	MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B

#define	MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C

#define	MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620

#define	MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639

#define	MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D

#define	MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E

#define	MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F


#define	MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690

#define	MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691

#define	MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692

#define	MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693

#define	MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694

#define	MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695

#define	MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696

#define	MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697

#define	MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698

#define	MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699

#define	MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A

#define	MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B

#define	MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C

#define	MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D

#define	MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E

#define	MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F


#define	MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0

#define	MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1

#define	MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2

#define	MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3

#define	MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4

#define	MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5

#define	MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6

#define	MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7

#define	MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8

#define	MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9

#define	MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA

#define	MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB

#define	MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC

#define	MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD

#define	MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE

#define	MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF


#define	MSR_SKYLAKE_LBR_INFO_0 0x00000DC0

#define	MSR_SKYLAKE_LBR_INFO_1 0x00000DC1

#define	MSR_SKYLAKE_LBR_INFO_2 0x00000DC2

#define	MSR_SKYLAKE_LBR_INFO_3 0x00000DC3

#define	MSR_SKYLAKE_LBR_INFO_4 0x00000DC4

#define	MSR_SKYLAKE_LBR_INFO_5 0x00000DC5

#define	MSR_SKYLAKE_LBR_INFO_6 0x00000DC6

#define	MSR_SKYLAKE_LBR_INFO_7 0x00000DC7

#define	MSR_SKYLAKE_LBR_INFO_8 0x00000DC8

#define	MSR_SKYLAKE_LBR_INFO_9 0x00000DC9

#define	MSR_SKYLAKE_LBR_INFO_10 0x00000DCA

#define	MSR_SKYLAKE_LBR_INFO_11 0x00000DCB

#define	MSR_SKYLAKE_LBR_INFO_12 0x00000DCC

#define	MSR_SKYLAKE_LBR_INFO_13 0x00000DCD

#define	MSR_SKYLAKE_LBR_INFO_14 0x00000DCE

#define	MSR_SKYLAKE_LBR_INFO_15 0x00000DCF

#define	MSR_SKYLAKE_LBR_INFO_16 0x00000DD0

#define	MSR_SKYLAKE_LBR_INFO_17 0x00000DD1

#define	MSR_SKYLAKE_LBR_INFO_18 0x00000DD2

#define	MSR_SKYLAKE_LBR_INFO_19 0x00000DD3

#define	MSR_SKYLAKE_LBR_INFO_20 0x00000DD4

#define	MSR_SKYLAKE_LBR_INFO_21 0x00000DD5

#define	MSR_SKYLAKE_LBR_INFO_22 0x00000DD6

#define	MSR_SKYLAKE_LBR_INFO_23 0x00000DD7

#define	MSR_SKYLAKE_LBR_INFO_24 0x00000DD8

#define	MSR_SKYLAKE_LBR_INFO_25 0x00000DD9

#define	MSR_SKYLAKE_LBR_INFO_26 0x00000DDA

#define	MSR_SKYLAKE_LBR_INFO_27 0x00000DDB

#define	MSR_SKYLAKE_LBR_INFO_28 0x00000DDC

#define	MSR_SKYLAKE_LBR_INFO_29 0x00000DDD

#define	MSR_SKYLAKE_LBR_INFO_30 0x00000DDE

#define	MSR_SKYLAKE_LBR_INFO_31 0x00000DDF

Detailed Description

MSR Definitions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file SkylakeMsr.h.

Macro Definition Documentation

◆ IS_SKYLAKE_PROCESSOR

#define IS_SKYLAKE_PROCESSOR	(	DisplayFamily,
		DisplayModel
	)

Value:

  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x4E || \
    DisplayModel == 0x5E || \
    DisplayModel == 0x55 || \
    DisplayModel == 0x8E || \
    DisplayModel == 0x9E || \
    DisplayModel == 0x66    \
    )                       \
   )

Is Intel processors based on the Skylake microarchitecture?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

Definition at line 32 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_ANY_CORE_C0

#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659

Package. Any Core C0 Residency. (R/O). Increment at the same rate as the TSC. The increment each cycle is one if any processor core in the package is in C0.

Parameters

ECX	MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);

Note: MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.

Definition at line 1034 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_ANY_GFXE_C0

#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A

Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate as the TSC. The increment each cycle is one if any processor graphic device's compute engines are in C0.

Parameters

ECX	MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);

Note: MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.

Definition at line 1053 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_BR_DETECT_CTRL

#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350

Branch Monitoring Global Control (R/W).

Parameters

ECX	MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.

Example usage

MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);
AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);

Definition at line 2667 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_BR_DETECT_STATUS

#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351

Branch Monitoring Global Status (R/W).

Parameters

ECX	MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.

Example usage

MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);
AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);

Definition at line 2752 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_CORE_C1_RESIDENCY

#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660

Core. Core C1 Residency Counter (R/O). Value since last reset for the Core C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC). This counter counts in case both of the core's threads are in an idle state and at least one of the core's thread residency is in a C1 state or in one of its sub states. The counter is updated only after a core C state exit. Note: Always reads 0 if core C1 is unsupported. A value of zero indicates that this processor does not support core C1 or never entered core C1 level state.

Parameters

ECX	MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);

Definition at line 2865 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_CORE_C3_RESIDENCY

#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662

Core. Core C3 Residency Counter (R/O). Will always return 0.

Parameters

ECX	MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);

Definition at line 2881 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0

#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B

Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment at the same rate as the TSC. The increment each cycle is one if at least one compute engine of the processor graphics is in C0 and at least one processor core in the package is also in C0.

Parameters

ECX	MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);

Note: MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.

Definition at line 1073 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_CORE_HDC_RESIDENCY

#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653

Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.

Parameters

ECX	MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);

Note: MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.

Definition at line 960 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS

#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F

Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).

Parameters

ECX	MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);

Note: MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.

Definition at line 738 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_DRAM_ENERGY_STATUS

#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619

Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.

Parameters

ECX	MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.

Example usage

MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);

Definition at line 3451 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_DRAM_PERF_STATUS

#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);

Definition at line 3493 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_DRAM_POWER_INFO

#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C

Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);
AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);

Definition at line 3510 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_DRAM_POWER_LIMIT

#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618

Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);
AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);

Definition at line 3433 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS

#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0

Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) (frequency refers to processor graphics frequency).

Parameters

ECX	MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);

Note: MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.

Definition at line 1247 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_0

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90

Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.

Parameters

ECX	MSR_SKYLAKE_IA32_L3_QOS_MASK_N
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);
AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);

Definition at line 3691 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_1

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91

Definition at line 3692 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_10

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A

Definition at line 3701 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_11

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B

Definition at line 3702 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_12

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C

Definition at line 3703 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_13

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D

Definition at line 3704 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_14

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E

Definition at line 3705 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_15

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F

Definition at line 3706 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_2

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92

Definition at line 3693 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_3

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93

Definition at line 3694 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_4

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94

Definition at line 3695 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_5

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95

Definition at line 3696 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_6

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96

Definition at line 3697 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_7

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97

Definition at line 3698 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_8

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98

Definition at line 3699 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_9

#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99

Definition at line 3700 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_MCG_CAP

#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179

Thread. Global Machine Check Capability (R/O).

Parameters

ECX	MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.

Example usage

MSR_SKYLAKE_IA32_MCG_CAP_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);

Definition at line 3123 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS

#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E

See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".

Parameters

ECX	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.

Example usage

MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);

Note: MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.

Definition at line 261 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET

#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390

See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".

Parameters

ECX	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.

Example usage

MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);

Note: MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.

Definition at line 372 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET

#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391

See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".

Parameters

ECX	MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.

Example usage

MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);

Note: MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.

Definition at line 484 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_PQR_ASSOC

#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F

THREAD. Resource Association Register (R/W).

Parameters

ECX	MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.

Example usage

MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);
AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);

Definition at line 3646 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_IA32_QM_EVTSEL

#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D

THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.

Parameters

ECX	MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.

Example usage

MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);
AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);

Definition at line 3600 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_16_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690

Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.

Parameters

ECX	MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);

Note: MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM. MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.

Definition at line 1210 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_16_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0

Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.

Parameters

ECX	MSR_SKYLAKE_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);

Note: MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM. MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.

Definition at line 1556 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_17_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691

Definition at line 1211 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_17_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1

Definition at line 1557 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_18_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692

Definition at line 1212 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_18_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2

Definition at line 1558 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_19_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693

Definition at line 1213 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_19_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3

Definition at line 1559 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_20_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694

Definition at line 1214 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_20_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4

Definition at line 1560 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_21_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695

Definition at line 1215 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_21_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5

Definition at line 1561 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_22_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696

Definition at line 1216 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_22_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6

Definition at line 1562 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_23_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697

Definition at line 1217 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_23_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7

Definition at line 1563 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_24_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698

Definition at line 1218 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_24_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8

Definition at line 1564 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_25_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699

Definition at line 1219 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_25_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9

Definition at line 1565 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_26_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A

Definition at line 1220 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_26_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA

Definition at line 1566 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_27_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B

Definition at line 1221 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_27_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB

Definition at line 1567 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_28_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C

Definition at line 1222 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_28_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC

Definition at line 1568 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_29_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D

Definition at line 1223 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_29_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD

Definition at line 1569 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_30_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E

Definition at line 1224 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_30_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE

Definition at line 1570 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_31_FROM_IP

#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F

Definition at line 1225 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_31_TO_IP

#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF

Definition at line 1571 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LASTBRANCH_TOS

#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9

Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that points to the MSR containing the most recent branch record.

Parameters

ECX	MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);

Note: MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

Definition at line 121 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_0

#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0

Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".

Parameters

ECX	MSR_SKYLAKE_LBR_INFO_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);

Note: MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM. MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM. MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM. MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM. MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM. MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM. MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM. MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM. MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM. MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM. MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM. MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM. MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM. MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM. MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM. MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM. MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM. MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM. MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM. MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM. MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM. MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM. MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM. MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM. MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM. MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM. MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM. MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM. MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM. MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM. MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM. MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.

Definition at line 1626 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_1

#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1

Definition at line 1627 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_10

#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA

Definition at line 1636 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_11

#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB

Definition at line 1637 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_12

#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC

Definition at line 1638 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_13

#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD

Definition at line 1639 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_14

#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE

Definition at line 1640 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_15

#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF

Definition at line 1641 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_16

#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0

Definition at line 1642 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_17

#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1

Definition at line 1643 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_18

#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2

Definition at line 1644 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_19

#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3

Definition at line 1645 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_2

#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2

Definition at line 1628 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_20

#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4

Definition at line 1646 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_21

#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5

Definition at line 1647 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_22

#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6

Definition at line 1648 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_23

#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7

Definition at line 1649 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_24

#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8

Definition at line 1650 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_25

#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9

Definition at line 1651 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_26

#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA

Definition at line 1652 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_27

#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB

Definition at line 1653 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_28

#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC

Definition at line 1654 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_29

#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD

Definition at line 1655 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_3

#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3

Definition at line 1629 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_30

#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE

Definition at line 1656 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_31

#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF

Definition at line 1657 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_4

#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4

Definition at line 1630 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_5

#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5

Definition at line 1631 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_6

#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6

Definition at line 1632 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_7

#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7

Definition at line 1633 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_8

#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8

Definition at line 1634 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_LBR_INFO_9

#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9

Definition at line 1635 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT

#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620

Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.

Parameters

ECX	MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.

Example usage

MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);
AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);

Definition at line 3532 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PEBS_FRONTEND

#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7

Thread. FrontEnd Precise Event Condition Select (R/W).

Parameters

ECX	MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.

Example usage

MSR_SKYLAKE_PEBS_FRONTEND_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);

Note: MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.

Definition at line 592 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PKG_C3_RESIDENCY

#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8

Package. Package C3 Residency Counter (R/O). Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states.

Parameters

ECX	MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);

Definition at line 2842 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL

#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. <http://biosbits.org/>__.

Parameters

ECX	MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

Definition at line 3034 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PKG_HDC_CONFIG

#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652

Package. HDC Configuration (R/W)..

Parameters

ECX	MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.

Example usage

MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);

Note: MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.

Definition at line 917 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY

#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656

Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.

Parameters

ECX	MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);

Note: MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.

Definition at line 995 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY

#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655

Package. Accumulate the cycles the package was in C2 state and at least one logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.

Parameters

ECX	MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);

Note: MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.

Definition at line 978 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER

#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D

Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both platform vendor hardware implementation and BIOS enablement support it. This MSR will read 0 if not valid.

Parameters

ECX	MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.

Example usage

MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);

Note: MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.

Definition at line 670 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PLATFORM_INFO

#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE

Package. Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org.

Parameters

ECX	MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.

Example usage

MSR_SKYLAKE_PLATFORM_INFO_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);
AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);

Definition at line 2966 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PLATFORM_POWER_LIMIT

#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C

Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor. The processor implements an exponential-weighted algorithm in the placement of the time windows.

Parameters

ECX	MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.

Example usage

MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);

Note: MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.

Definition at line 1099 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_POWER_CTL

#define MSR_SKYLAKE_POWER_CTL 0x000001FC

Core. Power Control Register See http://biosbits.org.

Parameters

ECX	MSR_SKYLAKE_POWER_CTL (0x000001FC)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.

Example usage

MSR_SKYLAKE_POWER_CTL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);

Definition at line 140 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PP0_ENERGY_STATUS [1/2]

#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);

Note: MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

Package. Reserved (R/O) Reads return 0.

Parameters

ECX	MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);

Definition at line 3580 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PP0_ENERGY_STATUS [2/2]

#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);

Note: MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

Package. Reserved (R/O) Reads return 0.

Parameters

ECX	MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);

Definition at line 3580 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PPERF

#define MSR_SKYLAKE_PPERF 0x0000064E

Thread. Productive Performance Count. (R/O). Hardware's view of workload scalability. See Section 14.4.5.1.

Parameters

ECX	MSR_SKYLAKE_PPERF (0x0000064E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);

Note: MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.

Definition at line 717 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PPIN

#define MSR_SKYLAKE_PPIN 0x0000004F

Package. Protected Processor Inventory Number (R/O). Protected Processor Inventory Number (R/O) See Table 2-25.

Parameters

ECX	MSR_SKYLAKE_PPIN (0x0000004F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);

Definition at line 2946 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PPIN_CTL

#define MSR_SKYLAKE_PPIN_CTL 0x0000004E

Package. Protected Processor Inventory Number Enable Control (R/W).

Parameters

ECX	MSR_SKYLAKE_PPIN_CTL (0x0000004E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.

Example usage

MSR_SKYLAKE_PPIN_CTL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);
AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);

Definition at line 2900 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PRMRR_PHYS_BASE

#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4

Core. Processor Reserved Memory Range Register - Physical Base Control Register (R/W).

Parameters

ECX	MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.

Example usage

MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);

Definition at line 2356 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PRMRR_PHYS_MASK

#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5

Core. Processor Reserved Memory Range Register - Physical Mask Control Register (R/W).

Parameters

ECX	MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.

Example usage

MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);

Definition at line 2405 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_PRMRR_VALID_CONFIG

#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB

Core. Valid PRMRR Configurations (R/W).

Parameters

ECX	MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.

Example usage

MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);

Definition at line 2457 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_RAPL_POWER_UNIT

#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606

Package. Unit Multipliers Used in RAPL Interfaces (R/O).

Parameters

ECX	MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.

Example usage

MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);

Definition at line 3376 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_RING_PERF_LIMIT_REASONS

#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1

Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) (frequency refers to ring interconnect in the uncore).

Parameters

ECX	MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);

Note: MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.

Definition at line 1400 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_RING_RATIO_LIMIT

#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620

Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits for the LLC and Ring.

Parameters

ECX	MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.

Example usage

MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);
AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);

Definition at line 2616 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_SGXOWNER0

#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0

Definition at line 214 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_SGXOWNER1

#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1

Definition at line 240 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_SGXOWNEREPOCH0

#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300

Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. Lower 64 bits of an 128-bit external entropy value for key derivation of an enclave.

Parameters

ECX	MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = 0;
AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);

Note: MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.

Definition at line 209 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_SGXOWNEREPOCH1

#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301

Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. Upper 64 bits of an 128-bit external entropy value for key derivation of an enclave.

Parameters

ECX	MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = 0;
AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);

Note: MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.

Definition at line 235 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_SMM_MCA_CAP

#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D

THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters

ECX	MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.

Example usage

MSR_SKYLAKE_SMM_MCA_CAP_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);
AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);

Definition at line 3201 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_TEMPERATURE_TARGET

#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2

Package. Temperature Target.

Parameters

ECX	MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.

Example usage

MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);
AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);

Definition at line 3250 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE

#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080

Package. NPK Address Used by AET Messages (R/W).

Parameters

ECX	MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.

Example usage

MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);

Definition at line 2305 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_TURBO_RATIO_LIMIT

#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);

Note: MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

Definition at line 62 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES

#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE

Package. This register defines the active core ranges for each frequency point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored. The last valid entry must have NUMCORE >= the number of cores in the SKU. If any of the rules above are broken, the configuration is silently rejected.

Parameters

ECX	MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.

Example usage

MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);
AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);

Definition at line 3303 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_ARB_PERFCTR0

#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0

Package. Uncore Arb unit, performance counter 0.

Parameters

ECX	MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);

Note: MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.

Definition at line 1816 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_ARB_PERFCTR1

#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1

Package. Uncore Arb unit, performance counter 1.

Parameters

ECX	MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);

Note: MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.

Definition at line 1834 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0

#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2

Package. Uncore Arb unit, counter 0 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);

Note: MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.

Definition at line 1852 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1

#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3

Package. Uncore Arb unit, counter 1 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);

Note: MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.

Definition at line 1870 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_0_PERFCTR0

#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706

Package. Uncore C-Box 0, performance counter 0.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);

Note: MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.

Definition at line 1924 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_0_PERFCTR1

#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707

Package. Uncore C-Box 0, performance counter 1.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);

Note: MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.

Definition at line 1942 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0

#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700

Package. Uncore C-Box 0, counter 0 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);

Note: MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.

Definition at line 1888 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1

#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701

Package. Uncore C-Box 0, counter 1 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);

Note: MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.

Definition at line 1906 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_1_PERFCTR0

#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716

Package. Uncore C-Box 1, performance counter 0.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);

Note: MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.

Definition at line 1996 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_1_PERFCTR1

#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717

Package. Uncore C-Box 1, performance counter 1.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);

Note: MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.

Definition at line 2014 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0

#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710

Package. Uncore C-Box 1, counter 0 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);

Note: MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.

Definition at line 1960 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1

#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711

Package. Uncore C-Box 1, counter 1 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);

Note: MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.

Definition at line 1978 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_2_PERFCTR0

#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726

Package. Uncore C-Box 2, performance counter 0.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);

Note: MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.

Definition at line 2068 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_2_PERFCTR1

#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727

Package. Uncore C-Box 2, performance counter 1.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);

Note: MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.

Definition at line 2086 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0

#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720

Package. Uncore C-Box 2, counter 0 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);

Note: MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.

Definition at line 2032 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1

#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721

Package. Uncore C-Box 2, counter 1 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);

Note: MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.

Definition at line 2050 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_3_PERFCTR0

#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736

Package. Uncore C-Box 3, performance counter 0.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);

Note: MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.

Definition at line 2140 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_3_PERFCTR1

#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737

Package. Uncore C-Box 3, performance counter 1.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);

Note: MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.

Definition at line 2158 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0

#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730

Package. Uncore C-Box 3, counter 0 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);

Note: MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.

Definition at line 2104 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1

#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731

Package. Uncore C-Box 3, counter 1 event select MSR.

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);

Note: MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.

Definition at line 2122 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_CBO_CONFIG

#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396

Package. Uncore C-Box configuration information (R/O).

Parameters

ECX	MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.

Example usage

MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);

Note: MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.

Definition at line 1772 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_PERF_FIXED_CTR

#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395

Package. Uncore fixed counter.

Parameters

ECX	MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.

Example usage

MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);

Note: MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.

Definition at line 1729 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_PERF_FIXED_CTRL

#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394

Package. Uncore fixed counter control (R/W).

Parameters

ECX	MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.

Example usage

MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);

Note: MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.

Definition at line 1678 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL

#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01

Package. Uncore PMU global control.

Parameters

ECX	MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.

Example usage

MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);

Note: MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.

Definition at line 2178 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS

#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02

Package. Uncore PMU main status.

Parameters

ECX	MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.

Example usage

MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);

Note: MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.

Definition at line 2252 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE

#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4

Package. (R/W) The PRMRR range is used to protect Xucode memory from unauthorized reads and writes. Any IO access to this range is aborted. This register controls the location of the PRMRR range by indicating its starting address. It functions in tandem with the PRMRR mask register.

Parameters

ECX	MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.

Example usage

MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);
AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);

Definition at line 2517 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK

#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5

Package. (R/W) This register controls the size of the PRMRR range by indicating which address bits must match the PRMRR base register value.

Parameters

ECX	MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)
EAX	Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.

Example usage

MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER  Msr;
 
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);
AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);

Definition at line 2564 of file SkylakeMsr.h.

◆ MSR_SKYLAKE_WEIGHTED_CORE_C0

#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658

Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate as the TSC. The increment each cycle is weighted by the number of processor cores in the package that reside in C0. If N cores are simultaneously in C0, then each cycle the counter increments by N.

Parameters

ECX	MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
 
Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);

Note: MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.

Definition at line 1015 of file SkylakeMsr.h.

Data Structures

Macros

Detailed Description

Macro Definition Documentation

◆ IS_SKYLAKE_PROCESSOR

◆ MSR_SKYLAKE_ANY_CORE_C0

◆ MSR_SKYLAKE_ANY_GFXE_C0

◆ MSR_SKYLAKE_BR_DETECT_CTRL

◆ MSR_SKYLAKE_BR_DETECT_STATUS

◆ MSR_SKYLAKE_CORE_C1_RESIDENCY

◆ MSR_SKYLAKE_CORE_C3_RESIDENCY

◆ MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0

◆ MSR_SKYLAKE_CORE_HDC_RESIDENCY

◆ MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS

◆ MSR_SKYLAKE_DRAM_ENERGY_STATUS

◆ MSR_SKYLAKE_DRAM_PERF_STATUS

◆ MSR_SKYLAKE_DRAM_POWER_INFO

◆ MSR_SKYLAKE_DRAM_POWER_LIMIT

◆ MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_0

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_1

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_10

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_11

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_12

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_13

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_14

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_15

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_2

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_3

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_4

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_5

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_6

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_7

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_8

◆ MSR_SKYLAKE_IA32_L3_QOS_MASK_9

◆ MSR_SKYLAKE_IA32_MCG_CAP

◆ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS

◆ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET

◆ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET

◆ MSR_SKYLAKE_IA32_PQR_ASSOC

◆ MSR_SKYLAKE_IA32_QM_EVTSEL

◆ MSR_SKYLAKE_LASTBRANCH_16_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_16_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_17_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_17_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_18_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_18_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_19_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_19_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_20_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_20_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_21_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_21_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_22_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_22_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_23_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_23_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_24_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_24_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_25_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_25_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_26_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_26_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_27_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_27_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_28_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_28_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_29_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_29_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_30_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_30_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_31_FROM_IP

◆ MSR_SKYLAKE_LASTBRANCH_31_TO_IP

◆ MSR_SKYLAKE_LASTBRANCH_TOS

◆ MSR_SKYLAKE_LBR_INFO_0

◆ MSR_SKYLAKE_LBR_INFO_1

◆ MSR_SKYLAKE_LBR_INFO_10

◆ MSR_SKYLAKE_LBR_INFO_11

◆ MSR_SKYLAKE_LBR_INFO_12

◆ MSR_SKYLAKE_LBR_INFO_13