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XeonPhiMsr.h File Reference

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Data Structures

union  MSR_XEON_PHI_SMI_COUNT_REGISTER
 
union  MSR_XEON_PHI_PPIN_CTL_REGISTER
 
union  MSR_XEON_PHI_PLATFORM_INFO_REGISTER
 
union  MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
 
union  MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
 
union  MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
 
union  MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
 
union  MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
 
union  MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
 
union  MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
 
union  MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
 
union  MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
 
union  MSR_XEON_PHI_LBR_SELECT_REGISTER
 
union  MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
 
union  MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
 
union  MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
 

Macros

#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_XEON_PHI_SMI_COUNT   0x00000034
 
#define MSR_XEON_PHI_PPIN_CTL   0x0000004E
 
#define MSR_XEON_PHI_PPIN   0x0000004F
 
#define MSR_XEON_PHI_PLATFORM_INFO   0x000000CE
 
#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL   0x000000E2
 
#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE   0x000000E4
 
#define MSR_XEON_PHI_FEATURE_CONFIG   0x0000013C
 
#define MSR_XEON_PHI_MISC_FEATURE_ENABLES   0x00000140
 
#define MSR_XEON_PHI_SMM_MCA_CAP   0x0000017D
 
#define MSR_XEON_PHI_IA32_MISC_ENABLE   0x000001A0
 
#define MSR_XEON_PHI_TEMPERATURE_TARGET   0x000001A2
 
#define MSR_XEON_PHI_MISC_FEATURE_CONTROL   0x000001A4
 
#define MSR_XEON_PHI_OFFCORE_RSP_0   0x000001A6
 
#define MSR_XEON_PHI_OFFCORE_RSP_1   0x000001A7
 
#define MSR_XEON_PHI_TURBO_RATIO_LIMIT   0x000001AD
 
#define MSR_XEON_PHI_LBR_SELECT   0x000001C8
 
#define MSR_XEON_PHI_LASTBRANCH_TOS   0x000001C9
 
#define MSR_XEON_PHI_LER_FROM_LIP   0x000001DD
 
#define MSR_XEON_PHI_LER_TO_LIP   0x000001DE
 
#define MSR_XEON_PHI_PEBS_ENABLE   0x000003F1
 
#define MSR_XEON_PHI_PKG_C3_RESIDENCY   0x000003F8
 
#define MSR_XEON_PHI_PKG_C6_RESIDENCY   0x000003F9
 
#define MSR_XEON_PHI_PKG_C7_RESIDENCY   0x000003FA
 
#define MSR_XEON_PHI_MC0_RESIDENCY   0x000003FC
 
#define MSR_XEON_PHI_MC6_RESIDENCY   0x000003FD
 
#define MSR_XEON_PHI_CORE_C6_RESIDENCY   0x000003FF
 
#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM   0x0000048C
 
#define MSR_XEON_PHI_IA32_VMX_FMFUNC   0x00000491
 
#define MSR_XEON_PHI_RAPL_POWER_UNIT   0x00000606
 
#define MSR_XEON_PHI_PKG_C2_RESIDENCY   0x0000060D
 
#define MSR_XEON_PHI_PKG_POWER_LIMIT   0x00000610
 
#define MSR_XEON_PHI_PKG_ENERGY_STATUS   0x00000611
 
#define MSR_XEON_PHI_PKG_PERF_STATUS   0x00000613
 
#define MSR_XEON_PHI_PKG_POWER_INFO   0x00000614
 
#define MSR_XEON_PHI_DRAM_POWER_LIMIT   0x00000618
 
#define MSR_XEON_PHI_DRAM_ENERGY_STATUS   0x00000619
 
#define MSR_XEON_PHI_DRAM_PERF_STATUS   0x0000061B
 
#define MSR_XEON_PHI_DRAM_POWER_INFO   0x0000061C
 
#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT   0x00000620
 
#define MSR_XEON_PHI_PP0_POWER_LIMIT   0x00000638
 
#define MSR_XEON_PHI_PP0_ENERGY_STATUS   0x00000639
 
#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL   0x00000648
 
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1   0x00000649
 
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2   0x0000064A
 
#define MSR_XEON_PHI_CONFIG_TDP_CONTROL   0x0000064B
 
#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO   0x0000064C
 
#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS   0x00000690
 

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file XeonPhiMsr.h.

Macro Definition Documentation

◆ IS_XEON_PHI_PROCESSOR

#define IS_XEON_PHI_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x57 || \
DisplayModel == 0x85 \
) \
)

Is Intel(R) Xeon(R) Phi(TM) processor Family?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.

Definition at line 32 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_CONFIG_TDP_CONTROL

#define MSR_XEON_PHI_CONFIG_TDP_CONTROL   0x0000064B

Package. ConfigTDP Control (R/W) See Table 2-24.

Parameters
ECXMSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
#define MSR_XEON_PHI_CONFIG_TDP_CONTROL
Definition: XeonPhiMsr.h:1550
Note
MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.

Definition at line 1550 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_CONFIG_TDP_LEVEL1

#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1   0x00000649

Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.

Parameters
ECXMSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1
Definition: XeonPhiMsr.h:1515
Note
MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.

Definition at line 1515 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_CONFIG_TDP_LEVEL2

#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2   0x0000064A

Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.

Parameters
ECXMSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2
Definition: XeonPhiMsr.h:1532
Note
MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.

Definition at line 1532 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_CONFIG_TDP_NOMINAL

#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL   0x00000648

Package. Base TDP Ratio (R/O) See Table 2-24.

Parameters
ECXMSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL
Definition: XeonPhiMsr.h:1498
Note
MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.

Definition at line 1498 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_CORE_C6_RESIDENCY

#define MSR_XEON_PHI_CORE_C6_RESIDENCY   0x000003FF

Core. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6 Residency Counter. (R/O).

Parameters
ECXMSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.

Definition at line 1133 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS

#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS   0x00000690

Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).

Parameters
ECXMSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.

Example usage

Note
MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.

Definition at line 1589 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_DRAM_ENERGY_STATUS

#define MSR_XEON_PHI_DRAM_ENERGY_STATUS   0x00000619

Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_DRAM_ENERGY_STATUS
Definition: XeonPhiMsr.h:1354
Note
MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.

Definition at line 1354 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_DRAM_PERF_STATUS

#define MSR_XEON_PHI_DRAM_PERF_STATUS   0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_DRAM_PERF_STATUS
Definition: XeonPhiMsr.h:1372
Note
MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.

Definition at line 1372 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_DRAM_POWER_INFO

#define MSR_XEON_PHI_DRAM_POWER_INFO   0x0000061C

Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.

Definition at line 1390 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_DRAM_POWER_LIMIT

#define MSR_XEON_PHI_DRAM_POWER_LIMIT   0x00000618

Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.

Definition at line 1337 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_FEATURE_CONFIG

#define MSR_XEON_PHI_FEATURE_CONFIG   0x0000013C

Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

Parameters
ECXMSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.

Example usage

Note
MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.

Definition at line 374 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_IA32_MISC_ENABLE

#define MSR_XEON_PHI_IA32_MISC_ENABLE   0x000001A0

Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters
ECXMSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.

Example usage

Note
MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

Definition at line 541 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM

#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM   0x0000048C

Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.

Parameters
ECXMSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM
Definition: XeonPhiMsr.h:1150
Note
MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.

Definition at line 1150 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_IA32_VMX_FMFUNC

#define MSR_XEON_PHI_IA32_VMX_FMFUNC   0x00000491

Core. Capability Reporting Register of VM-Function Controls (R/O) See Table 2-2.

Parameters
ECXMSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_IA32_VMX_FMFUNC
Definition: XeonPhiMsr.h:1168
Note
MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.

Definition at line 1168 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_LASTBRANCH_TOS

#define MSR_XEON_PHI_LASTBRANCH_TOS   0x000001C9

Thread. Last Branch Record Stack TOS (R/W).

Parameters
ECXMSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

Definition at line 967 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_LBR_SELECT

#define MSR_XEON_PHI_LBR_SELECT   0x000001C8

Thread. Last Branch Record Filtering Select Register (R/W).

Parameters
ECXMSR_XEON_PHI_LBR_SELECT (0x000001C8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_LBR_SELECT
Definition: XeonPhiMsr.h:892
Note
MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.

Definition at line 892 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_LER_FROM_LIP

#define MSR_XEON_PHI_LER_FROM_LIP   0x000001DD

Thread. Last Exception Record From Linear IP (R).

Parameters
ECXMSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_LER_FROM_LIP
Definition: XeonPhiMsr.h:984
Note
MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

Definition at line 984 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_LER_TO_LIP

#define MSR_XEON_PHI_LER_TO_LIP   0x000001DE

Thread. Last Exception Record To Linear IP (R).

Parameters
ECXMSR_XEON_PHI_LER_TO_LIP (0x000001DE)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_LER_TO_LIP
Definition: XeonPhiMsr.h:1001
Note
MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

Definition at line 1001 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_MC0_RESIDENCY

#define MSR_XEON_PHI_MC0_RESIDENCY   0x000003FC

Module. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0 Residency Counter. (R/O).

Parameters
ECXMSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_MC0_RESIDENCY
Definition: XeonPhiMsr.h:1095
Note
MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.

Definition at line 1095 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_MC6_RESIDENCY

#define MSR_XEON_PHI_MC6_RESIDENCY   0x000003FD

Module. Module C6 Residency Counter. (R/O).

Parameters
ECXMSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_MC6_RESIDENCY
Definition: XeonPhiMsr.h:1113
Note
MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.

Definition at line 1113 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_MISC_FEATURE_CONTROL

#define MSR_XEON_PHI_MISC_FEATURE_CONTROL   0x000001A4

Miscellaneous Feature Control (R/W).

Parameters
ECXMSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.

Example usage

Note
MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.

Definition at line 681 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_MISC_FEATURE_ENABLES

#define MSR_XEON_PHI_MISC_FEATURE_ENABLES   0x00000140

Thread. MISC_FEATURE_ENABLES.

Parameters
ECXMSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.

Example usage

Definition at line 424 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT

#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT   0x00000620

Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.

Parameters
ECXMSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.

Example usage

Definition at line 1412 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_OFFCORE_RSP_0

#define MSR_XEON_PHI_OFFCORE_RSP_0   0x000001A6

Shared. Offcore Response Event Select Register (R/W).

Parameters
ECXMSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_OFFCORE_RSP_0
Definition: XeonPhiMsr.h:730
Note
MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.

Definition at line 730 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_OFFCORE_RSP_1

#define MSR_XEON_PHI_OFFCORE_RSP_1   0x000001A7

Shared. Offcore Response Event Select Register (R/W).

Parameters
ECXMSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_OFFCORE_RSP_1
Definition: XeonPhiMsr.h:748
Note
MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.

Definition at line 748 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PEBS_ENABLE

#define MSR_XEON_PHI_PEBS_ENABLE   0x000003F1

Thread. See Table 2-2.

Parameters
ECXMSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_PEBS_ENABLE
Definition: XeonPhiMsr.h:1019
Note
MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.

Definition at line 1019 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_C2_RESIDENCY

#define MSR_XEON_PHI_PKG_C2_RESIDENCY   0x0000060D

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2 Residency Counter. (R/O).

Parameters
ECXMSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.

Definition at line 1246 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_C3_RESIDENCY

#define MSR_XEON_PHI_PKG_C3_RESIDENCY   0x000003F8

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3 Residency Counter. (R/O).

Parameters
ECXMSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.

Definition at line 1039 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_C6_RESIDENCY

#define MSR_XEON_PHI_PKG_C6_RESIDENCY   0x000003F9

Package. Package C6 Residency Counter. (R/O).

Parameters
ECXMSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.

Definition at line 1057 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_C7_RESIDENCY

#define MSR_XEON_PHI_PKG_C7_RESIDENCY   0x000003FA

Package. Package C7 Residency Counter. (R/O).

Parameters
ECXMSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.

Definition at line 1075 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL

#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL   0x000000E2

Module. C-State Configuration Control (R/W).

Parameters
ECXMSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

Note
MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

Definition at line 247 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_ENERGY_STATUS

#define MSR_XEON_PHI_PKG_ENERGY_STATUS   0x00000611

Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".

Parameters
ECXMSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_PKG_ENERGY_STATUS
Definition: XeonPhiMsr.h:1282
Note
MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.

Definition at line 1282 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_PERF_STATUS

#define MSR_XEON_PHI_PKG_PERF_STATUS   0x00000613

Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".

Parameters
ECXMSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_PKG_PERF_STATUS
Definition: XeonPhiMsr.h:1299
Note
MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.

Definition at line 1299 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_POWER_INFO

#define MSR_XEON_PHI_PKG_POWER_INFO   0x00000614

Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL Domain.".

Parameters
ECXMSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.

Definition at line 1318 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PKG_POWER_LIMIT

#define MSR_XEON_PHI_PKG_POWER_LIMIT   0x00000610

Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package RAPL Domain.".

Parameters
ECXMSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.

Definition at line 1265 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PLATFORM_INFO

#define MSR_XEON_PHI_PLATFORM_INFO   0x000000CE

Package. Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org.

Parameters
ECXMSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.

Example usage

Note
MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.

Definition at line 181 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PMG_IO_CAPTURE_BASE

#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE   0x000000E4

Module. Power Management IO Redirection in C-state (R/W).

Parameters
ECXMSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.

Example usage

Note
MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.

Definition at line 322 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PP0_ENERGY_STATUS

#define MSR_XEON_PHI_PP0_ENERGY_STATUS   0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters
ECXMSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_PP0_ENERGY_STATUS
Definition: XeonPhiMsr.h:1481
Note
MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

Definition at line 1481 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PP0_POWER_LIMIT

#define MSR_XEON_PHI_PP0_POWER_LIMIT   0x00000638

Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters
ECXMSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.

Definition at line 1463 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PPIN

#define MSR_XEON_PHI_PPIN   0x0000004F

Package. Protected Processor Inventory Number (R/O). Protected Processor Inventory Number (R/O) A unique value within a given CPUID family/model/stepping signature that a privileged inventory initialization agent can access to identify each physical processor, when access to MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if MSR_PPIN_CTL[bits 1:0] = '10b'.

Parameters
ECXMSR_XEON_PHI_PPIN (0x0000004F)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_XEON_PHI_PPIN
Definition: XeonPhiMsr.h:160

Definition at line 160 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_PPIN_CTL

#define MSR_XEON_PHI_PPIN_CTL   0x0000004E

Package. Protected Processor Inventory Number Enable Control (R/W).

Parameters
ECXMSR_XEON_PHI_PPIN_CTL (0x0000004E)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.

Example usage

Definition at line 100 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_RAPL_POWER_UNIT

#define MSR_XEON_PHI_RAPL_POWER_UNIT   0x00000606

Package. Unit Multipliers used in RAPL Interfaces (R/O).

Parameters
ECXMSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.

Example usage

Note
MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.

Definition at line 1187 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_SMI_COUNT

#define MSR_XEON_PHI_SMI_COUNT   0x00000034

Thread. SMI Counter (R/O).

Parameters
ECXMSR_XEON_PHI_SMI_COUNT (0x00000034)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.

Example usage

Note
MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.

Definition at line 57 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_SMM_MCA_CAP

#define MSR_XEON_PHI_SMM_MCA_CAP   0x0000017D

THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters
ECXMSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.

Example usage

Note
MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.

Definition at line 476 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_TEMPERATURE_TARGET

#define MSR_XEON_PHI_TEMPERATURE_TARGET   0x000001A2

Package.

Parameters
ECXMSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.

Example usage

Note
MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.

Definition at line 631 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_TURBO_ACTIVATION_RATIO

#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO   0x0000064C

Package. ConfigTDP Control (R/W) See Table 2-24.

Parameters
ECXMSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.

Definition at line 1568 of file XeonPhiMsr.h.

◆ MSR_XEON_PHI_TURBO_RATIO_LIMIT

#define MSR_XEON_PHI_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).

Parameters
ECXMSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.

Example usage

Note
MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

Definition at line 768 of file XeonPhiMsr.h.