TianoCore EDK2 master
XeonPhiMsr.h
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1
18#ifndef __XEON_PHI_MSR_H__
19#define __XEON_PHI_MSR_H__
20
22
32#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x57 || \
36 DisplayModel == 0x85 \
37 ) \
38 )
39
57#define MSR_XEON_PHI_SMI_COUNT 0x00000034
58
62typedef union {
66 struct {
70 UINT32 SMICount : 32;
71 UINT32 Reserved : 32;
72 } Bits;
76 UINT32 Uint32;
80 UINT64 Uint64;
82
100#define MSR_XEON_PHI_PPIN_CTL 0x0000004E
101
105typedef union {
109 struct {
120 UINT32 LockOut : 1;
127 UINT32 Enable_PPIN : 1;
128 UINT32 Reserved1 : 30;
129 UINT32 Reserved2 : 32;
130 } Bits;
134 UINT32 Uint32;
138 UINT64 Uint64;
140
160#define MSR_XEON_PHI_PPIN 0x0000004F
161
181#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
182
186typedef union {
190 struct {
191 UINT32 Reserved1 : 8;
198 UINT32 Reserved2 : 12;
205 UINT32 RatioLimit : 1;
212 UINT32 TDPLimit : 1;
213 UINT32 Reserved3 : 2;
214 UINT32 Reserved4 : 8;
221 UINT32 Reserved5 : 16;
222 } Bits;
226 UINT64 Uint64;
228
247#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
248
252typedef union {
256 struct {
262 UINT32 Limit : 3;
263 UINT32 Reserved1 : 7;
267 UINT32 IO_MWAIT : 1;
268 UINT32 Reserved2 : 4;
272 UINT32 CFGLock : 1;
273 UINT32 Reserved5 : 10;
280 UINT32 Reserved6 : 1;
291 UINT32 Reserved7 : 2;
292 UINT32 Reserved4 : 32;
293 } Bits;
297 UINT32 Uint32;
301 UINT64 Uint64;
303
322#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
323
327typedef union {
331 struct {
335 UINT32 Lvl2Base : 16;
341 UINT32 CStateRange : 7;
342 UINT32 Reserved3 : 9;
343 UINT32 Reserved2 : 32;
344 } Bits;
348 UINT32 Uint32;
352 UINT64 Uint64;
354
374#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
375
379typedef union {
383 struct {
394 UINT32 Reserved1 : 30;
395 UINT32 Reserved2 : 32;
396 } Bits;
400 UINT32 Uint32;
404 UINT64 Uint64;
406
424#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
425
429typedef union {
433 struct {
434 UINT32 Reserved1 : 1;
444 UINT32 Reserved2 : 30;
445 UINT32 Reserved3 : 32;
446 } Bits;
450 UINT32 Uint32;
454 UINT64 Uint64;
456
476#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
477
481typedef union {
485 struct {
491 UINT32 BankSupport : 32;
492 UINT32 Reserved4 : 24;
496 UINT32 TargetedSMI : 1;
501 UINT32 SMM_CPU_SVRSTR : 1;
514 UINT32 Reserved3 : 4;
515 } Bits;
519 UINT64 Uint64;
521
541#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
542
546typedef union {
550 struct {
554 UINT32 FastStrings : 1;
555 UINT32 Reserved1 : 2;
561 UINT32 Reserved2 : 3;
566 UINT32 Reserved3 : 3;
570 UINT32 BTS : 1;
574 UINT32 PEBS : 1;
575 UINT32 Reserved4 : 3;
579 UINT32 EIST : 1;
580 UINT32 Reserved5 : 1;
584 UINT32 MONITOR : 1;
585 UINT32 Reserved6 : 3;
594 UINT32 Reserved7 : 8;
595 UINT32 Reserved8 : 2;
599 UINT32 XD : 1;
600 UINT32 Reserved9 : 3;
605 UINT32 Reserved10 : 25;
606 } Bits;
610 UINT64 Uint64;
612
631#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
632
636typedef union {
640 struct {
641 UINT32 Reserved1 : 16;
649 UINT32 TargetOffset : 6;
650 UINT32 Reserved2 : 2;
651 UINT32 Reserved3 : 32;
652 } Bits;
656 UINT32 Uint32;
660 UINT64 Uint64;
662
681#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
682
686typedef union {
690 struct {
701 UINT32 Reserved1 : 30;
702 UINT32 Reserved2 : 32;
703 } Bits;
707 UINT32 Uint32;
711 UINT64 Uint64;
713
730#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
731
748#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
749
768#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
769
773typedef union {
777 struct {
778 UINT32 Reserved : 1;
784 UINT32 MaxCoresGroup0 : 7;
869 } Bits;
873 UINT64 Uint64;
875
892#define MSR_XEON_PHI_LBR_SELECT 0x000001C8
893
897typedef union {
901 struct {
905 UINT32 CPL_EQ_0 : 1;
909 UINT32 CPL_NEQ_0 : 1;
913 UINT32 JCC : 1;
917 UINT32 NEAR_REL_CALL : 1;
921 UINT32 NEAR_IND_CALL : 1;
925 UINT32 NEAR_RET : 1;
929 UINT32 NEAR_IND_JMP : 1;
933 UINT32 NEAR_REL_JMP : 1;
937 UINT32 FAR_BRANCH : 1;
938 UINT32 Reserved1 : 23;
939 UINT32 Reserved2 : 32;
940 } Bits;
944 UINT32 Uint32;
948 UINT64 Uint64;
950
967#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
968
984#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
985
1001#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
1002
1019#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
1020
1039#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
1040
1057#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
1058
1075#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
1076
1095#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
1096
1113#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
1114
1133#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
1134
1150#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1151
1168#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
1169
1187#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
1188
1192typedef union {
1196 struct {
1200 UINT32 PowerUnits : 4;
1201 UINT32 Reserved1 : 4;
1209 UINT32 Reserved2 : 3;
1214 UINT32 TimeUnits : 4;
1215 UINT32 Reserved3 : 12;
1216 UINT32 Reserved4 : 32;
1217 } Bits;
1221 UINT32 Uint32;
1225 UINT64 Uint64;
1227
1246#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
1247
1265#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
1266
1282#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
1283
1299#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
1300
1318#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
1319
1337#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
1338
1354#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
1355
1372#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
1373
1390#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
1391
1412#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
1413
1417typedef union {
1421 struct {
1426 UINT32 MAX_RATIO : 7;
1427 UINT32 Reserved1 : 1;
1432 UINT32 MIN_RATIO : 7;
1433 UINT32 Reserved2 : 17;
1434 UINT32 Reserved3 : 32;
1435 } Bits;
1439 UINT32 Uint32;
1443 UINT64 Uint64;
1445
1463#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
1464
1481#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
1482
1498#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
1499
1515#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
1516
1532#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
1533
1550#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
1551
1568#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
1569
1589#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
1590
1594typedef union {
1598 struct {
1602 UINT32 PROCHOT_Status : 1;
1606 UINT32 ThermalStatus : 1;
1607 UINT32 Reserved1 : 4;
1612 UINT32 Reserved2 : 1;
1617 UINT32 Reserved3 : 23;
1618 UINT32 Reserved4 : 32;
1619 } Bits;
1623 UINT32 Uint32;
1627 UINT64 Uint64;
1629
1630#endif