XeonPhiMsr.h

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#ifndef __XEON_PHI_MSR_H__
#define __XEON_PHI_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x57 || \
    DisplayModel == 0x85    \
    )                       \
   )
 
#define MSR_XEON_PHI_SMI_COUNT  0x00000034
 
typedef union {
  struct {
    UINT32    SMICount : 32;
    UINT32    Reserved : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_SMI_COUNT_REGISTER;
 
#define MSR_XEON_PHI_PPIN_CTL  0x0000004E
 
typedef union {
  struct {
    UINT32    LockOut     : 1;
    UINT32    Enable_PPIN : 1;
    UINT32    Reserved1   : 30;
    UINT32    Reserved2   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_PPIN_CTL_REGISTER;
 
#define MSR_XEON_PHI_PPIN  0x0000004F
 
#define MSR_XEON_PHI_PLATFORM_INFO  0x000000CE
 
typedef union {
  struct {
    UINT32    Reserved1              : 8;
    UINT32    MaximumNonTurboRatio   : 8;
    UINT32    Reserved2              : 12;
    UINT32    RatioLimit             : 1;
    UINT32    TDPLimit               : 1;
    UINT32    Reserved3              : 2;
    UINT32    Reserved4              : 8;
    UINT32    MaximumEfficiencyRatio : 8;
    UINT32    Reserved5              : 16;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
 
#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL  0x000000E2
 
typedef union {
  struct {
    UINT32    Limit                        : 3;
    UINT32    Reserved1                    : 7;
    UINT32    IO_MWAIT                     : 1;
    UINT32    Reserved2                    : 4;
    UINT32    CFGLock                      : 1;
    UINT32    Reserved5                    : 10;
    UINT32    C1StateAutoDemotionEnable    : 1;
    UINT32    Reserved6                    : 1;
    UINT32    C1StateAutoUndemotionEnable  : 1;
    UINT32    PKGC_StateAutoDemotionEnable : 1;
    UINT32    Reserved7                    : 2;
    UINT32    Reserved4                    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;
 
#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE  0x000000E4
 
typedef union {
  struct {
    UINT32    Lvl2Base    : 16;
    UINT32    CStateRange : 7;
    UINT32    Reserved3   : 9;
    UINT32    Reserved2   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
 
#define MSR_XEON_PHI_FEATURE_CONFIG  0x0000013C
 
typedef union {
  struct {
    UINT32    AESConfiguration : 2;
    UINT32    Reserved1        : 30;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
 
#define MSR_XEON_PHI_MISC_FEATURE_ENABLES  0x00000140
 
typedef union {
  struct {
    UINT32    Reserved1 : 1;
    UINT32    UserModeMonitorAndMwait : 1;
    UINT32    Reserved2               : 30;
    UINT32    Reserved3               : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;
 
#define MSR_XEON_PHI_SMM_MCA_CAP  0x0000017D
 
typedef union {
  struct {
    UINT32    BankSupport          : 32;
    UINT32    Reserved4            : 24;
    UINT32    TargetedSMI          : 1;
    UINT32    SMM_CPU_SVRSTR       : 1;
    UINT32    SMM_Code_Access_Chk  : 1;
    UINT32    Long_Flow_Indication : 1;
    UINT32    Reserved3            : 4;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;
 
#define MSR_XEON_PHI_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    FastStrings                    : 1;
    UINT32    Reserved1                      : 2;
    UINT32    AutomaticThermalControlCircuit : 1;
    UINT32    Reserved2                      : 3;
    UINT32    PerformanceMonitoring          : 1;
    UINT32    Reserved3                      : 3;
    UINT32    BTS                            : 1;
    UINT32    PEBS                           : 1;
    UINT32    Reserved4                      : 3;
    UINT32    EIST                           : 1;
    UINT32    Reserved5                      : 1;
    UINT32    MONITOR                        : 1;
    UINT32    Reserved6                      : 3;
    UINT32    LimitCpuidMaxval               : 1;
    UINT32    xTPR_Message_Disable           : 1;
    UINT32    Reserved7                      : 8;
    UINT32    Reserved8                      : 2;
    UINT32    XD                             : 1;
    UINT32    Reserved9                      : 3;
    UINT32    TurboModeDisable               : 1;
    UINT32    Reserved10                     : 25;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_XEON_PHI_TEMPERATURE_TARGET  0x000001A2
 
typedef union {
  struct {
    UINT32    Reserved1         : 16;
    UINT32    TemperatureTarget : 8;
    UINT32    TargetOffset      : 6;
    UINT32    Reserved2         : 2;
    UINT32    Reserved3         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;
 
#define MSR_XEON_PHI_MISC_FEATURE_CONTROL  0x000001A4
 
typedef union {
  struct {
    UINT32    DCUHardwarePrefetcherDisable : 1;
    UINT32    L2HardwarePrefetcherDisable  : 1;
    UINT32    Reserved1                    : 30;
    UINT32    Reserved2                    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;
 
#define MSR_XEON_PHI_OFFCORE_RSP_0  0x000001A6
 
#define MSR_XEON_PHI_OFFCORE_RSP_1  0x000001A7
 
#define MSR_XEON_PHI_TURBO_RATIO_LIMIT  0x000001AD
 
typedef union {
  struct {
    UINT32    Reserved                  : 1;
    UINT32    MaxCoresGroup0            : 7;
    UINT32    MaxRatioLimitGroup0       : 8;
    UINT32    MaxIncrementalCoresGroup1 : 5;
    UINT32    DeltaRatioGroup1          : 3;
    UINT32    MaxIncrementalCoresGroup2 : 5;
    UINT32    DeltaRatioGroup2          : 3;
    UINT32    MaxIncrementalCoresGroup3 : 5;
    UINT32    DeltaRatioGroup3          : 3;
    UINT32    MaxIncrementalCoresGroup4 : 5;
    UINT32    DeltaRatioGroup4          : 3;
    UINT32    MaxIncrementalCoresGroup5 : 5;
    UINT32    DeltaRatioGroup5          : 3;
    UINT32    MaxIncrementalCoresGroup6 : 5;
    UINT32    DeltaRatioGroup6          : 3;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;
 
#define MSR_XEON_PHI_LBR_SELECT  0x000001C8
 
typedef union {
  struct {
    UINT32    CPL_EQ_0      : 1;
    UINT32    CPL_NEQ_0     : 1;
    UINT32    JCC           : 1;
    UINT32    NEAR_REL_CALL : 1;
    UINT32    NEAR_IND_CALL : 1;
    UINT32    NEAR_RET      : 1;
    UINT32    NEAR_IND_JMP  : 1;
    UINT32    NEAR_REL_JMP  : 1;
    UINT32    FAR_BRANCH    : 1;
    UINT32    Reserved1     : 23;
    UINT32    Reserved2     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_LBR_SELECT_REGISTER;
 
#define MSR_XEON_PHI_LASTBRANCH_TOS  0x000001C9
 
#define MSR_XEON_PHI_LER_FROM_LIP  0x000001DD
 
#define MSR_XEON_PHI_LER_TO_LIP  0x000001DE
 
#define MSR_XEON_PHI_PEBS_ENABLE  0x000003F1
 
#define MSR_XEON_PHI_PKG_C3_RESIDENCY  0x000003F8
 
#define MSR_XEON_PHI_PKG_C6_RESIDENCY  0x000003F9
 
#define MSR_XEON_PHI_PKG_C7_RESIDENCY  0x000003FA
 
#define MSR_XEON_PHI_MC0_RESIDENCY  0x000003FC
 
#define MSR_XEON_PHI_MC6_RESIDENCY  0x000003FD
 
#define MSR_XEON_PHI_CORE_C6_RESIDENCY  0x000003FF
 
#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM  0x0000048C
 
#define MSR_XEON_PHI_IA32_VMX_FMFUNC  0x00000491
 
#define MSR_XEON_PHI_RAPL_POWER_UNIT  0x00000606
 
typedef union {
  struct {
    UINT32    PowerUnits        : 4;
    UINT32    Reserved1         : 4;
    UINT32    EnergyStatusUnits : 5;
    UINT32    Reserved2         : 3;
    UINT32    TimeUnits         : 4;
    UINT32    Reserved3         : 12;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;
 
#define MSR_XEON_PHI_PKG_C2_RESIDENCY  0x0000060D
 
#define MSR_XEON_PHI_PKG_POWER_LIMIT  0x00000610
 
#define MSR_XEON_PHI_PKG_ENERGY_STATUS  0x00000611
 
#define MSR_XEON_PHI_PKG_PERF_STATUS  0x00000613
 
#define MSR_XEON_PHI_PKG_POWER_INFO  0x00000614
 
#define MSR_XEON_PHI_DRAM_POWER_LIMIT  0x00000618
 
#define MSR_XEON_PHI_DRAM_ENERGY_STATUS  0x00000619
 
#define MSR_XEON_PHI_DRAM_PERF_STATUS  0x0000061B
 
#define MSR_XEON_PHI_DRAM_POWER_INFO  0x0000061C
 
#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT  0x00000620
 
typedef union {
  struct {
    UINT32    MAX_RATIO : 7;
    UINT32    Reserved1 : 1;
    UINT32    MIN_RATIO : 7;
    UINT32    Reserved2 : 17;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;
 
#define MSR_XEON_PHI_PP0_POWER_LIMIT  0x00000638
 
#define MSR_XEON_PHI_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL  0x00000648
 
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1  0x00000649
 
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2  0x0000064A
 
#define MSR_XEON_PHI_CONFIG_TDP_CONTROL  0x0000064B
 
#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO  0x0000064C
 
#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS  0x00000690
 
typedef union {
  struct {
    UINT32    PROCHOT_Status              : 1;
    UINT32    ThermalStatus               : 1;
    UINT32    Reserved1                   : 4;
    UINT32    VRThermAlertStatus          : 1;
    UINT32    Reserved2                   : 1;
    UINT32    ElectricalDesignPointStatus : 1;
    UINT32    Reserved3                   : 23;
    UINT32    Reserved4                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;
 
#endif