TianoCore EDK2 master
SkylakeMsr.h
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1
18#ifndef __SKYLAKE_MSR_H__
19#define __SKYLAKE_MSR_H__
20
22
32#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x4E || \
36 DisplayModel == 0x5E || \
37 DisplayModel == 0x55 || \
38 DisplayModel == 0x8E || \
39 DisplayModel == 0x9E || \
40 DisplayModel == 0x66 \
41 ) \
42 )
43
62#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD
63
67typedef union {
71 struct {
76 UINT32 Maximum1C : 8;
81 UINT32 Maximum2C : 8;
86 UINT32 Maximum3C : 8;
91 UINT32 Maximum4C : 8;
92 UINT32 Reserved : 32;
93 } Bits;
97 UINT32 Uint32;
101 UINT64 Uint64;
103
121#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
122
140#define MSR_SKYLAKE_POWER_CTL 0x000001FC
141
145typedef union {
149 struct {
150 UINT32 Reserved1 : 1;
156 UINT32 C1EEnable : 1;
157 UINT32 Reserved2 : 17;
166 UINT32 Fix_Me_1 : 1;
177 UINT32 Reserved3 : 11;
178 UINT32 Reserved4 : 32;
179 } Bits;
183 UINT32 Uint32;
187 UINT64 Uint64;
189
209#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300
210
211//
212// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.
213//
214#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0
215
235#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301
236
237//
238// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.
239//
240#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1
241
261#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E
262
266typedef union {
270 struct {
274 UINT32 Ovf_PMC0 : 1;
278 UINT32 Ovf_PMC1 : 1;
282 UINT32 Ovf_PMC2 : 1;
286 UINT32 Ovf_PMC3 : 1;
290 UINT32 Ovf_PMC4 : 1;
294 UINT32 Ovf_PMC5 : 1;
298 UINT32 Ovf_PMC6 : 1;
302 UINT32 Ovf_PMC7 : 1;
303 UINT32 Reserved1 : 24;
307 UINT32 Ovf_FixedCtr0 : 1;
311 UINT32 Ovf_FixedCtr1 : 1;
315 UINT32 Ovf_FixedCtr2 : 1;
316 UINT32 Reserved2 : 20;
320 UINT32 Trace_ToPA_PMI : 1;
321 UINT32 Reserved3 : 2;
325 UINT32 LBR_Frz : 1;
329 UINT32 CTR_Frz : 1;
333 UINT32 ASCI : 1;
337 UINT32 Ovf_Uncore : 1;
341 UINT32 Ovf_BufDSSAVE : 1;
345 UINT32 CondChgd : 1;
346 } Bits;
350 UINT64 Uint64;
352
372#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
373
378typedef union {
382 struct {
386 UINT32 Ovf_PMC0 : 1;
390 UINT32 Ovf_PMC1 : 1;
394 UINT32 Ovf_PMC2 : 1;
398 UINT32 Ovf_PMC3 : 1;
402 UINT32 Ovf_PMC4 : 1;
406 UINT32 Ovf_PMC5 : 1;
410 UINT32 Ovf_PMC6 : 1;
414 UINT32 Ovf_PMC7 : 1;
415 UINT32 Reserved1 : 24;
419 UINT32 Ovf_FixedCtr0 : 1;
423 UINT32 Ovf_FixedCtr1 : 1;
427 UINT32 Ovf_FixedCtr2 : 1;
428 UINT32 Reserved2 : 20;
432 UINT32 Trace_ToPA_PMI : 1;
433 UINT32 Reserved3 : 2;
437 UINT32 LBR_Frz : 1;
441 UINT32 CTR_Frz : 1;
445 UINT32 ASCI : 1;
449 UINT32 Ovf_Uncore : 1;
453 UINT32 Ovf_BufDSSAVE : 1;
457 UINT32 CondChgd : 1;
458 } Bits;
462 UINT64 Uint64;
464
484#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
485
490typedef union {
494 struct {
498 UINT32 Ovf_PMC0 : 1;
502 UINT32 Ovf_PMC1 : 1;
506 UINT32 Ovf_PMC2 : 1;
510 UINT32 Ovf_PMC3 : 1;
514 UINT32 Ovf_PMC4 : 1;
518 UINT32 Ovf_PMC5 : 1;
522 UINT32 Ovf_PMC6 : 1;
526 UINT32 Ovf_PMC7 : 1;
527 UINT32 Reserved1 : 24;
531 UINT32 Ovf_FixedCtr0 : 1;
535 UINT32 Ovf_FixedCtr1 : 1;
539 UINT32 Ovf_FixedCtr2 : 1;
540 UINT32 Reserved2 : 20;
544 UINT32 Trace_ToPA_PMI : 1;
545 UINT32 Reserved3 : 2;
549 UINT32 LBR_Frz : 1;
553 UINT32 CTR_Frz : 1;
557 UINT32 ASCI : 1;
561 UINT32 Ovf_Uncore : 1;
565 UINT32 Ovf_BufDSSAVE : 1;
566 UINT32 Reserved4 : 1;
567 } Bits;
571 UINT64 Uint64;
573
592#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7
593
597typedef union {
601 struct {
605 UINT32 EventCodeSelect : 3;
606 UINT32 Reserved1 : 1;
611 UINT32 Reserved2 : 3;
615 UINT32 IDQ_Bubble_Length : 12;
620 UINT32 Reserved3 : 9;
621 UINT32 Reserved4 : 32;
622 } Bits;
626 UINT32 Uint32;
630 UINT64 Uint64;
632
649#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
650
670#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D
671
675typedef union {
679 struct {
688 UINT32 TotalEnergy : 32;
689 UINT32 Reserved : 32;
690 } Bits;
694 UINT32 Uint32;
698 UINT64 Uint64;
700
717#define MSR_SKYLAKE_PPERF 0x0000064E
718
738#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F
739
743typedef union {
747 struct {
752 UINT32 PROCHOT_Status : 1;
757 UINT32 ThermalStatus : 1;
758 UINT32 Reserved1 : 2;
787 UINT32 OtherStatus : 1;
788 UINT32 Reserved2 : 1;
794 UINT32 PL1Status : 1;
800 UINT32 PL2Status : 1;
813 UINT32 Reserved3 : 2;
819 UINT32 PROCHOT_Log : 1;
825 UINT32 ThermalLog : 1;
826 UINT32 Reserved4 : 2;
845 UINT32 VRThermAlertLog : 1;
857 UINT32 OtherLog : 1;
858 UINT32 Reserved5 : 1;
865 UINT32 PL1Log : 1;
872 UINT32 PL2Log : 1;
886 UINT32 Reserved6 : 2;
887 UINT32 Reserved7 : 32;
888 } Bits;
892 UINT32 Uint32;
896 UINT64 Uint64;
898
917#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652
918
922typedef union {
926 struct {
931 UINT32 PKG_Cx_Monitor : 3;
932 UINT32 Reserved1 : 29;
933 UINT32 Reserved2 : 32;
934 } Bits;
938 UINT32 Uint32;
942 UINT64 Uint64;
944
960#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653
961
978#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655
979
995#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656
996
1015#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658
1016
1034#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659
1035
1053#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A
1054
1073#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B
1074
1099#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C
1100
1104typedef union {
1108 struct {
1141 UINT32 Time : 7;
1142 UINT32 Reserved1 : 8;
1162 UINT32 Reserved2 : 14;
1167 UINT32 Lock : 1;
1168 } Bits;
1172 UINT64 Uint64;
1174
1210#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690
1211#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691
1212#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692
1213#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693
1214#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694
1215#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695
1216#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696
1217#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697
1218#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698
1219#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699
1220#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A
1221#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B
1222#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C
1223#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D
1224#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E
1225#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F
1227
1247#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1248
1253typedef union {
1257 struct {
1262 UINT32 PROCHOT_Status : 1;
1267 UINT32 ThermalStatus : 1;
1268 UINT32 Reserved1 : 3;
1288 UINT32 OtherStatus : 1;
1289 UINT32 Reserved2 : 1;
1295 UINT32 PL1Status : 1;
1301 UINT32 PL2Status : 1;
1307 UINT32 Reserved3 : 3;
1313 UINT32 PROCHOT_Log : 1;
1319 UINT32 ThermalLog : 1;
1320 UINT32 Reserved4 : 3;
1345 UINT32 OtherLog : 1;
1346 UINT32 Reserved5 : 1;
1353 UINT32 PL1Log : 1;
1360 UINT32 PL2Log : 1;
1368 UINT32 Reserved6 : 3;
1369 UINT32 Reserved7 : 32;
1370 } Bits;
1374 UINT32 Uint32;
1378 UINT64 Uint64;
1380
1400#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1
1401
1405typedef union {
1409 struct {
1414 UINT32 PROCHOT_Status : 1;
1419 UINT32 ThermalStatus : 1;
1420 UINT32 Reserved1 : 3;
1440 UINT32 OtherStatus : 1;
1441 UINT32 Reserved2 : 1;
1447 UINT32 PL1Status : 1;
1453 UINT32 PL2Status : 1;
1454 UINT32 Reserved3 : 4;
1460 UINT32 PROCHOT_Log : 1;
1466 UINT32 ThermalLog : 1;
1467 UINT32 Reserved4 : 3;
1492 UINT32 OtherLog : 1;
1493 UINT32 Reserved5 : 1;
1500 UINT32 PL1Log : 1;
1507 UINT32 PL2Log : 1;
1508 UINT32 Reserved6 : 4;
1509 UINT32 Reserved7 : 32;
1510 } Bits;
1514 UINT32 Uint32;
1518 UINT64 Uint64;
1520
1556#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0
1557#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1
1558#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2
1559#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3
1560#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4
1561#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5
1562#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6
1563#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7
1564#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8
1565#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9
1566#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA
1567#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB
1568#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC
1569#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD
1570#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE
1571#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF
1573
1626#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0
1627#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1
1628#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2
1629#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3
1630#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4
1631#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5
1632#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6
1633#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7
1634#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8
1635#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9
1636#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA
1637#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB
1638#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC
1639#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD
1640#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE
1641#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF
1642#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0
1643#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1
1644#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2
1645#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3
1646#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4
1647#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5
1648#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6
1649#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7
1650#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8
1651#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9
1652#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA
1653#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB
1654#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC
1655#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD
1656#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE
1657#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF
1659
1678#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394
1679
1683typedef union {
1687 struct {
1688 UINT32 Reserved1 : 20;
1692 UINT32 EnableOverflow : 1;
1693 UINT32 Reserved2 : 1;
1697 UINT32 EnableCounting : 1;
1698 UINT32 Reserved3 : 9;
1699 UINT32 Reserved4 : 32;
1700 } Bits;
1704 UINT32 Uint32;
1708 UINT64 Uint64;
1710
1729#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395
1730
1734typedef union {
1738 struct {
1742 UINT32 CurrentCount : 32;
1746 UINT32 CurrentCountHi : 12;
1747 UINT32 Reserved : 20;
1748 } Bits;
1752 UINT64 Uint64;
1754
1772#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396
1773
1777typedef union {
1781 struct {
1786 UINT32 CBox : 4;
1787 UINT32 Reserved1 : 28;
1788 UINT32 Reserved2 : 32;
1789 } Bits;
1793 UINT32 Uint32;
1797 UINT64 Uint64;
1799
1816#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0
1817
1834#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1
1835
1852#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2
1853
1870#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3
1871
1888#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700
1889
1906#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701
1907
1924#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706
1925
1942#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707
1943
1960#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710
1961
1978#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711
1979
1996#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716
1997
2014#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717
2015
2032#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2033
2050#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2051
2068#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726
2069
2086#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727
2087
2104#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2105
2122#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2123
2140#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736
2141
2158#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737
2159
2178#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01
2179
2183typedef union {
2187 struct {
2191 UINT32 PMI_Sel_Slice0 : 1;
2195 UINT32 PMI_Sel_Slice1 : 1;
2199 UINT32 PMI_Sel_Slice2 : 1;
2203 UINT32 PMI_Sel_Slice3 : 1;
2207 UINT32 PMI_Sel_Slice4 : 1;
2208 UINT32 Reserved1 : 14;
2209 UINT32 Reserved2 : 10;
2213 UINT32 EN : 1;
2217 UINT32 WakePMI : 1;
2221 UINT32 FREEZE : 1;
2222 UINT32 Reserved3 : 32;
2223 } Bits;
2227 UINT32 Uint32;
2231 UINT64 Uint64;
2233
2252#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02
2253
2257typedef union {
2261 struct {
2265 UINT32 Fixed : 1;
2269 UINT32 ARB : 1;
2270 UINT32 Reserved1 : 1;
2274 UINT32 CBox : 1;
2275 UINT32 Reserved2 : 28;
2276 UINT32 Reserved3 : 32;
2277 } Bits;
2281 UINT32 Uint32;
2285 UINT64 Uint64;
2287
2305#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080
2306
2311typedef union {
2315 struct {
2321 UINT32 Fix_Me_1 : 1;
2322 UINT32 Reserved : 17;
2330 UINT32 Fix_Me_2 : 32;
2331 } Bits;
2335 UINT64 Uint64;
2337
2356#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4
2357
2361typedef union {
2365 struct {
2370 UINT32 Reserved1 : 9;
2378 UINT32 Fix_Me_1 : 14;
2379 UINT32 Reserved2 : 18;
2380 } Bits;
2384 UINT64 Uint64;
2386
2405#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5
2406
2410typedef union {
2414 struct {
2415 UINT32 Reserved1 : 10;
2419 UINT32 Fix_Me_1 : 1;
2423 UINT32 VLD : 1;
2427 UINT32 Fix_Me_2 : 20;
2431 UINT32 Fix_Me_3 : 14;
2432 UINT32 Reserved2 : 18;
2433 } Bits;
2437 UINT64 Uint64;
2439
2457#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB
2458
2462typedef union {
2466 struct {
2470 UINT32 Fix_Me_1 : 1;
2471 UINT32 Reserved1 : 4;
2475 UINT32 Fix_Me_2 : 1;
2479 UINT32 Fix_Me_3 : 1;
2483 UINT32 Fix_Me_4 : 1;
2484 UINT32 Reserved2 : 24;
2485 UINT32 Reserved3 : 32;
2486 } Bits;
2490 UINT32 Uint32;
2494 UINT64 Uint64;
2496
2517#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4
2518
2522typedef union {
2526 struct {
2527 UINT32 Reserved1 : 12;
2532 UINT32 Fix_Me_1 : 20;
2537 UINT32 Fix_Me_2 : 7;
2538 UINT32 Reserved2 : 25;
2539 } Bits;
2543 UINT64 Uint64;
2545
2564#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5
2565
2569typedef union {
2573 struct {
2574 UINT32 Reserved1 : 10;
2579 UINT32 Fix_Me_1 : 1;
2584 UINT32 Fix_Me_2 : 1;
2585 UINT32 Reserved2 : 20;
2586 UINT32 Reserved3 : 32;
2587 } Bits;
2591 UINT32 Uint32;
2595 UINT64 Uint64;
2597
2616#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620
2617
2621typedef union {
2625 struct {
2630 UINT32 Fix_Me_1 : 7;
2631 UINT32 Reserved1 : 1;
2636 UINT32 Fix_Me_2 : 7;
2637 UINT32 Reserved2 : 17;
2638 UINT32 Reserved3 : 32;
2639 } Bits;
2643 UINT32 Uint32;
2647 UINT64 Uint64;
2649
2667#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350
2668
2672typedef union {
2676 struct {
2680 UINT32 EnMonitoring : 1;
2687 UINT32 EnExcept : 1;
2693 UINT32 EnLBRFrz : 1;
2699 UINT32 DisableInGuest : 1;
2700 UINT32 Reserved1 : 4;
2707 UINT32 WindowSize : 10;
2708 UINT32 Reserved2 : 6;
2714 UINT32 WindowCntSel : 2;
2721 UINT32 CntAndMode : 1;
2722 UINT32 Reserved3 : 5;
2723 UINT32 Reserved4 : 32;
2724 } Bits;
2728 UINT32 Uint32;
2732 UINT64 Uint64;
2734
2752#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351
2753
2757typedef union {
2761 struct {
2772 UINT32 LBRsValid : 1;
2773 UINT32 Reserved1 : 6;
2779 UINT32 CntrHit0 : 1;
2785 UINT32 CntrHit1 : 1;
2786 UINT32 Reserved2 : 6;
2792 UINT32 CountWindow : 10;
2793 UINT32 Reserved3 : 6;
2803 UINT32 Count0 : 8;
2813 UINT32 Count1 : 8;
2814 UINT32 Reserved4 : 16;
2815 } Bits;
2819 UINT32 Uint32;
2823 UINT64 Uint64;
2825
2842#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8
2843
2865#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660
2866
2881#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662
2882
2900#define MSR_SKYLAKE_PPIN_CTL 0x0000004E
2901
2905typedef union {
2909 struct {
2913 UINT32 LockOut : 1;
2917 UINT32 Enable_PPIN : 1;
2918 UINT32 Reserved1 : 30;
2919 UINT32 Reserved2 : 32;
2920 } Bits;
2924 UINT32 Uint32;
2928 UINT64 Uint64;
2930
2946#define MSR_SKYLAKE_PPIN 0x0000004F
2947
2966#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE
2967
2971typedef union {
2975 struct {
2976 UINT32 Reserved1 : 8;
2981 UINT32 Reserved2 : 7;
2985 UINT32 PPIN_CAP : 1;
2986 UINT32 Reserved3 : 4;
3001 UINT32 Reserved4 : 1;
3002 UINT32 Reserved5 : 8;
3007 UINT32 Reserved6 : 16;
3008 } Bits;
3012 UINT64 Uint64;
3014
3034#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2
3035
3039typedef union {
3043 struct {
3053 UINT32 C_StateLimit : 3;
3054 UINT32 Reserved1 : 7;
3059 UINT32 Reserved2 : 4;
3063 UINT32 CFGLock : 1;
3069 UINT32 Reserved3 : 8;
3094 UINT32 Reserved4 : 1;
3095 UINT32 Reserved5 : 32;
3096 } Bits;
3100 UINT32 Uint32;
3104 UINT64 Uint64;
3106
3123#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179
3124
3128typedef union {
3132 struct {
3136 UINT32 Count : 8;
3140 UINT32 MCG_CTL_P : 1;
3144 UINT32 MCG_EXT_P : 1;
3148 UINT32 MCP_CMCI_P : 1;
3152 UINT32 MCG_TES_P : 1;
3153 UINT32 Reserved1 : 4;
3157 UINT32 MCG_EXT_CNT : 8;
3161 UINT32 MCG_SER_P : 1;
3165 UINT32 MCG_EM_P : 1;
3169 UINT32 MCG_ELOG_P : 1;
3170 UINT32 Reserved2 : 5;
3171 UINT32 Reserved3 : 32;
3172 } Bits;
3176 UINT32 Uint32;
3180 UINT64 Uint64;
3182
3201#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D
3202
3206typedef union {
3210 struct {
3211 UINT32 Reserved1 : 32;
3212 UINT32 Reserved2 : 26;
3225 UINT32 Reserved3 : 4;
3226 } Bits;
3230 UINT64 Uint64;
3232
3250#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2
3251
3255typedef union {
3259 struct {
3260 UINT32 Reserved1 : 16;
3269 UINT32 Reserved2 : 4;
3270 UINT32 Reserved3 : 32;
3271 } Bits;
3275 UINT32 Uint32;
3279 UINT64 Uint64;
3281
3303#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE
3304
3308typedef union {
3312 struct {
3317 UINT32 NUMCORE_0 : 8;
3322 UINT32 NUMCORE_1 : 8;
3327 UINT32 NUMCORE_2 : 8;
3332 UINT32 NUMCORE_3 : 8;
3337 UINT32 NUMCORE_4 : 8;
3342 UINT32 NUMCORE_5 : 8;
3347 UINT32 NUMCORE_6 : 8;
3352 UINT32 NUMCORE_7 : 8;
3353 } Bits;
3357 UINT64 Uint64;
3359
3376#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606
3377
3381typedef union {
3385 struct {
3389 UINT32 PowerUnits : 4;
3390 UINT32 Reserved1 : 4;
3398 UINT32 Reserved2 : 3;
3403 UINT32 TimeUnits : 4;
3404 UINT32 Reserved3 : 12;
3405 UINT32 Reserved4 : 32;
3406 } Bits;
3410 UINT32 Uint32;
3414 UINT64 Uint64;
3416
3433#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618
3434
3451#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619
3452
3456typedef union {
3460 struct {
3465 UINT32 Energy : 32;
3466 UINT32 Reserved : 32;
3467 } Bits;
3471 UINT32 Uint32;
3475 UINT64 Uint64;
3477
3493#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B
3494
3510#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C
3511
3532#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620
3533
3537typedef union {
3541 struct {
3546 UINT32 MAX_RATIO : 7;
3547 UINT32 Reserved1 : 1;
3552 UINT32 MIN_RATIO : 7;
3553 UINT32 Reserved2 : 17;
3554 UINT32 Reserved3 : 32;
3555 } Bits;
3559 UINT32 Uint32;
3563 UINT64 Uint64;
3565
3580#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
3581
3600#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D
3601
3605typedef union {
3609 struct {
3615 UINT32 EventID : 8;
3616 UINT32 Reserved1 : 24;
3620 UINT32 RMID : 10;
3621 UINT32 Reserved2 : 22;
3622 } Bits;
3626 UINT64 Uint64;
3628
3646#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F
3647
3651typedef union {
3655 struct {
3659 UINT32 RMID : 10;
3660 UINT32 Reserved1 : 22;
3664 UINT32 COS : 20;
3665 UINT32 Reserved2 : 12;
3666 } Bits;
3670 UINT64 Uint64;
3672
3691#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90
3692#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91
3693#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92
3694#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93
3695#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94
3696#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95
3697#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96
3698#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97
3699#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98
3700#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99
3701#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A
3702#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B
3703#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C
3704#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D
3705#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E
3706#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F
3707
3711typedef union {
3715 struct {
3719 UINT32 CBM : 20;
3720 UINT32 Reserved2 : 12;
3721 UINT32 Reserved3 : 32;
3722 } Bits;
3726 UINT32 Uint32;
3730 UINT64 Uint64;
3732
3733#endif