SkylakeMsr.h

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#ifndef __SKYLAKE_MSR_H__
#define __SKYLAKE_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x4E || \
    DisplayModel == 0x5E || \
    DisplayModel == 0x55 || \
    DisplayModel == 0x8E || \
    DisplayModel == 0x9E || \
    DisplayModel == 0x66    \
    )                       \
   )
 
#define MSR_SKYLAKE_TURBO_RATIO_LIMIT  0x000001AD
 
typedef union {
  struct {
    UINT32    Maximum1C : 8;
    UINT32    Maximum2C : 8;
    UINT32    Maximum3C : 8;
    UINT32    Maximum4C : 8;
    UINT32    Reserved  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;
 
#define MSR_SKYLAKE_LASTBRANCH_TOS  0x000001C9
 
#define MSR_SKYLAKE_POWER_CTL  0x000001FC
 
typedef union {
  struct {
    UINT32    Reserved1 : 1;
    UINT32    C1EEnable : 1;
    UINT32    Reserved2 : 17;
    UINT32    Fix_Me_1 : 1;
    UINT32    DisableEnergyEfficiencyOptimization : 1;
    UINT32    Reserved3                           : 11;
    UINT32    Reserved4                           : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_POWER_CTL_REGISTER;
 
#define MSR_SKYLAKE_SGXOWNEREPOCH0  0x00000300
 
//
// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.
//
#define MSR_SKYLAKE_SGXOWNER0  MSR_SKYLAKE_SGXOWNEREPOCH0
 
#define MSR_SKYLAKE_SGXOWNEREPOCH1  0x00000301
 
//
// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.
//
#define MSR_SKYLAKE_SGXOWNER1  MSR_SKYLAKE_SGXOWNEREPOCH1
 
#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS  0x0000038E
 
typedef union {
  struct {
    UINT32    Ovf_PMC0       : 1;
    UINT32    Ovf_PMC1       : 1;
    UINT32    Ovf_PMC2       : 1;
    UINT32    Ovf_PMC3       : 1;
    UINT32    Ovf_PMC4       : 1;
    UINT32    Ovf_PMC5       : 1;
    UINT32    Ovf_PMC6       : 1;
    UINT32    Ovf_PMC7       : 1;
    UINT32    Reserved1      : 24;
    UINT32    Ovf_FixedCtr0  : 1;
    UINT32    Ovf_FixedCtr1  : 1;
    UINT32    Ovf_FixedCtr2  : 1;
    UINT32    Reserved2      : 20;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved3      : 2;
    UINT32    LBR_Frz        : 1;
    UINT32    CTR_Frz        : 1;
    UINT32    ASCI           : 1;
    UINT32    Ovf_Uncore     : 1;
    UINT32    Ovf_BufDSSAVE  : 1;
    UINT32    CondChgd       : 1;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;
 
#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET  0x00000390
 
typedef union {
  struct {
    UINT32    Ovf_PMC0       : 1;
    UINT32    Ovf_PMC1       : 1;
    UINT32    Ovf_PMC2       : 1;
    UINT32    Ovf_PMC3       : 1;
    UINT32    Ovf_PMC4       : 1;
    UINT32    Ovf_PMC5       : 1;
    UINT32    Ovf_PMC6       : 1;
    UINT32    Ovf_PMC7       : 1;
    UINT32    Reserved1      : 24;
    UINT32    Ovf_FixedCtr0  : 1;
    UINT32    Ovf_FixedCtr1  : 1;
    UINT32    Ovf_FixedCtr2  : 1;
    UINT32    Reserved2      : 20;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved3      : 2;
    UINT32    LBR_Frz        : 1;
    UINT32    CTR_Frz        : 1;
    UINT32    ASCI           : 1;
    UINT32    Ovf_Uncore     : 1;
    UINT32    Ovf_BufDSSAVE  : 1;
    UINT32    CondChgd       : 1;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
 
#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET  0x00000391
 
typedef union {
  struct {
    UINT32    Ovf_PMC0       : 1;
    UINT32    Ovf_PMC1       : 1;
    UINT32    Ovf_PMC2       : 1;
    UINT32    Ovf_PMC3       : 1;
    UINT32    Ovf_PMC4       : 1;
    UINT32    Ovf_PMC5       : 1;
    UINT32    Ovf_PMC6       : 1;
    UINT32    Ovf_PMC7       : 1;
    UINT32    Reserved1      : 24;
    UINT32    Ovf_FixedCtr0  : 1;
    UINT32    Ovf_FixedCtr1  : 1;
    UINT32    Ovf_FixedCtr2  : 1;
    UINT32    Reserved2      : 20;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved3      : 2;
    UINT32    LBR_Frz        : 1;
    UINT32    CTR_Frz        : 1;
    UINT32    ASCI           : 1;
    UINT32    Ovf_Uncore     : 1;
    UINT32    Ovf_BufDSSAVE  : 1;
    UINT32    Reserved4      : 1;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
 
#define MSR_SKYLAKE_PEBS_FRONTEND  0x000003F7
 
typedef union {
  struct {
    UINT32    EventCodeSelect     : 3;
    UINT32    Reserved1           : 1;
    UINT32    EventCodeSelectHigh : 1;
    UINT32    Reserved2           : 3;
    UINT32    IDQ_Bubble_Length   : 12;
    UINT32    IDQ_Bubble_Width    : 3;
    UINT32    Reserved3           : 9;
    UINT32    Reserved4           : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;
 
#define MSR_SKYLAKE_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER  0x0000064D
 
typedef union {
  struct {
    UINT32    TotalEnergy : 32;
    UINT32    Reserved    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;
 
#define MSR_SKYLAKE_PPERF  0x0000064E
 
#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS  0x0000064F
 
typedef union {
  struct {
    UINT32    PROCHOT_Status                   : 1;
    UINT32    ThermalStatus                    : 1;
    UINT32    Reserved1                        : 2;
    UINT32    ResidencyStateRegulationStatus   : 1;
    UINT32    RunningAverageThermalLimitStatus : 1;
    UINT32    VRThermAlertStatus               : 1;
    UINT32    VRThermDesignCurrentStatus       : 1;
    UINT32    OtherStatus                      : 1;
    UINT32    Reserved2                        : 1;
    UINT32    PL1Status                        : 1;
    UINT32    PL2Status                        : 1;
    UINT32    MaxTurboLimitStatus              : 1;
    UINT32    TurboTransitionAttenuationStatus : 1;
    UINT32    Reserved3                        : 2;
    UINT32    PROCHOT_Log                      : 1;
    UINT32    ThermalLog                       : 1;
    UINT32    Reserved4                        : 2;
    UINT32    ResidencyStateRegulationLog      : 1;
    UINT32    RunningAverageThermalLimitLog    : 1;
    UINT32    VRThermAlertLog                  : 1;
    UINT32    VRThermalDesignCurrentLog        : 1;
    UINT32    OtherLog                         : 1;
    UINT32    Reserved5                        : 1;
    UINT32    PL1Log                           : 1;
    UINT32    PL2Log                           : 1;
    UINT32    MaxTurboLimitLog                 : 1;
    UINT32    TurboTransitionAttenuationLog    : 1;
    UINT32    Reserved6                        : 2;
    UINT32    Reserved7                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_SKYLAKE_PKG_HDC_CONFIG  0x00000652
 
typedef union {
  struct {
    UINT32    PKG_Cx_Monitor : 3;
    UINT32    Reserved1      : 29;
    UINT32    Reserved2      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;
 
#define MSR_SKYLAKE_CORE_HDC_RESIDENCY  0x00000653
 
#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY  0x00000655
 
#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY  0x00000656
 
#define MSR_SKYLAKE_WEIGHTED_CORE_C0  0x00000658
 
#define MSR_SKYLAKE_ANY_CORE_C0  0x00000659
 
#define MSR_SKYLAKE_ANY_GFXE_C0  0x0000065A
 
#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0  0x0000065B
 
#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT  0x0000065C
 
typedef union {
  struct {
    UINT32    PlatformPowerLimit1         : 15;
    UINT32    EnablePlatformPowerLimit1   : 1;
    UINT32    PlatformClampingLimitation1 : 1;
    UINT32    Time                        : 7;
    UINT32    Reserved1                   : 8;
    UINT32    PlatformPowerLimit2         : 15;
    UINT32    EnablePlatformPowerLimit2   : 1;
    UINT32    PlatformClampingLimitation2 : 1;
    UINT32    Reserved2                   : 14;
    UINT32    Lock                        : 1;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;
 
#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP  0x00000690
#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP  0x00000691
#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP  0x00000692
#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP  0x00000693
#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP  0x00000694
#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP  0x00000695
#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP  0x00000696
#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP  0x00000697
#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP  0x00000698
#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP  0x00000699
#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP  0x0000069A
#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP  0x0000069B
#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP  0x0000069C
#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP  0x0000069D
#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP  0x0000069E
#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP  0x0000069F
 
#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS  0x000006B0
 
typedef union {
  struct {
    UINT32    PROCHOT_Status                   : 1;
    UINT32    ThermalStatus                    : 1;
    UINT32    Reserved1                        : 3;
    UINT32    RunningAverageThermalLimitStatus : 1;
    UINT32    VRThermAlertStatus               : 1;
    UINT32    VRThermalDesignCurrentStatus     : 1;
    UINT32    OtherStatus                      : 1;
    UINT32    Reserved2                        : 1;
    UINT32    PL1Status                        : 1;
    UINT32    PL2Status                        : 1;
    UINT32    InefficientOperationStatus       : 1;
    UINT32    Reserved3                        : 3;
    UINT32    PROCHOT_Log                      : 1;
    UINT32    ThermalLog                       : 1;
    UINT32    Reserved4                        : 3;
    UINT32    RunningAverageThermalLimitLog    : 1;
    UINT32    VRThermAlertLog                  : 1;
    UINT32    VRThermalDesignCurrentLog        : 1;
    UINT32    OtherLog                         : 1;
    UINT32    Reserved5                        : 1;
    UINT32    PL1Log                           : 1;
    UINT32    PL2Log                           : 1;
    UINT32    InefficientOperationLog          : 1;
    UINT32    Reserved6                        : 3;
    UINT32    Reserved7                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS  0x000006B1
 
typedef union {
  struct {
    UINT32    PROCHOT_Status                   : 1;
    UINT32    ThermalStatus                    : 1;
    UINT32    Reserved1                        : 3;
    UINT32    RunningAverageThermalLimitStatus : 1;
    UINT32    VRThermAlertStatus               : 1;
    UINT32    VRThermalDesignCurrentStatus     : 1;
    UINT32    OtherStatus                      : 1;
    UINT32    Reserved2                        : 1;
    UINT32    PL1Status                        : 1;
    UINT32    PL2Status                        : 1;
    UINT32    Reserved3                        : 4;
    UINT32    PROCHOT_Log                      : 1;
    UINT32    ThermalLog                       : 1;
    UINT32    Reserved4                        : 3;
    UINT32    RunningAverageThermalLimitLog    : 1;
    UINT32    VRThermAlertLog                  : 1;
    UINT32    VRThermalDesignCurrentLog        : 1;
    UINT32    OtherLog                         : 1;
    UINT32    Reserved5                        : 1;
    UINT32    PL1Log                           : 1;
    UINT32    PL2Log                           : 1;
    UINT32    Reserved6                        : 4;
    UINT32    Reserved7                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP  0x000006D0
#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP  0x000006D1
#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP  0x000006D2
#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP  0x000006D3
#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP  0x000006D4
#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP  0x000006D5
#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP  0x000006D6
#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP  0x000006D7
#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP  0x000006D8
#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP  0x000006D9
#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP  0x000006DA
#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP  0x000006DB
#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP  0x000006DC
#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP  0x000006DD
#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP  0x000006DE
#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP  0x000006DF
 
#define MSR_SKYLAKE_LBR_INFO_0   0x00000DC0
#define MSR_SKYLAKE_LBR_INFO_1   0x00000DC1
#define MSR_SKYLAKE_LBR_INFO_2   0x00000DC2
#define MSR_SKYLAKE_LBR_INFO_3   0x00000DC3
#define MSR_SKYLAKE_LBR_INFO_4   0x00000DC4
#define MSR_SKYLAKE_LBR_INFO_5   0x00000DC5
#define MSR_SKYLAKE_LBR_INFO_6   0x00000DC6
#define MSR_SKYLAKE_LBR_INFO_7   0x00000DC7
#define MSR_SKYLAKE_LBR_INFO_8   0x00000DC8
#define MSR_SKYLAKE_LBR_INFO_9   0x00000DC9
#define MSR_SKYLAKE_LBR_INFO_10  0x00000DCA
#define MSR_SKYLAKE_LBR_INFO_11  0x00000DCB
#define MSR_SKYLAKE_LBR_INFO_12  0x00000DCC
#define MSR_SKYLAKE_LBR_INFO_13  0x00000DCD
#define MSR_SKYLAKE_LBR_INFO_14  0x00000DCE
#define MSR_SKYLAKE_LBR_INFO_15  0x00000DCF
#define MSR_SKYLAKE_LBR_INFO_16  0x00000DD0
#define MSR_SKYLAKE_LBR_INFO_17  0x00000DD1
#define MSR_SKYLAKE_LBR_INFO_18  0x00000DD2
#define MSR_SKYLAKE_LBR_INFO_19  0x00000DD3
#define MSR_SKYLAKE_LBR_INFO_20  0x00000DD4
#define MSR_SKYLAKE_LBR_INFO_21  0x00000DD5
#define MSR_SKYLAKE_LBR_INFO_22  0x00000DD6
#define MSR_SKYLAKE_LBR_INFO_23  0x00000DD7
#define MSR_SKYLAKE_LBR_INFO_24  0x00000DD8
#define MSR_SKYLAKE_LBR_INFO_25  0x00000DD9
#define MSR_SKYLAKE_LBR_INFO_26  0x00000DDA
#define MSR_SKYLAKE_LBR_INFO_27  0x00000DDB
#define MSR_SKYLAKE_LBR_INFO_28  0x00000DDC
#define MSR_SKYLAKE_LBR_INFO_29  0x00000DDD
#define MSR_SKYLAKE_LBR_INFO_30  0x00000DDE
#define MSR_SKYLAKE_LBR_INFO_31  0x00000DDF
 
#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL  0x00000394
 
typedef union {
  struct {
    UINT32    Reserved1      : 20;
    UINT32    EnableOverflow : 1;
    UINT32    Reserved2      : 1;
    UINT32    EnableCounting : 1;
    UINT32    Reserved3      : 9;
    UINT32    Reserved4      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;
 
#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR  0x00000395
 
typedef union {
  struct {
    UINT32    CurrentCount   : 32;
    UINT32    CurrentCountHi : 12;
    UINT32    Reserved       : 20;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;
 
#define MSR_SKYLAKE_UNC_CBO_CONFIG  0x00000396
 
typedef union {
  struct {
    UINT32    CBox      : 4;
    UINT32    Reserved1 : 28;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;
 
#define MSR_SKYLAKE_UNC_ARB_PERFCTR0  0x000003B0
 
#define MSR_SKYLAKE_UNC_ARB_PERFCTR1  0x000003B1
 
#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0  0x000003B2
 
#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1  0x000003B3
 
#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0  0x00000700
 
#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1  0x00000701
 
#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0  0x00000706
 
#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1  0x00000707
 
#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0  0x00000710
 
#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1  0x00000711
 
#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0  0x00000716
 
#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1  0x00000717
 
#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0  0x00000720
 
#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1  0x00000721
 
#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0  0x00000726
 
#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1  0x00000727
 
#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0  0x00000730
 
#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1  0x00000731
 
#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0  0x00000736
 
#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1  0x00000737
 
#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL  0x00000E01
 
typedef union {
  struct {
    UINT32    PMI_Sel_Slice0 : 1;
    UINT32    PMI_Sel_Slice1 : 1;
    UINT32    PMI_Sel_Slice2 : 1;
    UINT32    PMI_Sel_Slice3 : 1;
    UINT32    PMI_Sel_Slice4 : 1;
    UINT32    Reserved1      : 14;
    UINT32    Reserved2      : 10;
    UINT32    EN             : 1;
    UINT32    WakePMI        : 1;
    UINT32    FREEZE         : 1;
    UINT32    Reserved3      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;
 
#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS  0x00000E02
 
typedef union {
  struct {
    UINT32    Fixed     : 1;
    UINT32    ARB       : 1;
    UINT32    Reserved1 : 1;
    UINT32    CBox      : 1;
    UINT32    Reserved2 : 28;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;
 
#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE  0x00000080
 
typedef union {
  struct {
    UINT32    Fix_Me_1             : 1;
    UINT32    Reserved             : 17;
    UINT32    ACPIBAR_BASE_ADDRESS : 14;
    UINT32    Fix_Me_2             : 32;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;
 
#define MSR_SKYLAKE_PRMRR_PHYS_BASE  0x000001F4
 
typedef union {
  struct {
    UINT32    MemTypePRMRRBASEMemType : 3;
    UINT32    Reserved1               : 9;
    UINT32    BasePRMRRBaseAddress    : 20;
    UINT32    Fix_Me_1                : 14;
    UINT32    Reserved2               : 18;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;
 
#define MSR_SKYLAKE_PRMRR_PHYS_MASK  0x000001F5
 
typedef union {
  struct {
    UINT32    Reserved1 : 10;
    UINT32    Fix_Me_1  : 1;
    UINT32    VLD       : 1;
    UINT32    Fix_Me_2  : 20;
    UINT32    Fix_Me_3  : 14;
    UINT32    Reserved2 : 18;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;
 
#define MSR_SKYLAKE_PRMRR_VALID_CONFIG  0x000001FB
 
typedef union {
  struct {
    UINT32    Fix_Me_1  : 1;
    UINT32    Reserved1 : 4;
    UINT32    Fix_Me_2  : 1;
    UINT32    Fix_Me_3  : 1;
    UINT32    Fix_Me_4  : 1;
    UINT32    Reserved2 : 24;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;
 
#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE  0x000002F4
 
typedef union {
  struct {
    UINT32    Reserved1 : 12;
    UINT32    Fix_Me_1  : 20;
    UINT32    Fix_Me_2  : 7;
    UINT32    Reserved2 : 25;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;
 
#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK  0x000002F5
 
typedef union {
  struct {
    UINT32    Reserved1 : 10;
    UINT32    Fix_Me_1  : 1;
    UINT32    Fix_Me_2  : 1;
    UINT32    Reserved2 : 20;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;
 
#define MSR_SKYLAKE_RING_RATIO_LIMIT  0x00000620
 
typedef union {
  struct {
    UINT32    Fix_Me_1  : 7;
    UINT32    Reserved1 : 1;
    UINT32    Fix_Me_2  : 7;
    UINT32    Reserved2 : 17;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;
 
#define MSR_SKYLAKE_BR_DETECT_CTRL  0x00000350
 
typedef union {
  struct {
    UINT32    EnMonitoring   : 1;
    UINT32    EnExcept       : 1;
    UINT32    EnLBRFrz       : 1;
    UINT32    DisableInGuest : 1;
    UINT32    Reserved1      : 4;
    UINT32    WindowSize     : 10;
    UINT32    Reserved2      : 6;
    UINT32    WindowCntSel   : 2;
    UINT32    CntAndMode     : 1;
    UINT32    Reserved3      : 5;
    UINT32    Reserved4      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;
 
#define MSR_SKYLAKE_BR_DETECT_STATUS  0x00000351
 
typedef union {
  struct {
    UINT32    BranchMonitoringEventSignaled : 1;
    UINT32    LBRsValid                     : 1;
    UINT32    Reserved1                     : 6;
    UINT32    CntrHit0                      : 1;
    UINT32    CntrHit1                      : 1;
    UINT32    Reserved2                     : 6;
    UINT32    CountWindow                   : 10;
    UINT32    Reserved3                     : 6;
    UINT32    Count0 : 8;
    UINT32    Count1    : 8;
    UINT32    Reserved4 : 16;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;
 
#define MSR_SKYLAKE_PKG_C3_RESIDENCY  0x000003F8
 
#define MSR_SKYLAKE_CORE_C1_RESIDENCY  0x00000660
 
#define MSR_SKYLAKE_CORE_C3_RESIDENCY  0x00000662
 
#define MSR_SKYLAKE_PPIN_CTL  0x0000004E
 
typedef union {
  struct {
    UINT32    LockOut     : 1;
    UINT32    Enable_PPIN : 1;
    UINT32    Reserved1   : 30;
    UINT32    Reserved2   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_PPIN_CTL_REGISTER;
 
#define MSR_SKYLAKE_PPIN  0x0000004F
 
#define MSR_SKYLAKE_PLATFORM_INFO  0x000000CE
 
typedef union {
  struct {
    UINT32    Reserved1              : 8;
    UINT32    MaximumNon_TurboRatio  : 8;
    UINT32    Reserved2              : 7;
    UINT32    PPIN_CAP               : 1;
    UINT32    Reserved3              : 4;
    UINT32    ProgrammableRatioLimit : 1;
    UINT32    ProgrammableTDPLimit   : 1;
    UINT32    ProgrammableTJOFFSET   : 1;
    UINT32    Reserved4              : 1;
    UINT32    Reserved5              : 8;
    UINT32    MaximumEfficiencyRatio : 8;
    UINT32    Reserved6              : 16;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;
 
#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL  0x000000E2
 
typedef union {
  struct {
    UINT32    C_StateLimit                     : 3;
    UINT32    Reserved1                        : 7;
    UINT32    MWAITRedirectionEnable           : 1;
    UINT32    Reserved2                        : 4;
    UINT32    CFGLock                          : 1;
    UINT32    AutomaticC_StateConversionEnable : 1;
    UINT32    Reserved3                        : 8;
    UINT32    C3StateAutoDemotionEnable        : 1;
    UINT32    C1StateAutoDemotionEnable        : 1;
    UINT32    EnableC3Undemotion               : 1;
    UINT32    EnableC1Undemotion               : 1;
    UINT32    CStateDemotionEnable             : 1;
    UINT32    CStateUnDemotionEnable           : 1;
    UINT32    Reserved4                        : 1;
    UINT32    Reserved5                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;
 
#define MSR_SKYLAKE_IA32_MCG_CAP  0x00000179
 
typedef union {
  struct {
    UINT32    Count       : 8;
    UINT32    MCG_CTL_P   : 1;
    UINT32    MCG_EXT_P   : 1;
    UINT32    MCP_CMCI_P  : 1;
    UINT32    MCG_TES_P   : 1;
    UINT32    Reserved1   : 4;
    UINT32    MCG_EXT_CNT : 8;
    UINT32    MCG_SER_P   : 1;
    UINT32    MCG_EM_P    : 1;
    UINT32    MCG_ELOG_P  : 1;
    UINT32    Reserved2   : 5;
    UINT32    Reserved3   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;
 
#define MSR_SKYLAKE_SMM_MCA_CAP  0x0000017D
 
typedef union {
  struct {
    UINT32    Reserved1            : 32;
    UINT32    Reserved2            : 26;
    UINT32    SMM_Code_Access_Chk  : 1;
    UINT32    Long_Flow_Indication : 1;
    UINT32    Reserved3            : 4;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;
 
#define MSR_SKYLAKE_TEMPERATURE_TARGET  0x000001A2
 
typedef union {
  struct {
    UINT32    Reserved1           : 16;
    UINT32    TemperatureTarget   : 8;
    UINT32    TCCActivationOffset : 4;
    UINT32    Reserved2           : 4;
    UINT32    Reserved3           : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;
 
#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES  0x000001AE
 
typedef union {
  struct {
    UINT32    NUMCORE_0 : 8;
    UINT32    NUMCORE_1 : 8;
    UINT32    NUMCORE_2 : 8;
    UINT32    NUMCORE_3 : 8;
    UINT32    NUMCORE_4 : 8;
    UINT32    NUMCORE_5 : 8;
    UINT32    NUMCORE_6 : 8;
    UINT32    NUMCORE_7 : 8;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;
 
#define MSR_SKYLAKE_RAPL_POWER_UNIT  0x00000606
 
typedef union {
  struct {
    UINT32    PowerUnits        : 4;
    UINT32    Reserved1         : 4;
    UINT32    EnergyStatusUnits : 5;
    UINT32    Reserved2         : 3;
    UINT32    TimeUnits         : 4;
    UINT32    Reserved3         : 12;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;
 
#define MSR_SKYLAKE_DRAM_POWER_LIMIT  0x00000618
 
#define MSR_SKYLAKE_DRAM_ENERGY_STATUS  0x00000619
 
typedef union {
  struct {
    UINT32    Energy   : 32;
    UINT32    Reserved : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;
 
#define MSR_SKYLAKE_DRAM_PERF_STATUS  0x0000061B
 
#define MSR_SKYLAKE_DRAM_POWER_INFO  0x0000061C
 
#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT  0x00000620
 
typedef union {
  struct {
    UINT32    MAX_RATIO : 7;
    UINT32    Reserved1 : 1;
    UINT32    MIN_RATIO : 7;
    UINT32    Reserved2 : 17;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;
 
#define MSR_SKYLAKE_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_SKYLAKE_IA32_QM_EVTSEL  0x00000C8D
 
typedef union {
  struct {
    UINT32    EventID   : 8;
    UINT32    Reserved1 : 24;
    UINT32    RMID      : 10;
    UINT32    Reserved2 : 22;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;
 
#define MSR_SKYLAKE_IA32_PQR_ASSOC  0x00000C8F
 
typedef union {
  struct {
    UINT32    RMID      : 10;
    UINT32    Reserved1 : 22;
    UINT32    COS       : 20;
    UINT32    Reserved2 : 12;
  } Bits;
  UINT64    Uint64;
} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;
 
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0   0x00000C90
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1   0x00000C91
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2   0x00000C92
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3   0x00000C93
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4   0x00000C94
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5   0x00000C95
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6   0x00000C96
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7   0x00000C97
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8   0x00000C98
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9   0x00000C99
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10  0x00000C9A
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11  0x00000C9B
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12  0x00000C9C
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13  0x00000C9D
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14  0x00000C9E
#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15  0x00000C9F
 
typedef union {
  struct {
    UINT32    CBM       : 20;
    UINT32    Reserved2 : 12;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;
 
#endif